TWI856788B - Light emitting device - Google Patents

Abstract

A light emitting device is disclosed. The light emitting device includes: a substrate; a semiconductor stack formed on the substrate and including a first type semiconductor layer, a second type semiconductor layer, an active region located between the first type semiconductor layer and the second type semiconductor layer to emit light; a reflective structure formed on the semiconductor stack and including one or multiple openings; and a conductive structure formed on the reflective structure and filling in the one or multiple openings to electrically connected to the second type semiconductor layer; wherein the reflective structure includes a plurality of groups of stack structures, the plurality of groups of stack structures includes a first stack structure, and the first stack structure includes a first sub-layer, a second sub-layer and a third sub-layer sequentially stacking on the semiconductor stack, wherein the first sub-layer has a first optical thickness and a first refractive index, the second sub-layer has a second optical thickness and a second refractive index, the third sub-layer has a third optical thickness and a third refractive index, wherein the first optical thickness > the third optical thickness > the second optical thickness, and the first refractive index < the second refractive index < the third refractive index.

Description

Light-emitting element

This application relates to a light-emitting element, more specifically, to a light-emitting element with enhanced brightness.

Light-emitting diodes (LEDs) in solid-state light-emitting devices have low power consumption, low heat generation, long life, small size, fast response speed and good photoelectric properties, such as stable emission wavelength, so they have been widely used in household appliances, indicator lights and optoelectronic products.

A conventional LED includes a substrate, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer formed on the substrate, as well as p- and n-electrodes formed on the p-type and n-type semiconductor layers, respectively. When the LED is energized through the electrodes and at a forward bias of a specific value, holes from the p-type semiconductor layer and electrons from the n-type semiconductor layer combine in the active region to emit light. However, as LEDs are applied to various optoelectronic products, the brightness specifications of LEDs are also improved. How to improve their brightness is one of the research and development goals of researchers in this technical field.

The present application discloses a light-emitting element, comprising a substrate; a semiconductor stack disposed on the substrate, comprising a first type semiconductor layer, a second type semiconductor layer, and an active region located between the first type semiconductor layer and the second type semiconductor layer for emitting a light; a reflective structure formed on the semiconductor stack and having one or more reflective structure openings; and a conductive structure formed on the reflective structure, filling the one or more reflective structure openings and electrically connected to the second type semiconductor layer; wherein the reflective structure comprises a plurality of A stacking structure, and the plurality of stacking structures include a first stacking structure, the first stacking structure includes a first sublayer, a second sublayer and a third sublayer sequentially stacked on a semiconductor stack, the first sublayer has a first optical thickness and a first refractive index, the second sublayer has a second optical thickness and a second refractive index, the third sublayer has a third optical thickness and a third refractive index, the first optical thickness> the third optical thickness> the second optical thickness, and the first refractive index<the second refractive index<the third refractive index.

1. 1’: Light-emitting element

10: Substrate

10a: Upper surface of substrate

12: Semiconductor stacking

121: Type I semiconductor layer

121a: Upper surface of the first type semiconductor layer

122: Type II semiconductor layer

123: Active layer

18: Transparent conductive layer

18a: Upper surface of transparent conductive layer

180: Transparent conductive layer opening

28: Exposed area

20: First contact layer

21: First protective layer

210: First protective layer opening

212: Second first protective layer opening

214: Third first protective layer opening

23: Second protective layer

230: Openings of the first and second protective layers

232: Second protective layer opening

234: Opening of the third and second protective layers

25: The third protective layer

251: Openings of the first and third protective layers

252: Second and third protective layer openings

30: Second contact layer

36: Conductive structure

360: Conductive structure opening

40: Middle layer

40a: Upper surface of the middle layer

401: First middle layer opening

402: Second middle layer opening

50:Reflection structure

51, 51’: stacking structure

51a, 51b, 51c: first sublayer, second sublayer, third sublayer

501: First reflection structure opening

502: Second reflection structure opening

80a: first welding pad

80b: Second welding pad

D1, D2: first distance, second distance

MS: High platform

P1, E1, O1: curves

R1: Wedge-shaped part

R2: Platform Department

R3: Connection part

t1, t2, t3: first thickness, second thickness, third thickness

W1, W2, W3, W4: first side wall, second side wall, third side wall, fourth side wall

θ1: sharp angle

[Figure 1] shows a top view of the light-emitting element 1 of the first embodiment of the present application.

[Figure 2A] shows a cross-sectional view of a light-emitting element 1 of an embodiment of the present application.

[Figure 2B] shows a partial enlarged cross-sectional view of a light-emitting element 1 in an embodiment of the present application.

[Figure 2C] shows a partial enlarged cross-sectional view of a light-emitting element 1 in an embodiment of the present application.

[Figure 3A] shows a cross-sectional view of a light-emitting element 1' in an embodiment of the present application.

[Figure 3B] shows a partial enlarged cross-sectional view of a light-emitting element 1' in an embodiment of the present application.

[Figure 4] shows the reflectivity curves of the light-emitting element 1 of the first embodiment of the present application and the light-emitting element of the comparative example.

Hereinafter, the exemplary embodiments of the present invention will be described in detail with reference to the diagrams, so that the technical personnel in the field of the present invention can fully understand the spirit of the present invention. The present invention is not limited to the following embodiments, but can be implemented in other forms. In this specification, there are some identical symbols, which represent components with the same or similar structures, functions, and principles, and can be inferred by those with general knowledge in the industry based on the teachings of this specification. For the sake of brevity in the specification, components with the same symbols will not be repeated.

FIG1 shows a top view of a light-emitting element 1 of an embodiment of the present application. FIG2A shows a cross-sectional view along the line segment A-A' in FIG1. The light-emitting element 1 includes a substrate 10, a semiconductor stack 12, one or more exposed areas 28, a first protective layer 21, a reflective structure 50, a second protective layer 23, a first contact layer 20, a second contact layer 30, a third protective layer 25, a first pad 80a, and a second pad 80b. In one embodiment, the light-emitting element 1 may include a transparent conductive layer 18 located on the second type semiconductor layer 122, between the second type semiconductor layer 122 and the reflective structure 50.

In detail, the semiconductor stack 12 is located on the substrate 10, and includes a first type semiconductor layer 121, a second type semiconductor layer 122, and an active region 123 located between the first type semiconductor layer 121 and the second type semiconductor layer 122. The exposed region 28 includes a peripheral region and an internal region respectively located in the semiconductor stack 12, and exposes an upper surface 121a of the first type semiconductor layer. The exposed region 28 includes a side wall and a bottom, and the bottom is formed by the exposed upper surface 121a of the first type semiconductor layer. The first protective layer 21 covers a portion of the upper surface 121a of the first type semiconductor layer in the exposed region 28, and extends to cover a portion of the upper surface of the second type semiconductor layer 122. In other words, the first protective layer 21 contacts a portion of the bottom and sidewalls of the exposed region 28, and a portion of the upper surface of the second type semiconductor layer 122. In another embodiment, around the semiconductor stack 12, the first protective layer 21 further extends to cover the sidewalls of the first type semiconductor layer 121 connected to the upper surface 10a of the substrate (not shown). The first protective layer 21 includes one or more first first protective layer openings 210 and one or more second first protective layer openings 212. The first first protective layer openings 210 are located on the second type semiconductor layer 122 to expose the second type semiconductor layer 122 and/or the transparent conductive layer 18. The second first protective layer openings 212 are located on the exposed area 28 in the inner area of the semiconductor stack 12 and expose the upper surface 121a of the first type semiconductor layer. In one embodiment, the transparent conductive layer 18 is located in the first first protective layer opening 210 and extends onto the first protective layer 21. The reflective structure 50 is located on the transparent conductive layer 18 or the second type semiconductor layer 122, and includes one or more first reflective structure openings 501 formed corresponding to the exposed area 28 and the transparent conductive layer opening 180, and one or more second reflective structure openings 502 exposing the transparent conductive layer 18 and/or the second type semiconductor layer 122. The conductive structure 36 is located on the reflective structure 50, and is electrically connected to the transparent conductive layer 18 and/or the second type semiconductor layer 122 through the reflective structure openings 502. In one embodiment (not shown), the reflective structure 50 includes a plurality of island structures distributed on the second type semiconductor layer 122, and the conductive structure 36 is electrically connected to the transparent conductive layer 18 and the second type semiconductor layer 122 through the gaps between the island structures. The second protective layer 23 is formed on the first protective layer 21, extending from the exposed area 28 to cover the conductive structure 36. The second protective layer 23 includes one or more first and second protective layer openings 230 located on the conductive structure 36, and a portion of the conductive structure 36 is exposed through the first and second protective layer openings 230. In addition, the second protective layer 23 includes one or more second second protective layer openings 232 respectively located on the exposed area 28 in the inner area of the semiconductor stack 12, and the first type semiconductor layer upper surface 121a is exposed through the second second protective layer openings 232. In one embodiment, the first protective layer 21 and the second protective layer 23 respectively include one or more third first protective layer openings 214 and one or more third second protective layer openings 234 located in the exposed area 28 in the surrounding area of the semiconductor stack 12, and the first type semiconductor layer upper surface 121a is exposed through the third first protective layer openings 214 and the third second protective layer openings 234. In one embodiment, a plurality of third first protective layer openings 214 and a plurality of third second protective layer openings 234 can be disposed at intervals on the exposed area 28 located in the area surrounding the semiconductor stack 12. In one embodiment, since the second protective layer 23 covers the sidewalls of the exposed area 28, that is, the sidewalls of the semiconductor stack 12, the semiconductor stack 12 can be protected to avoid possible damage to the semiconductor stack 12 or short circuit caused by heterogeneous electrical contact in subsequent processes. In another embodiment, around the semiconductor stack 12, the second protective layer 23 further covers the sidewalls of the first type semiconductor layer 121 below the exposed area 28.

In one embodiment, the exposed area 28 can be formed by removing part of the second type semiconductor layer 122, the active layer 123 and the first type semiconductor layer 121 to expose the upper surface 121a of the first type semiconductor layer 121. As shown in FIG1 , relative to the exposed area 28, the semiconductor stack 12 in other areas forms a mesa MS. In this embodiment, the exposed area 28 includes a surrounding area surrounding the mesa MS around the semiconductor stack 12 and an internal area distributed in the mesa MS. In one embodiment of the first type semiconductor, see FIG1 , the contour of the mesa MS includes a plurality of convex portions and a plurality of concave portions arranged at intervals. In one embodiment, the contour of the mesa MS with the plurality of convex portions and the plurality of concave portions arranged is wavy. In other embodiments, from the top view, the profile of the mesa MS includes a sawtooth shape, a square wave shape or other non-linear patterns. In one embodiment, a plurality of recesses are provided corresponding to the third first protective layer opening 214 and the third second protective layer opening 234. The recesses of the mesa MS profile can increase the area of the surrounding area of the exposed area 28, thereby increasing the contact area between the contact layer 20 and the exposed area 28 to improve current injection. In addition, the mesa MS profile can increase the lateral light extraction area. However, the increase of the concave portion will also cause the loss of the luminous area. Therefore, the pattern design of the high-platform MS profile can be optimized by considering the contact area between the contact layer 20 and the surrounding area of the exposed area 28, as well as the loss of the luminous area. The pattern design of the high-platform MS profile can improve the current injection while maintaining the optimal luminous area, and can improve the light extraction efficiency of the light-emitting element 1.

The first contact layer 20 and the second contact layer 30 are formed on the semiconductor stack 12. The first contact layer 20 covers the first protection layer 21 and the second protection layer 23, and is electrically connected to the first type semiconductor layer 121 through the second first protection layer opening 212, the third first protection layer opening 214, the second second protection layer opening 232, and the third second protection layer opening 234. The second contact layer 30 is separated from the first contact layer 20, contacts the conductive structure 36 through the first second protection layer opening 230, and is electrically connected to the second type semiconductor layer 122. In one embodiment, the second contact layer 30 is located in the first second protection layer opening 230. In another embodiment, the second contact layer 30 is located in the first and second protective layer openings 230 and further extends onto the second protective layer 23. The third protective layer 25 is located on the first contact layer 20 and the second contact layer 30, and includes one or more first and third protective layer openings 251 to expose the first contact layer 20, and one or more second and third protective layer openings 252 to expose the second contact layer 30. The third protective layer 25 further covers the sidewalls around the semiconductor stack 12 and the upper surface 10a of the substrate. The first pad 80a is located in the first and third protective layer openings 251 and contacts the first contact layer 20. The second pad 80b is located in the second-third protective layer opening 252 and contacts the second contact layer 30. In another embodiment, the first pad 80a and the second pad 80b are located in the first-third protective layer opening 251 and the second-third protective layer opening 252, respectively, and extend onto the third protective layer 25. The second pad 80b and the second contact layer 30 can form a second contact structure electrically connected to the second type semiconductor layer 122. The first pad 80a and the first contact layer 20 can form a first contact structure electrically connected to the first type semiconductor layer 121. The first contact structure is formed on the reflective structure 50 and is electrically connected to the first type semiconductor layer 121 through the second first protective layer opening 212, the third first protective layer opening 214, the second second protective layer opening 232 and the third second protective layer opening 234. The second contact structure is electrically connected to the second type semiconductor layer 122 through the first second protective layer opening 230.

In one embodiment, the substrate 10 may be a growth substrate, including a gallium arsenide (GaAs) substrate and a gallium phosphide (GaP) substrate for growing gallium indium phosphide (AlGaInP), or a sapphire (Al ₂ O ₃ ) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, and an aluminum nitride (AlN) substrate for growing gallium indium nitride (InGaN) or aluminum gallium nitride (AlGaN). The substrate 10 includes a substrate upper surface 10a. The substrate 10 may be a patterned substrate, that is, the substrate upper surface 10a has a patterned structure (not shown). In one embodiment, light emitted from the semiconductor stack 12 may be refracted by the patterned structure of the substrate 10, thereby increasing the brightness of the light-emitting element. In addition, the patterned structure reduces or suppresses the misalignment between the substrate 10 and the semiconductor stack 12 due to lattice mismatch, thereby improving the epitaxial quality of the semiconductor stack 12.

In one embodiment, the semiconductor stack 12 may further include a buffer structure (not shown), and the buffer structure, the first type semiconductor layer 121, the active region 123 and the second type semiconductor layer 122 are sequentially formed on the substrate 10. The buffer structure can reduce the above-mentioned lattice mismatch and suppress dislocation, thereby improving the epitaxial quality. The material of the buffer layer includes GaN, AlGaN or AlN. In one embodiment, the buffer structure includes a plurality of sublayers (not shown). The sublayers include the same material or different materials. In one embodiment, the buffer structure includes two sublayers, wherein the growth method of the first sublayer is sputtering, and the growth method of the second sublayer is MOCVD. In one embodiment, the buffer layer further includes a third sublayer. The growth method of the third sublayer is MOCVD, and the growth temperature of the second sublayer is higher or lower than the growth temperature of the third sublayer. In one embodiment, the first, second and third sublayers include the same material, such as AlN, or different materials, such as AN, GaN, AlGaN. In one embodiment of the present application, the first type semiconductor layer 121 and the second type semiconductor layer 122, such as a cladding layer or a confinement layer, have different conductivity types, electrical properties, polarities or doping elements for providing electrons or holes. For example, the first type semiconductor layer 121 is an n-type semiconductor, and the second type semiconductor layer 122 is a p-type semiconductor. The active region 123 is formed between the first type semiconductor layer 121 and the second type semiconductor layer 122. Electrons and holes combine in the active region 123 under the drive of electric current, converting electrical energy into light energy to emit light. The wavelength of light emitted by the light-emitting element 1 or the semiconductor stack 12 can be adjusted by changing the physical properties and chemical composition of one or more layers in the semiconductor stack 12.

x，y

1；x+y

1。根據活性區域123的材料，當活性區域123的材料是AlInGaP系列時，可以發出波長介於610nm和650nm之間的紅光或波長介於550nm和570nm之間的黃光。當活性區域123的材料是InGaN 系列時，可以發出波長介於400nm和490nm之間的藍光或深藍光或波長介於490nm和550nm之間的綠光。當活性區域123的材料是AlGaN系列時，可以發出波長介於400nm和250nm之間的UV光。活性區域123可以是單異質結構(single heterostructure；SH)、雙異質結構(double heterostructure；DH)、雙面雙異質結構(double-side double heterostructure；DDH)、多重量子井(multi-quantum well；MQW)。活性區域123的材料可以是i型、p型或n型半導體。於一實施例中，在基板10上形成半導體疊層12的方法包含有機金屬化學氣相沉積(MOCVD)、分子束磊晶法(MBE)、氫化物氣相磊晶(HVPE)或離子鍍，例如濺鍍或蒸鍍等。 The material of the _{semiconductor} stack 12 includes a III-V semiconductor material of _{AlxInyGa (1-xy) N} or _{AlxInyGa (1-xy)} P, wherein 0

x,y

1; x+y

1. Depending on the material of the active region 123, when the material of the active region 123 is AlInGaP series, red light with a wavelength between 610nm and 650nm or yellow light with a wavelength between 550nm and 570nm can be emitted. When the material of the active region 123 is InGaN series, blue light or deep blue light with a wavelength between 400nm and 490nm or green light with a wavelength between 490nm and 550nm can be emitted. When the material of the active region 123 is AlGaN series, UV light with a wavelength between 400nm and 250nm can be emitted. The active region 123 may be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW). The material of the active region 123 may be an i-type, p-type, or n-type semiconductor. In one embodiment, the method of forming the semiconductor stack 12 on the substrate 10 includes metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydrogen vapor phase epitaxy (HVPE), or ion plating, such as sputtering or evaporation.

The first protective layer 21, the second protective layer 23 and the third protective layer 25 are transparent to the light emitted by the semiconductor stack 12, and are made of non-conductive materials, including organic materials or inorganic materials. The organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, polyimide or fluorocarbon polymer. Inorganic materials include, for example, silicone, glass, or dielectric materials. Dielectric materials include, for example, silicon oxide ( _SiOx ), silicon nitride ( _SiNx ), silicon oxynitride ( _SiOxNy ), niobium oxide ( _Nb2O5 ), helium oxide ( _HfO2 ), titanium oxide ( _TiOx ), magnesium fluoride ( _MgF2 ), aluminum oxide ( _Al2O3 ), _etc. The first protective layer 21, _{the second} protective layer 23, and the third protective layer 25 can be the same material or different materials. The first protective layer 21, the second protective layer 23 and the third protective layer 25 are formed by atomic layer deposition (ALD), sputtering, evaporation and spin-coating, etc. The first protective layer 21, the second protective layer 23 and the third protective layer 25 can be formed by the same or different methods. The openings of the first protective layer 21, the second protective layer 23 and the third protective layer 25 are formed by dry etching, wet etching or lift-off, etc. The openings of the first protective layer 21, the second protective layer 23 and the third protective layer 25 can be formed by the same or different methods.

As shown in FIG. 2A , the transparent conductive layer 18 covers the upper surface of the second type semiconductor layer 122 and is in electrical contact with the second type semiconductor layer 122, and includes one or more transparent conductive layer openings 180 formed corresponding to the exposed area 28. The transparent conductive layer 18 can be a metal or a transparent conductive material, wherein the metal can be selected from a thin metal layer with light transmittance, and the transparent conductive material is transparent to the light emitted by the active layer 123, including graphene, indium tin oxide (ITO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc oxide (ZnO) or indium zinc oxide (IZO) and other materials. In one embodiment, the transparent conductive layer 18 covers a portion of the first protective layer 21. In another embodiment. The transparent conductive layer 18 does not cover the first protective layer 21. In another embodiment, the transparent conductive layer 18 may be formed first, and then the first protective layer 21 may be formed, and the first protective layer 21 may cover part of the transparent conductive layer 18 or may not cover the transparent conductive layer 18. In one embodiment, the first protective layer 21 is formed between the transparent conductive layer 18 and the reflective structure 50, and the transparent conductive layer 18 is exposed.

As shown in FIG. 1 and FIG. 2A , the first contact layer 20 covers the second protection layer 23, and electrically connects the first type semiconductor layer 121 and the second type semiconductor layer 122 through the second second protection layer opening 232 and the third second protection layer opening 234 of the second protection layer 23. The first contact layer 20 and the second contact layer 30 include metal materials, such as aluminum (Al), chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), or alloys or stacks of the above materials. The first pad 80a and the second pad 80b are formed in the first and third protective layer openings 251 and the first and third protective layer openings 252, respectively, and are electrically connected to the first type semiconductor layer 121 and the second type semiconductor layer 122 respectively by contacting the first contact layer 20 and the second contact layer 30. The first pad 80a and the second pad 80b include metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), etc., or a stack or alloy of the above materials. The first pad 80a and the second pad 80b can be composed of a single layer or multiple layers. For example, the first pad 80a and the second pad 80b may include Ti/Au, Ti/Pt/Au, Cr/Au, Cr/Pt/Au, Ni/Au, Ni/Pt/Au or Cr/Al/Cr/Ni/Au. In one embodiment, the first pad 80a and the second pad 80b are flip-chip bonded to a circuit on a carrier (not shown) to achieve connection with an external electronic component or an external power source. In another embodiment, the first pad 80a and/or the second pad 80b may extend to cover the third protective layer 25. In another embodiment, the area where the first pad 80a and/or the second pad 80b are located can avoid the exposed area 28 and be distributed in the inner area of the semiconductor stack 12 to avoid the peeling of the interfaces between the pads and the semiconductor stack 12 due to the height difference. In one embodiment, the surfaces of the first pad 80a and the second pad 80b have a plurality of recesses (not shown) corresponding to the second reflective structure opening 502. Through these recesses, the bonding force between the pads and the carrier can be improved in the subsequent packaging process to improve the process yield.

FIG2B shows a partial enlarged cross-sectional view of the portion marked C1 in FIG2A , and the reflective structure 50 includes a plurality of stacked structures 51. In one embodiment, as shown in FIG2B , the reflective structure 50 includes one or more stacked structures 51, and the stacked structures 51 sequentially include a first sublayer 51a, a second sublayer 51b, and a third sublayer 51c. In one embodiment, the reflective structure 50 includes one or more stacked structures 51 and one or more stacked structures 51', wherein the stacked structure 51' is composed of only any two stacked layers of the first sublayer 51a, the second sublayer 51b, and the third sublayer 51c. 2C , the reflective structure 50 includes at least two stacked structures 51 formed by stacking a first sublayer 51a, a second sublayer 51b, and a third sublayer 51c in sequence, and a stacked structure 51′ formed by stacking a first sublayer 51a and a second sublayer 51b in sequence. In one embodiment, the stacked structure 51′ may be plural. In one embodiment, the stacked structure 51′ may be formed by stacking a first sublayer 51a and a third sublayer 51c in sequence, or by stacking a second sublayer 51b and a third sublayer 51c in sequence. In one embodiment, the first sublayer 51a, the second sublayer 51b and the third sublayer 51c are formed of dielectric materials, and the dielectric materials include silicon-containing materials, such as silicon oxide ( _SiOx ), _silicon nitride ( _SiNx ), or silicon oxynitride ( _SiOxNy ), metal oxides, such as niobium oxide ( _Nb2O5 ), _niobium oxide ( _HfO2 ), titanium oxide ( _TiOx ), _or aluminum oxide ( _Al2O3 ), and metal fluorides, such as magnesium fluoride ( _MgF2 ). The reflective structure 50 is formed by stacking materials with different refractive indexes and designing their thicknesses, and provides a reflective function for light in a specific wavelength range emitted by the active region 123, such as a distributed Bragg reflector (DBR). In this embodiment, the first sublayer 51a has a first refractive index, the second sublayer 51b has a second refractive index, and the third sublayer 51c has a third refractive index, wherein the first refractive index < the second refractive index < the third refractive index. The thickness of each sublayer can be adjusted according to its stacking order and refractive index. In one embodiment, the first sublayer 51a has a first optical thickness, the second sublayer 51b has a second optical thickness, and the third sublayer 51c has a third optical thickness, wherein the first optical thickness> the third optical thickness> the second optical thickness. In one embodiment, the material of the first sublayer 51a includes silicon oxide, whose refractive index is approximately between 1.4 and 1.6, such as silicon dioxide (SiO ₂ ), the material of the second sublayer 51b includes aluminum oxide, whose refractive index is approximately between 1.6 and 1.8, such as aluminum oxide (Al ₂ O ₃ ), and the material of the third sublayer 51c includes titanium oxide, whose refractive index is approximately between 2.4 and 2.6, such as titanium dioxide (TiO ₂ ). In one embodiment, when the reflective structure 50 includes at least one first stacked structure 51 including a first sublayer 51a, a second sublayer 51b and a third sublayer 51c stacked in sequence, the reflective structure 50 may further include a stacked structure 51' in which any two sublayers are stacked in sequence to optimize the optical effect of the reflective structure 50. In one embodiment, the stacked structure closest to the conductive structure 36 in the reflective structure 50 is the stacked structure 51', wherein the sublayer in contact with the conductive structure 36 has a greater adhesion to the conductive structure 36 than other sublayers. By selecting the material of the sublayer in contact with the conductive structure 36, the adhesion between the conductive structure 36 and the reflective structure 50 can be increased to improve the reliability of the light-emitting element. In one embodiment, the second sublayer 51b has better adhesion to the conductive structure 36, and its material is, for example, aluminum oxide. In one embodiment, any stacked structure 51' consisting of two sub-layers stacked in sequence can be located between any two stacked structures 51 consisting of three sub-layers stacked in sequence, or between the stacked structure 51 and the transparent conductive layer 18 or the second type semiconductor layer 122, to optimize the optical effect of the reflective structure 50. The reflective structure 50 is formed by atomic layer deposition (ALD), sputtering, evaporation, and spin-coating. The opening of the reflective structure 50 is formed by dry etching, wet etching, or lift-off.

FIG2C shows a partial enlarged cross-sectional view of the portion marked C2 in FIG2A . The reflective structure 50 has a first side wall W1 at a position corresponding to the second reflective structure opening 502. The transparent conductive layer 18 located below the reflective structure 50 has a transparent conductive layer upper surface 18a, and an acute angle θ1 is sandwiched between the first side wall W1 and the transparent conductive layer upper surface 18a. In one embodiment, the acute angle θ1 is between 10 degrees and 45 degrees. Since the reflective structure 50 is composed of a stacked structure 51, compared to a general distributed Bragg reflector, it has a greater selection of materials with different refractive indices and can be used to adjust the optical thickness of each sublayer, thereby obtaining a reflective structure 50 that is thinner than a general distributed Bragg reflector, so that the reflective structure 50 is less likely to generate cracks due to stress. In addition, in the subsequent patterning process, a thicker lift-off process that cannot be used in a general distributed Bragg reflector can be selected, so that the transparent conductive layer 18 below is less likely to be damaged by etching. In one embodiment, the thickness of the second sublayer 51b is 0 to 0.5 times that of the first sublayer 51a and/or the third sublayer 51c. In one embodiment, when the thickness of the second sublayer 51b is 0 times that of the first sublayer 51a and/or the third sublayer 51c, a stacked structure 51' is formed in which the first sublayer 51a and the third sublayer 51c are stacked in sequence. After the reflective structure opening 502 is formed in the reflective structure 50 by a patterning process such as etching or lift-off, an acute angle θ1 is sandwiched between the first side wall W1 and the upper surface 18a of the transparent conductive layer, so that the conductive structure 36 can be smoothly coated on the reflective structure 50, and then form a good electrical connection with the transparent conductive layer 18 and/or the second type semiconductor layer 122. In one embodiment, the reflective structure 50 can be directly formed on the second type semiconductor layer 122, so there is an acute angle between the first side wall W1 of the reflective structure 50 and the upper surface of the second type semiconductor layer 122.

As shown in FIG. 2C , the reflective structure 50 has a wedge-shaped portion R1, a platform portion R2, and a connecting portion R3 connecting the wedge-shaped portion R1 and the platform portion R2, wherein the wedge-shaped portion R1 is adjacent to the second reflective structure opening 502 and has an acute angle θ1 between it and the upper surface 18a of the transparent conductive layer, and the platform portion R2 is far from the second reflective structure opening 502 and has substantially the same thickness as a whole, and has an upper surface substantially parallel to the upper surface 18a of the transparent conductive layer. The connecting portion R3 is located between the wedge portion R1 and the platform portion R2 and has a gradually increasing thickness from the wedge portion R1 to the platform portion R2, wherein the first sublayer 51a has a first thickness t1 at the wedge portion R1, a second thickness t2 at the platform portion R2, and a third thickness t3 at the connecting portion R3, the first thickness t1<third thickness t3<second thickness t2, and the thickness of the first sublayer 51a gradually increases from the position adjacent to the second reflective structure opening 502 to the position away from the second reflective structure opening 502, so that the conductive structure 36 can be smoothly coated on the reflective structure 50 to contact the transparent conductive layer 18 or the second type semiconductor layer 122 and form a good electrical connection with the second type semiconductor layer 122.

Please refer to FIG. 2A again. The conductive structure 36 is formed on the transparent conductive layer 18 and the reflective structure 50. The conductive structure 36 is electrically connected to the transparent conductive layer 18 and the second semiconductor layer 122 through the second reflective structure opening 502 of the reflective structure 50. The conductive structure 36 includes a plurality of conductive structure openings 360 corresponding to the positions of the first reflective structure opening 501 and the exposed area 28 of the reflective structure 50. In one embodiment, the conductive structure 36 includes a metal structure, which may include a single layer of metal or a stack formed by a plurality of layers of metal. The conductive structure 36 and the reflective structure 50 form an omnidirectional reflector (ODR) to enhance the reflection of light and the brightness of the light-emitting element 1. In one embodiment, for light with a peak wavelength between 400 nm and 700 nm emitted from the active region 123, the omnidirectional reflector formed by the conductive structure 36 and the reflective structure 50 has a reflectivity of more than 90%. In one embodiment, the conductive structure 36 includes a barrier layer (not shown) and a reflective layer (not shown), the barrier layer is formed and covers the reflective layer, and the barrier layer can prevent the migration, diffusion or oxidation of the metal elements of the reflective layer. The material of the reflective layer includes a metal material with high reflectivity for light emitted by the semiconductor stack 12, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), ruthenium (Ru), or alloys or stacks of the above materials. The material of the barrier layer includes chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), or alloys or stacks of the above materials. In one embodiment, when the barrier layer is a metal stack, the barrier layer is formed by alternately stacking two or more metal layers, such as Cr/Pt, Cr/Ti, Cr/TiW, Cr/W, Cr/Zn, Ti/Pt, Ti/W, Ti/TiW, Ti/Zn, Pt/TiW, Pt/W, Pt/Zn, TiW/W, TiW/Zn, or W/Zn, etc.

In one embodiment, by inserting a second sublayer 51b having a refractive index between the first sublayer 51a and the third sublayer 51c between the first sublayer 51a and the third sublayer 51c, the interference phenomenon caused by the excessive difference in refractive index of the stacked layers of the general distributed Bragg reflector can be reduced, so that the omnidirectional reflector formed by the conductive structure 36 and the reflective structure 50 can have a reflectivity of more than 90% for the light in the specific wavelength range emitted by the active area 123, and also make the omnidirectional reflector formed by the conductive structure 36 and the reflective structure 50 have good reflectivity at all angles. For example, FIG. 4 shows a wavelength-to-wavelength reflectivity curve of the light-emitting element 1 of the first embodiment of the present application, the first comparative light-emitting element, and the second comparative light-emitting element. The structures of the light-emitting element 1, the first comparative light-emitting element, and the second comparative light-emitting element are similar, except that the light-emitting element of the first comparative example has only the conductive structure 36 (i.e., there is no reflective structure 50 under the conductive structure 36), and the light-emitting element of the second comparative example is a general distributed Bragg inversion structure composed of a stacked structure of the conductive structure 36 and two sub-layers. Curve O1 is the reflectivity of the first comparative light emitting element for light with a peak wavelength between 380 nm and 780 nm, curve P1 is the reflectivity of the second comparative light emitting element for light with a peak wavelength between 380 nm and 780 nm, and curve E1 is the reflectivity of the omnidirectional reflector formed by the conductive structure 36 and the reflective structure 50 of the light emitting element 1 of the present embodiment for light with a peak wavelength between 380 nm and 780 nm. Due to the interference phenomenon caused by the large refractive index difference of the stacked layers of the general distributed Bragg reflector, the reflectivity of the curve P1 of the second comparative example light-emitting element drops sharply at a wavelength close to 400 nanometers; from the reflectivity curve O1 of the first comparative example light-emitting element, although there is no sharp drop in reflectivity at a wavelength close to 400 nanometers due to the interference phenomenon of the curve P1, its reflectivity below 580 nanometers is lower than that of the second comparative example light-emitting element and light-emitting element 1; and from the curve E1 of the light-emitting element 1, there is no sharp drop in reflectivity due to the interference phenomenon, and the reflectivity between 400 nanometers and 780 nanometers can reach more than 90%.

FIG3A shows a cross-sectional view of a light-emitting element 1′ of an embodiment of the present application, and FIG3B shows a partial enlarged cross-sectional view of a portion marked C3 in FIG3A. However, the description of the elements with the same symbols has been described in the previous description of FIG1 and FIG2A-2C, so it is not repeated here. The difference is that the light-emitting element 1′ further includes an intermediate layer 40 formed between the second type semiconductor layer 122 and/or the transparent conductive layer 18 and the reflective structure 50, wherein the intermediate layer 40 includes one or more first intermediate layer openings 401 and one or more second intermediate layer openings 402. The position of the first intermediate layer opening 401 corresponds to the exposed area 28 and the transparent conductive layer opening 180. The second intermediate layer opening 402 is distributed on the second type semiconductor layer 122 and/or the transparent conductive layer 18, and is formed corresponding to the positions of a plurality of second reflective structure openings 502, respectively, and exposes the second type semiconductor layer 122 and/or the transparent conductive layer 18 thereunder. In one embodiment, around the semiconductor stack 12, the intermediate layer 40 further covers the sidewalls of the first type semiconductor layer 121.

The intermediate layer 40 is transparent to the light emitted by the semiconductor stack 12, and its material is a non-conductive material, including organic materials or inorganic materials. The organic materials include Su8, benzocyclobutene, perfluorocyclobutane, epoxy resin, acrylic resin, cycloolefin polymer, polymethyl methacrylate, polyethylene terephthalate, polycarbonate, polyetherimide, polyimide or fluorocarbon polymer. The inorganic material includes, for example, silicone, glass or dielectric material, and the dielectric material is, for example, silicon oxide, silicon nitride, silicon oxynitride, niobium oxide, niobium oxide, titanium oxide, magnesium fluoride, aluminum oxide, etc. The intermediate layer 40 is formed by atomic deposition, sputtering, evaporation and spin coating. The opening of the intermediate layer 40 may be formed by dry etching, wet etching or lift-off. In one embodiment, when the reflective structure 50 is etched, such as dry etching, to form the second reflective structure opening 502, the intermediate layer 40 may be used as an etching stopper to prevent the etching from damaging the second type semiconductor layer 122 and/or the transparent conductive layer 18 thereunder. In one embodiment, after the second reflective structure opening 502 is formed, a second intermediate layer opening 402 may be formed in the intermediate layer 40 to expose the second type semiconductor layer 122 and/or the transparent conductive layer 18 by the same or different etching method, such as wet etching. The second intermediate layer opening 402 is formed below the second reflective structure opening 502 corresponding thereto. In one embodiment, the intermediate layer 40 can be formed of the same material as the first protective layer 21, such as silicon oxide. In one embodiment, the intermediate layer 40 can be formed on the transparent conductive layer 18 in the same process as the first protective layer 21. In one embodiment, the intermediate layer 40 can be formed of the same material as the second sublayer 51b, such as aluminum oxide, and the intermediate layer 40 can be used to increase the adhesion of the conductive structure 36 and the reflective structure 50 as a whole.

3B , the intermediate layer 40 is formed on the transparent conductive layer 18 and has a second intermediate layer opening 402 exposing the transparent conductive layer 18. In one embodiment, the intermediate layer 40 can be directly formed on the second type semiconductor layer 122. The reflective structure 50 is formed on the intermediate layer 40 and has a second reflective structure opening 502 corresponding to the second intermediate layer opening 402 of the intermediate layer 40. The reflective structure 50 has a first side wall W1 at a position corresponding to the second reflective structure opening 502, the intermediate layer 40 has an intermediate layer upper surface 40a at a position corresponding to the second intermediate layer opening 502, the intermediate layer 40 has a second side wall W2 at a position corresponding to the second intermediate layer opening 402, the first side wall W1 of the reflective structure 50 is located on the intermediate layer upper surface 40a and is located on the same side as the second side wall W2 of the intermediate layer 40, and has a first distance D1 between the first side wall W1 and the second side wall W2. The reflective structure 50 has a third side wall W3 located on the upper surface 40a of the middle layer at a position corresponding to the second reflective structure opening 502 relative to the other side of the first side wall W1, and the middle layer 40 has a fourth side wall W4 at a position corresponding to the second middle layer opening 402 and is located on the same side as the third side wall W3 of the reflective structure 50, and has a second distance D2 between the third side wall W3, wherein the first distance D1 and the second distance D2 may be the same or different. In one embodiment, the minimum distance between the first sidewall W1 and the third sidewall W3 of the reflective structure 50 is defined as the first width of the second reflective structure opening 502, and the minimum distance between the second sidewall W2 and the fourth sidewall W4 of the intermediate layer 40 is defined as the second width of the second intermediate layer opening 402, and the first width is greater than the second width. In one embodiment, the first sidewall W1 and the third sidewall W3 of the reflective structure 50 have the same inner angle or different inner angles with the intermediate layer upper surface 40a. In one embodiment, the second sidewall W2 and the fourth sidewall W4 of the intermediate layer 40 have the same inner angle or different inner angles with the transparent conductive layer upper surface 18a. In one embodiment, the first side wall W1 of the reflective structure 50 and the upper surface 40a of the intermediate layer and the second side wall W2 of the intermediate layer 40 and the upper surface 18a of the transparent conductive layer respectively have the same inner angle or different inner angles. In one embodiment, the third side wall W3 of the reflective structure 50 and the upper surface 40a of the intermediate layer and the fourth side wall W4 of the intermediate layer 40 and the upper surface 18a of the transparent conductive layer respectively have the same inner angle or different inner angles.

However, the above embodiments are only for illustrative purposes to illustrate the principles and effects of this application, and are not intended to limit this application. Anyone with common knowledge in the technical field to which this application belongs can modify and change the above embodiments without violating the technical principles and spirit of this application. For example, all equivalent changes and modifications made according to the shape, structure, features and spirit described in the patent scope of this application should be included in the patent scope of this application.

18: Transparent conductive layer

18a: Upper surface of transparent conductive layer

36: Conductive structure

50:Reflection structure

51, 51’: stacking structure

51a: First sublayer

51b: Second sublayer

51c: The third sublayer

502: Second reflection structure opening

R1: Wedge-shaped part

R2: Platform Department

R3: Connection part

t1, t2, t3: first thickness, second thickness, third thickness

W1: First side wall

θ 1: sharp angle

Claims (10)

A light-emitting element comprises: a semiconductor stack, comprising a first type semiconductor layer, a second type semiconductor layer, and an active layer located between the first type semiconductor layer and the second type semiconductor layer for emitting a light; a reflective structure formed on the semiconductor stack, the reflective structure comprising a stacked structure and having an opening, the stacked structure comprising a plurality of sub-layers; and a conductive structure formed on the reflective structure, electrically connected to the second type semiconductor layer through the opening; wherein the material of a sub-layer of the stacked structure that contacts the conductive structure at the outermost side comprises aluminum oxide, wherein the adhesion between the sub-layer and the conductive structure is greater than the adhesion between the other layers of the plurality of sub-layers and the conductive structure. The light-emitting element as described in claim 1 further comprises an intermediate layer formed between the semiconductor stack and the reflective structure, wherein the intermediate layer has an intermediate layer opening corresponding to the opening of the reflective structure. The light-emitting element as described in claim 2, wherein the opening has a first width, the middle layer opening has a second width, and the first width is greater than the second width. The light-emitting element as described in claim 2, wherein the reflective structure has a first side wall, the intermediate layer has a second side wall and an intermediate layer upper surface, and the first side wall is located on the intermediate layer upper surface and has a distance from the second side wall. A light-emitting element as described in claim 2, wherein the material of the intermediate layer comprises aluminum oxide or silicon oxide. The light-emitting element as described in claim 2 further includes a transparent conductive layer located between the reflective structure and the second type semiconductor layer of the semiconductor stack. The light-emitting element as described in claim 6, wherein the intermediate layer opening exposes the transparent conductive layer, and the conductive structure is coated on the reflective structure and electrically connected to the transparent conductive layer. The light-emitting element as described in claim 1 further comprises a first contact structure and a second contact structure, wherein the first contact structure is electrically connected to the first type semiconductor layer, and the second contact structure contacts the conductive structure. The light-emitting element as described in claim 1, wherein the conductive structure includes a reflective layer, and the material of the reflective layer includes a metal material having a high reflectivity for the light emitted by the semiconductor stack. The light-emitting element as described in claim 1, wherein the material of other layers of the plurality of sub-layers includes silicon oxide, silicon nitride, silicon oxynitride, niobium oxide, niobium oxide, titanium oxide or aluminum oxide.