TWI847848B - Memory device and manufacturing method thereof - Google Patents

Abstract

A memory device includes a substrate, a bottom source structure, gate layers, dielectric layers, a contact structure and a plurality of support pillar structures. The bottom source structure is located over the substrate. The bottom source structure includes a bottom electrode layer, a dielectric stack structure and a blocking structure. The gate layers and the dielectric layers are alternately stacked over the bottom source structure. The contact structure penetrates through the gate layers and the dielectric layers and extends to the bottom source structure. The support pillar structure penetrates through the gate layers and the dielectric layers and extends to the bottom source structure. The dielectric stack structure of the bottom source structure surrounds each of the support pillar structures. The blocking structure of the bottom source structure is located between one of the support pillar structures and the contact structure.

Description

Memory device and manufacturing method thereof

The present disclosure relates to a memory device and a method for manufacturing the memory device.

In the semiconductor industry, the structure of memory devices is constantly changing, and the storage capacity of memory devices is constantly increasing. Memory devices are used in storage components of many products (such as MP3 players, digital cameras, and computer files). As these applications increase, the demand for memory devices focuses on small size and large storage capacity. In order to meet this condition, a memory device with high component density, small size and robust structure and a method for manufacturing the same are required. Therefore, it is important to provide a robust process in the manufacture of memory devices.

One technical aspect of the present disclosure is a memory device.

According to some embodiments of the present disclosure, a memory device includes a substrate, a bottom source structure, a plurality of gate layers and a plurality of dielectric layers, a contact structure, and a plurality of pillar structures. The bottom source structure is disposed on the substrate. The bottom source structure includes a bottom electrode layer, a dielectric stack structure, and a blocking structure. The gate layer and the dielectric layer are alternately stacked on the bottom source structure. The contact structure passes through the gate layer and the dielectric layer and extends to the bottom source structure. The pillar structure passes through the gate layer and the dielectric layer and extends to the bottom source structure. The dielectric stack structure of the bottom source structure surrounds each of the pillar structures, and the barrier structure of the bottom source structure is disposed between one of the pillar structures and the contact structure.

In some embodiments of the present disclosure, the blocking structure contacts the dielectric stack structure and the contact structure.

In some embodiments of the present disclosure, the bottom-source structure further includes a first conductive layer and a second conductive layer disposed on the first conductive layer. The blocking structure is disposed between the first conductive layer and the second conductive layer.

In some embodiments of the present disclosure, the contact structure extends along a first direction, and the first portion of the blocking structure is adjacent to a section of the contact structure along the first direction.

In some embodiments of the present disclosure, the blocking structure further includes a second portion. The second portion of the blocking structure extends along a second direction perpendicular to the first direction.

In some embodiments of the present disclosure, the memory device further includes a memory structure. The memory structure passes through a gate layer and a dielectric layer above the array region. The contact structure extends along a first direction above the array region and the step region including the pillar structure.

Another technical aspect of the present disclosure is a memory device.

According to some embodiments of the present disclosure, a memory device includes a substrate, a bottom source structure, a plurality of gate layers and a plurality of dielectric layers, a contact structure and a pillar structure. The bottom source structure is disposed on the substrate. The bottom source structure includes a bottom electrode layer and a dielectric stack structure. The gate layer and the dielectric layer are stacked alternately on the bottom source structure. The contact structure passes through the gate layer and the dielectric layer and extends to the bottom source structure. The pillar structure passes through the gate layer and the dielectric layer and extends to the bottom source structure. The dielectric stack structure of the bottom source structure is laterally located between the lower portion of the contact structure and the lower portion of the pillar structure.

In some embodiments of the present disclosure, the bottom source structure further includes a blocking structure. The blocking structure is laterally adjacent to the dielectric stack structure.

In some embodiments of the present disclosure, a bottom surface of the pillar structure is below a bottom surface of the dielectric stack structure.

Another technical aspect of the present disclosure is a method for manufacturing a memory device.

According to some embodiments of the present disclosure, a method for manufacturing a memory device includes sequentially forming a first conductive layer, a dielectric stack structure, and a second conductive layer on a substrate, wherein the substrate has an array region and a step region. Forming a blocking layer on the second conductive layer, wherein the blocking layer above the step region further passes through the second conductive layer and the dielectric stack structure. Forming a plurality of dielectric layers and a plurality of sacrificial material layers alternately stacked on the blocking layer. A memory structure is formed downward through the dielectric layer, sacrificial material layer, blocking layer, second conductive layer and dielectric stack structure above the array region, wherein the memory structure includes a memory element and a channel layer above the memory element. A pillar structure is formed downward through the dielectric layer, sacrificial material layer, blocking layer, second conductive layer and dielectric stack structure above the step region. A slit trench is formed downward through the dielectric layer and sacrificial material layer above the array region and the step region. The blocking layer and second conductive layer above the array region are etched from the slit trench to expose the dielectric stack structure. The dielectric stack structure and the memory element of the memory structure above the array region are etched to expose the channel layer of the memory structure. A bottom electrode layer is formed to electrically connect the channel layer of the memory structure. The sacrificial material layer is replaced with a plurality of gate layers. A contact structure is formed in the slit trench.

The following will disclose multiple embodiments of the present disclosure with drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary and therefore should not be used to limit the present disclosure. In addition, in order to simplify the drawings, some commonly used structures and components will be depicted in the drawings in a simple schematic manner. In addition, in order to facilitate the reader's viewing, the size of each component in the drawings is not drawn according to the actual scale.

As used herein, "about", "approximately" or "substantially" shall generally refer to within 10% of a given value or range, and more preferably within 5%. The numerical values given herein are approximate, meaning that if not explicitly stated, the meaning of the term "about", "approximately" or "substantially" can be inferred.

In the embodiments of the present disclosure, a memory device and a method for manufacturing the same are provided. It should be understood that, for ease of description, the term "top view" in the present disclosure may generally refer to a cross-sectional view of the second conductive layer of the memory device (i.e., the cross-sectional position of the line segment A-A in FIG. 1B ) to highlight the technical features of the present disclosure. In addition, FIG. 1A , FIG. 2A , FIG. 3A , FIG. 4A , FIG. 5A , FIG. 6A , FIG. 7A , FIG. 8A , FIG. 9A , FIG. 10A , FIG. 11A , FIG. 12A , FIG. 13A , and FIG. 14A illustrate top views of the layout of the memory device according to some embodiments of the present disclosure, and for the sake of simplicity, some components are not illustrated in these top views. Figures 1A-1B, 2A-2B, 3A-3B, 4A-4B, 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9A-9B, 10A-10B, 11A-11B, 12A-12B, 13A-13B, and 14A-14C show views of a method of manufacturing a memory device 100 at different stages according to some embodiments of the present disclosure.

FIG. 1A shows a top view of a step of manufacturing the memory device 100, and FIG. 1B shows a cross-sectional view of the memory device 100 above the array region AR and the step region SR taken along line segment A1-A1' and line segment S1-S1' in FIG. 1A, respectively. Referring to FIG. 1A and FIG. 1B, a substrate 110 is provided. The substrate 110 has an array region AR and a step region SR, wherein a memory array is formed above the array region AR of the substrate 110. The step region SR is adjacent to the array region AR.

An isolation layer 120 is formed on the substrate 110. Then, a first conductive layer 130, a dielectric stack structure DS, a second conductive layer 170, and an isolation layer 180 are sequentially formed on the substrate 110. In some embodiments, the first conductive layer 130, the dielectric stack structure DS, and the second conductive layer 170 are referred to as a bottom stack structure. In some other embodiments, the first conductive layer 130, the dielectric stack structure DS, the second conductive layer 170, and the isolation layer 180 are referred to as a bottom stack structure. The bottom stack structure extends along a plane defined by a first direction D1 and a second direction D2, wherein the first direction D1 is perpendicular to the second direction D2. The isolation layer 120 contacts the substrate 110. The first conductive layer 130 contacts the isolation layer 120. The dielectric stack structure DS contacts the first conductive layer 130. The second conductive layer 170 contacts the dielectric stack structure DS. The isolation layer 180 contacts the second conductive layer 170. In some embodiments, forming the dielectric stack structure DS includes sequentially forming a first dielectric layer 140, a second dielectric layer 150, and a third dielectric layer 160. The first dielectric layer 140 contacts the first conductive layer 130, and the third dielectric layer 160 contacts the second conductive layer 170.

After forming the isolation layer 180 on the substrate 110, an opening O1 is formed downward through the isolation layer 180, the second conductive layer 170, and the third dielectric layer 160 of the dielectric stack structure DS, and exposes the second dielectric layer 150 of the dielectric stack structure DS. In some embodiments, forming the opening O1 further includes etching a portion of the second dielectric layer 150 so that the exposed surface 153 of the second dielectric layer 150 is located below the top surface 151 of the second dielectric layer 150 (or the bottom surface of the third dielectric layer 160). In some embodiments, a patterned photoresist is formed on the isolation layer 180, wherein the patterned photoresist can be formed by appropriate deposition, development and/or etching techniques. Next, the isolation layer 180, the second conductive layer 170, and the third dielectric layer 160 of the dielectric stack structure DS that are not covered by the patterned photoresist are etched using the patterned photoresist as an etching mask to form an opening O1. After the opening O1 is formed, the patterned photoresist can be removed by using a photoresist stripping process (e.g., an ashing process).

As shown in FIG. 1A , the opening O1 is disposed above the step region SR and is separated from the array region AR. The opening O1 may include a first portion O1a and a second portion O1b perpendicular to the first portion O1a. Specifically, the first portion O1a extends along a first direction D1, and the second portion O1b extends along a second direction D2. The first portion O1a is connected to the second portion O1b. The opening O1 has a comb-shaped outline in a top view.

In some embodiments, substrate 110 is a semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or the like. Substrate 110 may include an interconnect structure having conductive contacts, transistors, or other similar components. In some embodiments, isolation layer 120 includes an oxide (e.g., silicon oxide). In some embodiments, first conductive layer 130 and second conductive layer 170 include the same material. For example, first conductive layer 130 and second conductive layer 170 include a semiconductor material (e.g., polysilicon). In some embodiments, first dielectric layer 140 is a first oxide layer, second dielectric layer 150 is a nitride layer, and third dielectric layer 160 is a second oxide layer. In some embodiments, the isolation layer 180 includes an oxide (eg, silicon oxide). In some embodiments, the isolation layer 120 and the isolation layer 180 include the same material (eg, oxide).

FIG. 2A is a top view showing a step of manufacturing the memory device 100, and FIG. 2B is a cross-sectional view of the memory device 100 above the array region AR and the step region SR taken along line segment A1-A1′ and line segment S1-S1′ in FIG. 1A, respectively. FIG. 3A is a top view showing a step of manufacturing the memory device 100, and FIG. 3B is a cross-sectional view of the memory device 100 above the array region AR and the step region SR taken along line segment A1-A1′ and line segment S1-S1′ in FIG. 3A, respectively. 2A, 2B, 3A, and 3B, after the opening O1 is formed, the dielectric stack structure DS is etched to laterally expand a portion P1 of the opening O1 below the second conductive layer 170. Referring to FIG. 2A and FIG. 2B, a first etching process is performed on the second dielectric layer 150 so that the bottom surface 165 of the third dielectric layer 160 is exposed. In some embodiments, the first etching process is a dry etching process, a wet etching process, or a combination thereof. In some embodiments, since the second dielectric layer 150 and the first dielectric layer 140 (or the third dielectric layer 160) have different etching selectivities, during the first etching process, the second dielectric layer 150 is etched while the first dielectric layer 140 (or the third dielectric layer 160) remains substantially intact (not etched). In other words, the first dielectric layer 140, the third dielectric layer 160, the second conductive layer 170, and the isolation layer 180 have higher etching resistance to the first etching process than the second dielectric layer 150.

As shown in FIG. 2A, FIG. 2B, FIG. 3A, and FIG. 3B, after performing the first etching process, a second etching process is performed to expose the bottom surface 175 of the second conductive layer 170 and the top surface 131 of the first conductive layer 130. In detail, performing the second etching process includes etching the third dielectric layer 160 and the first dielectric layer 140 of the dielectric stack structure DS. In some embodiments, performing the second etching process further includes etching the isolation layer 180, so that the top surface 171 of the second conductive layer 170 is exposed. During the second etching process, since the first dielectric layer 140, the third dielectric layer 160 and the isolation layer 180 are made of the same material (e.g., oxide), the first dielectric layer 140, the third dielectric layer 160 and the isolation layer 180 can be etched simultaneously. After performing the second etching process, the opening O1 exposes the sidewall 147 of the first dielectric layer 140, the sidewall 157 of the second dielectric layer 150 and the sidewall 167 of the third dielectric layer 160. The sidewall 147, the sidewall 157 and the sidewall 167 are substantially aligned with each other. As a result of the first etching process and the second etching process, the opening O1 has a first width W1 in the second conductive layer 170 and a second width W2 in the dielectric stack structure DS. The second width W2 of the opening O1 is greater than the first width W1 of the opening O1. In some embodiments, the second etching process is a dry etching process, a wet etching process, or a combination thereof. In some embodiments, since the first dielectric layer 140 (or the third dielectric layer 160) and the second dielectric layer 150 have different etching selectivities, during the second etching process, the first dielectric layer 140 (or the third dielectric layer 160) is etched while the second dielectric layer 150 remains substantially intact (not etched). That is, the second dielectric layer 150 and the second conductive layer 170 have higher resistance to the second etching process than the first dielectric layer 140, the third dielectric layer 160 and the isolation layer 180. In some embodiments, the etchant of the second etching process is different from the etchant of the first etching process.

FIG. 4A shows a top view of a step of manufacturing the memory device 100, and FIG. 4B shows a cross-sectional view of the memory device 100 above the array region AR and the step region SR, respectively, taken along line segment A1-A1′ and line segment S1-S1′ in FIG. 4A. Referring to FIG. 4A and FIG. 4B, after performing the second etching process, a conductive material is filled in the opening O1 and above the second conductive layer 170 to form a blocking layer 190. In other words, the second conductive layer 170 is covered by the blocking layer 190. The blocking layer 190 has a portion 195′ above the step region SR and passing through the second conductive layer 170 and the dielectric stack structure DS. In some embodiments, since the conductive structure fills the opening O1, the blocking layer 190 in the second conductive layer 170 and the dielectric stack structure DS inherits the geometric shape of the opening O1. In other words, the blocking layer 190 in the second conductive layer 170 has a first width W1, and the blocking layer 190 in the dielectric stack structure DS has a second width W2 greater than the first width W1.

In some embodiments, as shown in FIGS. 3A , 3B, 4A, and 4B, the first width W1 of the opening O1 in the second conductive layer 170 is greater than the thickness T1 of the dielectric stack structure DS. Therefore, the opening O1 can be completely filled with the conductive material, so there is no void in the blocking layer 190. If the first width W1 of the opening O1 in the second conductive layer 170 is less than the thickness T1 of the dielectric stack structure DS, the opening O1 in the second conductive layer 170 will be sealed by the conductive material prematurely, so that a void may be formed in a portion of the blocking layer 190 in the dielectric stack structure DS. In some embodiments, the first width W1 of the opening O1 in the second conductive layer 170 (or the first width of the blocking layer 190) is in a range from about 50 nm to about 200 nm. If the first width W1 is less than 50 nm, the blocking layer 190 in the dielectric stack structure DS may have a gap. If the first width W1 is greater than 200 nm, the blocking layer 190 above the second conductive layer 170 may be too thick.

In some embodiments, the thickness T2 of the blocking layer 190 above the second conductive layer 170 is greater than half of the first width W1 of the opening Ol in the second conductive layer 170. Therefore, the opening Ol can be filled with conductive material, so there is no gap in the blocking layer 190. In some embodiments, the thickness T2 of the blocking layer 190 above the second conductive layer 170 is in the range of about 50 nanometers to about 300 nanometers. If the thickness T2 of the blocking layer 190 is less than 50 nanometers, the blocking layer 190 in the dielectric stack structure DS will have a gap. If the thickness T2 of the blocking layer 190 is greater than 300 nanometers, the electrical performance of the blocking layer 190 will be poor.

In some embodiments, the blocking layer 190 is formed by filling the opening O1 with a conductive material using chemical vapor deposition, atomic layer deposition, physical vapor deposition, or other suitable deposition processes. In some embodiments, the blocking layer 190 and the second conductive layer 170 include the same material. For example, the blocking layer 190 and the second conductive layer 170 include a semiconductor material (e.g., polysilicon). In some embodiments, the blocking layer 190 and the first conductive layer 130 include the same material. For example, the blocking layer 190 and the first conductive layer 130 include a semiconductor material (e.g., polysilicon).

FIG. 5A shows a top view of a step of manufacturing the memory device 100, and FIG. 5B shows a cross-sectional view of the memory device 100 above the array region AR and the step region SR taken along the line segment A1-A1′ and the line segment S1-S1′ in FIG. 5A, respectively. Referring to FIG. 5A and FIG. 5B, a plurality of dielectric layers 210 and a plurality of sacrificial material layers 220 are alternately stacked above the blocking layer 190. The dielectric layers 210 and the sacrificial material layers 220 are alternately arranged above the blocking layer 190, and the bottommost layer of the dielectric layer 210 closest to the blocking layer 190 directly contacts the blocking layer 190. In some embodiments, the dielectric layer 210 and the sacrificial material layer 220 include different materials. For example, the dielectric layer 210 includes an oxide (eg, silicon oxide) and the sacrificial material layer 220 includes a nitride (eg, silicon nitride).

FIG. 6A shows a top view of a step of manufacturing the memory device 100, and FIG. 6B shows a cross-sectional view of the memory device 100 above the array region AR and the step region SR taken along line segment A1-A1′ and line segment S1-S1′ in FIG. 6A, respectively. Referring to FIG. 6A and FIG. 6B, after forming the dielectric layer 210 and the sacrificial material layer 220, a plurality of memory structures MS are formed downwardly through the dielectric layer 210, the sacrificial material layer 220, the blocking layer 190, the second conductive layer 170, and the dielectric stack structure DS above the array region AR. In some embodiments, each of the memory structures MS has a portion embedded in the first conductive layer 130. Each of the memory structures MS includes a channel structure CH and a conductive plug 260 located on the channel structure CH. Each of the channel structures CH includes a memory element 230, a channel layer 240, and a dielectric filling structure 250. The memory element 230 contacts the sacrificial material layer 220, the blocking layer 190, the second conductive layer 170, the dielectric stack structure DS, and the first conductive layer 130. The channel layer 240 contacts the memory element 230, and the channel layer 240 is located between the memory element 230 and the dielectric filling structure 250. In some embodiments, the memory element 230 includes a blocking layer 232, a memory storage layer 234, and a tunneling layer 236. The blocking layer 232 is disposed on the sidewalls of the dielectric layer 210, the sidewalls of the sacrificial material layer 220, the sidewalls of the blocking layer 190, the sidewalls of the second conductive layer 170, the sidewalls of the dielectric stack structure DS, the sidewalls of the first conductive layer 130, and the surface of the first conductive layer 130. The memory storage layer 234 is disposed on the blocking layer 232, and the tunneling layer 236 is disposed on the memory storage layer 234. The blocking layer 232 and the tunneling layer 236 may include oxide (e.g., silicon oxide) or other suitable dielectric materials, and the memory storage layer 234 may include nitride (e.g., silicon nitride) or other materials capable of capturing electrons. Therefore, the memory element 230 may be a three-layer structure of an oxide layer, a nitride layer, and an oxide layer. The channel layer 240 may include polysilicon or other suitable semiconductor materials. The dielectric filling structure 250 may include oxide (e.g., silicon oxide) or other suitable dielectric materials. The conductive plug 260 may include polysilicon or other suitable semiconductor materials. The conductive plug 260 and the channel layer 240 may include the same material, such as a semiconductor material or polysilicon.

In some embodiments, forming the memory structure MS includes the following steps: A plurality of openings O2 are formed downward through the dielectric layer 210, the sacrificial material layer 220, the blocking layer 190, the second conductive layer 170, and the dielectric stack structure DS above the array region AR, so that the first conductive layer 130 is exposed. A memory element 230 (including a blocking layer 232, a memory storage layer 234, and a tunneling layer 236) is formed on opposite sidewalls of the opening O2, but the opening O2 is not yet completely filled with the memory element 230. Then, a channel layer 240 is formed on the sidewalls and bottom of the memory element 230, but the opening O2 is not yet completely filled with the channel layer 240. Thereafter, a dielectric material is filled in the opening O2 to form a dielectric filling structure 250 on the channel layer 240. In this way, a channel structure CH including the memory element 230, the channel layer 240, and the dielectric filling structure 250 is formed. After the channel structure CH (i.e., the memory element 230, the channel layer 240, and the dielectric filling structure 250) is formed, the space 260S is recessed to expose the top surface of the channel structure CH. Therefore, the top surface of the channel structure CH is below the top surface 211 of the topmost layer of the dielectric layer 210. Then, a conductive material is filled in the space 260S to form a conductive plug 260 on the channel structure CH. In other words, the top surface 261 of the conductive plug 260 is substantially coplanar with the top surface 211 of the topmost layer of the dielectric layer 210. Thus, the memory structure MS including the channel structure CH (including the memory element 230, the channel layer 240 and the dielectric filling structure 250) and the conductive plug 260 is formed in the opening O2.

For the step region SR, a plurality of pillar structures 270 are formed to pass downward through the dielectric layer 210, the sacrificial material layer 220, the blocking layer 190, the second conductive layer 170, and the dielectric stack structure DS above the step region SR. In detail, the dielectric layer 210, the sacrificial material layer 220, the blocking layer 190, the second conductive layer 170, and the dielectric stack structure DS above the step region SR are first etched to form a hole H1 exposing the first conductive layer 130. Then, a dielectric material is filled in the hole H1 to form the pillar structures 270. In some embodiments, each of the pillar structures 270 has a portion embedded in the first conductive layer 130. In some embodiments, pillar structures 270 include oxide (e.g., silicon oxide) or other suitable dielectric materials. In some embodiments, forming memory structures MS is performed before forming pillar structures 270. In some embodiments, as shown in FIG. 6A , each of memory structures MS has a circular outline in a top view, and each of pillar structures 270 has a circular outline in a top view. In some embodiments, as shown in FIG. 6A , each of pillar structures 270 has a diameter greater than a diameter of each of memory structures MS.

Thereafter, an isolation layer 280 is formed on the topmost layer of the dielectric layer 210. In some embodiments, the pillar structure 270 and the isolation layer 280 can be formed together using a single deposition process. In other words, the pillar structure 270 and the isolation layer 280 include the same material. In some embodiments, the pillar structure 270 and the isolation layer 280 include an oxide (e.g., silicon oxide) or other suitable dielectric material. In some embodiments, the pillar structure 270, the isolation layer 280 and the dielectric layer 210 include the same material, such as an oxide.

FIG. 7A shows a top view of a step of manufacturing the memory device 100, and FIG. 7B shows a cross-sectional view of the memory device 100 above the array region AR and the step region SR, respectively, taken along line segment A1-A1′ and line segment S1-S1′ in FIG. 7A. Referring to FIG. 7A and FIG. 7B, after forming the memory structure MS and forming the pillar structure 270, the dielectric layer 210 and the sacrificial material layer 220 are etched to form slit trenches ST above the array region AR and the step region SR and downwardly through the dielectric layer 210 and the sacrificial material layer 220. In some implementations, forming the slit trench ST further includes etching the blocking layer 190 over the array region AR and the step region SR.

In some embodiments, as shown in FIG. 7A , each of the slit trenches ST extends between the array region AR and the step region SR and extends along the first direction D1. In some embodiments, as discussed above with respect to FIG. 1A , the opening O1 forming the blocking layer 190 includes a first portion O1a along the first direction D1 and a second portion O1b along the second direction D2. The slit trenches ST are parallel to and overlap the first portion O1a of the corresponding opening O1. The second portion O1b of the opening O1 is located between the memory structure MS and the pillar structure 270.

Referring now to FIG. 15 , FIG. 15 shows a top view of a memory device 100′ according to some embodiments of the present disclosure. As shown in FIGS. 7A and 15 , the memory device 100′ of FIG. 15 is substantially the same as the memory device 100 of FIG. 7A , except for the outline of the opening O1′ that forms the blocking layer 190. The opening O1′ extends along the first direction D1. The slit trenches ST are respectively parallel to and overlap the corresponding openings O1′. The opening O1′ does not have a portion located in the middle of the memory structure MS and the pillar structure 270.

FIG. 8A shows a top view of a step of manufacturing the memory device 100, and FIG. 8B shows a cross-sectional view of the memory device 100 above the array region AR and the step region SR taken along line segment A1-A1′ and line segment S1-S1′ in FIG. 8A, respectively. Referring to FIG. 8A and FIG. 8B, an etching process is performed to further extend (or deepen) the slit trench ST. For the array region AR, the blocking layer 190 and the second conductive layer 170 are etched from the slit trench ST, and the etching process may be stopped at the position of the third dielectric layer 160 of the dielectric stack structure DS because the third dielectric layer 160 may include a higher etching resistance to the etching process. For the step region SR, a first portion of the blocking layer 190 exposed by the slit trench ST is removed, and a second portion of the blocking layer 190 not exposed by the slit trench ST remains under the second conductive layer 170 after the etching process is completed. The remaining second portion of the blocking layer 190 is referred to as a blocking structure 195. In other words, the remaining second portion of the blocking layer 190 between the first conductive layer 130 and the second conductive layer 170 is referred to as a blocking structure 195. The blocking structure 195 contacts the dielectric stack structure DS. After etching the blocking layer 190 above the array region AR and the step region SR, the first conductive layer 130 above the array region AR is still covered by the dielectric stack structure DS, while the first conductive layer 130 above the step region SR is exposed. In some embodiments, a portion of the first conductive layer 130 over the step region SR is etched such that an exposed surface 137 of the first conductive layer 130 is below a top surface 131 of the first conductive layer 130 contacting the stopper structure 195. In some embodiments, etching the stopper layer 190 over the array region AR and the step region SR is performed by using a dry etching process, a wet etching process, or a combination thereof.

FIG. 9A shows a top view of a step of manufacturing the memory device 100, and FIG. 9B shows a cross-sectional view of the memory device 100 above the array region AR and the step region SR taken along line segment A1-A1′ and line segment S1-S1′ in FIG. 9A, respectively. Referring to FIG. 9A and FIG. 9B, a protective layer 290 is conformally formed on the structure of FIG. 8A and FIG. 8B. In detail, the protective layer 290 is formed on the top surface 281 of the isolation layer 280, the sidewalls of the dielectric layer 210, the sidewalls of the sacrificial material layer 220, the sidewalls of the blocking layer 190, and the sidewalls of the second conductive layer 170. In some embodiments, for the array region AR, a protection layer 290 is formed on the third dielectric layer 160 of the dielectric stack structure DS and contacts the third dielectric layer 160 of the dielectric stack structure DS. The protection layer 290 is configured to prevent the sidewalls of the slit trench ST (e.g., the sidewalls of the dielectric layer 210 and the sidewalls of the sacrificial material layer 220) from being damaged in a subsequent etching process (e.g., the etching process of the dielectric stack structure DS of FIGS. 10A to 11B). In some embodiments, for the step region SR, the protection layer 290 is formed on the top surface of the first conductive layer 130 and the sidewalls of the blocking structure 195, and the protection layer 290 contacts the first conductive layer 130 and the blocking structure 195. In some embodiments, the protection layer 290 includes a semiconductor material (e.g., polysilicon). In some embodiments, the protection layer 290, the second conductive layer 170, and/or the first conductive layer 130 include the same material.

After forming the protective layer 290, the bottom portion of the protective layer 290 is etched to expose the dielectric stack structure DS above the array region AR and to expose the first conductive layer 130 above the step region SR. In some embodiments, etching the protective layer 290 is performed by using a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the third dielectric layer 160 of the dielectric stack structure DS above the array region AR is etched to expose the second dielectric layer 150 of the dielectric stack structure DS below. In some embodiments, a portion of the second dielectric layer 150 of the dielectric stack structure DS is etched so that the sidewalls and the surface of the second dielectric layer 150 are exposed. Since the blocking structure 195 above the step region SR protects the adjacent dielectric stack structure DS, the dielectric stack structure DS will not be exposed (i.e., covered by the blocking structure 195) during the etching of the protection layer 290. In addition, during the etching of the dielectric stack structure DS (i.e., during the etching process of the dielectric stack structure DS in FIGS. 10A to 11B), damage to the pillar structure 270 will be avoided or prevented, thereby avoiding deformation or collapse problems.

FIG. 10A shows a top view of a step of manufacturing the memory device 100, and FIG. 10B shows a cross-sectional view of the memory device 100 above the array region AR and the step region SR taken along line segment A1-A1' and line segment S1-S1' in FIG. 10A, respectively. Referring to FIG. 10A and FIG. 10B, the entire second dielectric layer 150 of the dielectric stack structure DS above the array region AR is removed to form a recess R1. The recess R1 exposes the first dielectric layer 140 and the third dielectric layer 160 of the dielectric stack structure DS. In some embodiments, as shown in FIG. 10B, the recess R1 is connected to the slit trench ST. In some embodiments, a wet etching process is used to remove the second dielectric layer 150 of the dielectric stack structure DS, wherein the wet etching process may use a phosphoric acid solution or other appropriate acidic etching solutions.

FIG. 11A shows a top view of a step of manufacturing the memory device 100, and FIG. 11B shows a cross-sectional view of the memory device 100 above the array region AR and the step region SR taken along line segment A1-A1' and line segment S1-S1' in FIG. 11A, respectively. Referring to FIG. 11A and FIG. 11B, the entire first dielectric layer 140 and the third dielectric layer 160 of the dielectric stack structure DS above the array region AR are removed to expand the recess R1. The memory element 230 of the memory structure MS is etched through the recess R1 to expose the channel layer 240 above the array region AR. The recess R1 further exposes the first conductive layer 130 and the second conductive layer 170 above the array region AR. In some embodiments, the first dielectric layer 140 and the third dielectric layer 160 of the dielectric stack structure DS and the memory element 230 are etched by using a dry etching process, a wet etching process or a combination thereof.

FIG. 12A shows a top view of a step of manufacturing the memory device 100, and FIG. 12B shows a cross-sectional view of the memory device 100 above the array region AR and the step region SR taken along line segment A1-A1′ and line segment S1-S1′ in FIG. 12A, respectively. Referring to FIG. 12A and FIG. 12B, the conductive structure 300′ is filled in the groove R1. In addition, the conductive structure 300′ is formed on the sidewall of the slit trench ST, but the slit trench ST is not completely filled with the conductive structure 300′. In some embodiments, the conductive structure 300′ is conformally formed on the protective layer 290. Therefore, the conductive structure 300' includes a first portion 302' on the isolation layer 280 and a second portion 304' on the sidewall of the slit trench ST. In some embodiments, the conductive structure 300' is filled into the recess R1 by using chemical vapor deposition, atomic layer deposition, physical vapor deposition or other appropriate deposition process methods. In some embodiments, the conductive structure 300' includes a semiconductor material (e.g., polysilicon). In some embodiments, the conductive structure 300', the protective layer 290, the second conductive layer 170 and/or the first conductive layer 130 include the same material.

FIG. 13A shows a top view of a step in manufacturing the memory device 100, and FIG. 13B shows a cross-sectional view of the memory device 100 above the array region AR and the step region SR taken along line segment A1-A1′ and line segment S1-S1′ in FIG. 13A, respectively. Referring to FIG. 13A and FIG. 13B, the conductive structure 300′ is patterned to form (or define) a bottom electrode layer 300 electrically connected to the channel layer 240 of the memory structure MS. In detail, as shown in FIG. 12B and FIG. 13B , an etching process is performed to remove a first portion 302′ of the conductive structure 300′ above the isolation layer 280 and a second portion 304′ of the conductive structure 300′ on the sidewall of the slit trench ST. In some embodiments, as shown in FIG. 13B , a surface 303 of the bottom electrode layer 300 is exposed through the slit trench ST, and the surface 303 of the bottom electrode layer 300 is below the bottom surface 175 of the second conductive layer 170. In some embodiments, the etching process is performed so that the entire conductive structure 300′ above the step region SR is removed, thereby exposing the first conductive layer 130 above the step region SR. In addition, the entirety of the protective layer 290 over the array region AR and the step region SR is removed. Therefore, the top surface 281 of the isolation layer 280, the sidewalls of the dielectric layer 210, the sidewalls of the sacrificial material layer 220, the sidewalls of the blocking layer 190, and the sidewalls of the second conductive layer 170 over the array region AR and the step region SR are exposed. In some embodiments, the sidewall 193 of the blocking structure 195 separated from the dielectric stack structure DS is exposed. In some embodiments, since the conductive structure 300' and the protective layer 290 include the same material (e.g., polysilicon or other suitable semiconductor materials), the conductive structure 300' and the protective layer 290 can be removed in a single selective etching process. In some embodiments, a wet etching process is used to remove the conductive structure 300' and the protective layer 290. In some embodiments, the first conductive layer 130, the dielectric stack structure DS, the second conductive layer 170, the blocking layer 190, the blocking structure 195, and the bottom electrode layer 300 are referred to as a bottom source structure BS.

FIG. 14A shows a top view of a step of manufacturing the memory device 100, FIG. 14B shows a cross-sectional view of the memory device 100 above the array region AR and the step region SR taken along line segments A1-A1′ and S1-S1′ in FIG. 2A, respectively, and FIG. 14C shows a cross-sectional view of the memory device 100 above the step region SR taken along line segment S2-S2′ in FIG. 14A. Referring to FIGS. 13A, 13B, and 14A to 14C, the sacrificial material layer 220 is replaced with a plurality of gate layers 330. Specifically, the entirety of the sacrificial material layer 220 is removed to form the recess R2, so that the recess R2 is connected to the slit trench ST. In some embodiments, the sacrificial material layer 220 is removed using a wet etching process, wherein the wet etching process may use a phosphoric acid solution or other appropriate acidic etching solutions. In some embodiments, the pillar structure 270 provides structural support to prevent the memory device 100 from collapsing during the removal of the sacrificial material layer 220.

After the sacrificial material layer 220 is removed to form the groove R2, a conductive material is filled in the groove R2, and then an etching process is performed to remove excess conductive material to form a gate layer 330. The gate layer 330 may be referred to as a word line. Specifically, the gate layer 330 may serve as a control gate electrode of the memory device 100 (particularly a vertical NAND memory device). In some embodiments, the conductive material is filled in the groove R2 by using chemical vapor deposition, atomic layer deposition, physical vapor deposition, chemical plating process or other appropriate deposition process. In some implementations, gate layer 330 includes metal (eg, tungsten) or other suitable conductive materials.

After the sacrificial material layer 220 is replaced with the gate layer 330, a contact structure CS is formed in the slit trench ST. In detail, each of the contact structures CS includes a liner layer 310 and an electrode layer 320. The liner layer 310 may be formed in the slit trench ST by using a deposition process, and then a conductive material is filled in the slit trench ST to form the electrode layer 320. The formation of the liner layer 310 may use a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, or other appropriate deposition processes. The liner layer 310 includes an oxide (e.g., silicon oxide) or other suitable dielectric material. In some embodiments, the liner layer 310, the isolation layer 280, and/or the dielectric layer 210 include the same material (e.g., oxide). In some embodiments, the electrode layer 320 is formed using a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, or other suitable deposition process. The electrode layer 320 may include a semiconductor material (e.g., polysilicon), a metal, or other suitable conductive material. In some embodiments, the electrode layer 320, the conductive plug 260, the bottom electrode layer 300, the first conductive layer 130, the second conductive layer 170 and/or the blocking layer 190 (or the blocking structure 195) include the same material, such as polysilicon.

In some embodiments, a planarization process (e.g., a chemical mechanical polishing process) is performed to remove excess materials of the liner layer 310 and/or the electrode layer 320. For example, the isolation layer 280 is used as an etch stop layer to perform the planarization process so that the top surface of each contact structure CS (i.e., the top surface 321 of the electrode layer 320 and the top surface 311 of the liner layer 310) is substantially coplanar with the top surface 281 of the isolation layer 280.

In some embodiments, the contact structure CS is disposed on the sidewalls of the gate layer 330, the sidewalls of the dielectric layer 210, the sidewalls of the blocking layer 190, and the sidewalls of the second conductive layer 170. In other words, the contact structure CS passes down through the gate layer 330, the dielectric layer 210, the blocking layer 190, and the second conductive layer 170. In addition, for the step region SR, each of the contact structures CS has a portion embedded in the first conductive layer 130. In some embodiments, the liner layer 310 is configured to separate the electrode layer 320 and the gate layer 330 to avoid electrical contact between the electrode layer 320 and the gate layer 330. The electrode layer 320 of the contact structure CS is electrically connected to the bottom electrode layer 300 above the array region AR, and the electrode layer 320 of the contact structure CS is electrically connected to the first conductive layer 130 above the step region SR.

In some embodiments, the memory device 100 includes a substrate 110, a bottom source structure BS, a gate layer 330, a dielectric layer 210, a contact structure CS, and a pillar structure 270. The gate layer 330 and the dielectric layer 210 are stacked alternately above the bottom source structure BS. The contact structure CS passes through the gate layer 330 and the dielectric layer 210 downward and extends to the bottom source structure BS. The pillar structure 270 passes through the gate layer 330 and the dielectric layer 210 downward and extends to the bottom source structure BS. The bottom source structure BS is disposed above the substrate 110, and the bottom source structure BS includes a bottom electrode layer 300, a first conductive layer 130, a dielectric stack structure DS, a second conductive layer 170, a blocking layer 190, and a blocking structure 195. FIG. 14C shows a cross-sectional view of the memory device 100 above the step region SR taken along the line segment S2-S2' in FIG. 14A. In some embodiments, as shown in FIG. 14C, the dielectric stack structure DS is laterally located between two adjacent pillar structures 270 along the second direction D2. The blocking structure 195 of the bottom source structure BS is laterally located between one of the pillar structures 270 and one of the contact structures CS along the second direction D2. In other words, for the step region SR, the dielectric stack structure DS surrounds each of the pillar structures 270, and the blocking structure 195 surrounds each of the contact structures CS.

In some embodiments, as shown in FIG. 14C , each of the contact structures CS includes an upper portion CSU and a lower portion CSL. For the step region SR, the upper portion CSU is disposed in the isolation layer 280, the dielectric layer 210, and the gate layer 330, and the lower portion CSL is disposed in the blocking layer 190, the second conductive layer 170, the blocking structure 195, and the first conductive layer 130. For the step region SR, the lower portion CSL contacts the blocking structure 195 and is surrounded by the blocking structure 195. Specifically, for the step region SR, two opposite sidewalls of the lower portion CSL of each of the contact structures CS contact the blocking structure 195.

In some embodiments, as shown in FIG. 14C , each of the pillar structures 270 includes an upper portion 270U and a lower portion 270L. The upper portion 270U is disposed in the dielectric layer 210 and the gate layer 330, and the lower portion 270L is disposed in the blocking layer 190, the second conductive layer 170, the dielectric stack structure DS, and the first conductive layer 130. The lower portion 270L contacts the dielectric stack structure DS and is surrounded by the dielectric stack structure DS. Each of the pillar structures 270 has a top surface 271 below the top surface 281 of the isolation layer 280 and a bottom surface 275 below the top surface 131 of the first conductive layer 130. In some embodiments, the bottom surface 275 of the pillar structure 270 is below the bottom surface DS2 of the dielectric stack structure DS. In some embodiments, the dielectric stack structure DS of the bottom-source structure BS is laterally located between the lower portion CSL of one of the contact structures CS and the lower portion 270L of one of the pillar structures 270 along the second direction D2.

In some embodiments, as shown in FIG. 14B and FIG. 14C , the dielectric stack structure DS is vertically disposed between the first conductive layer 130 and the second conductive layer 170 along a direction perpendicular to a plane defined by the first direction D1 and the second direction D2. The blocking structure 195 is vertically disposed between the first conductive layer 130 and the second conductive layer 170 along a direction perpendicular to a plane defined by the first direction D1 and the second direction D2. The blocking structure 195 is laterally adjacent to the dielectric stack structure DS along the second direction D2. In some embodiments, for the step region SR, each of the blocking structures 195 contacts a sidewall DS1 of the dielectric stack structure DS and a sidewall of one of the contact structures CS. Specifically, for the step region SR, two opposite side walls of each of the blocking structures 195 contact the dielectric stack structure DS and the lower portion CSL of one of the contact structures CS, respectively. In some embodiments, for the step region SR, each of the blocking structures 195 contacts the lower portion CSL of one of the contact structures CS and is separated from the lower portion 270L of one of the pillar structures 270. In other words, the blocking structure 195 and the pillar structure 270 are separated by the dielectric stack structure DS. In some embodiments, the dielectric stack structure DS contacts one of the blocking structures 195 and one of the pillar structures 270. In some embodiments, as shown in FIG. 14B , the dielectric stack structure DS contacts the lower portion 270L of each of the pillar structures 270 and is separated from the lower portion CSL of each of the contact structures CS. In other words, the dielectric stack structure DS is separated from the contact structure CS by the blocking structure 195. The dielectric stack structure DS is laterally adjacent to the blocking structure 195.

In some embodiments, as shown in FIG. 14B , the memory device 100 further includes a memory structure MS above the array region AR. The memory structure MS passes downward through the dielectric layer 210, the gate layer 330, the blocking layer 190, and the second conductive layer 170 above the array region AR. The memory structure MS is separated from the pillar structure 270. In other words, the memory structure MS is disposed above the array region AR of the substrate 110, and the pillar structure 270 is disposed above the step region SR of the substrate 110. The bottom electrode layer 300 of the bottom source structure BS is electrically connected to the memory structure MS and the contact structure CS.

In some embodiments, as shown in FIG. 14A , the memory structures MS are arranged in multiple rows along the second direction D2, wherein the memory structures MS can be considered as vertical NAND memory strings. The contact structure CS extends along the first direction D1 above the array region AR and the step region SR. The array region AR includes the memory structure MS, and the step region SR includes the pillar structure 270. The contact structure CS is configured to divide the memory device 100 into a plurality of blocks. For example, the memory structure MS and the pillar structure 270 located between two adjacent contact structures CS are considered as one block. In some embodiments, as shown in FIG. 7A and FIG. 14A , the blocking structure 195 inherits the geometry of the opening O1. Specifically, the blocking structure 195 includes a first portion 195a corresponding to the first portion O1a of the opening O1 and a second portion 195b corresponding to the second portion O1b of the opening O1. That is, the profile of the first portion 195a of the blocking structure 195 is substantially the same as the profile of the first portion O1a of the opening O1, and the profile of the second portion 195b of the blocking structure 195 is substantially the same as the profile of the second portion O1b of the opening O1. In some embodiments, as shown in FIG. 7A and FIG. 14A, the first portion 195a of the blocking structure 195 is disposed adjacent to the section of the contact structure CS along the first direction D1. The second portion 195b of the blocking structure 195 extends along the second direction D2 perpendicular to the first direction D1.

According to the above-mentioned embodiments of the present disclosure, since the dielectric stack structure surrounds each of the pillar structures and the blocking structure is disposed between one of the pillar structures and the contact structure, damage to the pillar structure during an etching process (e.g., etching the dielectric stack to expose the channel layer of the memory structure) can be avoided or prevented, thereby avoiding deformation or collapse problems.

Although the present disclosure has been disclosed in the above implementation form, it is not intended to limit the present disclosure. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the scope of the attached patent application.

100,100’: memory device 110: substrate 120: isolation layer 130: first conductive layer 131,151,171,211,261,271,281,311,321: top surface 137,153,303: surface 147,157,167,193,DS1: side wall 140: first dielectric layer 150: second dielectric layer 160: third dielectric layer 165,175,275,DS2: bottom surface 170: second conductive layer 180: isolation layer 190: blocking layer 195: blocking structure 195’: part 210: Dielectric layer 220: Sacrificial material layer 230: Memory element 232: Blocking layer 234: Memory storage layer 236: Tunneling layer 240: Channel layer 250: Dielectric filling structure 260: Conductive plug 260S: Space 270: Pillar structure 270U, CSU: Upper part 270L, CSL: Lower part 280: Isolation layer 290: Protective layer 300: Bottom electrode layer 300’: Conductive structure 302’: First part 304’: Second part 310: Pad layer 320: Electrode layer 330: Gate layer AR: Array region BS: Bottom source structure CH: Channel structure CS: Contact structure D1: First direction D2: Second direction DS: Dielectric stack structure H1: Hole MS: Memory structure O1, O1’, O2: Opening O1a, 195a: First part O1b, 195b: Second part P1: Part R1, R2: Groove T1, T2: Thickness SR: Step region ST: Slit trench W1: First width W2: Second width A1-A1’, S1-S1’, S2-S2’: Line segment

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more clearly understandable, the attached drawings are described as follows: Figures 1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A and 14A show top views of the manufacturing method of the memory device according to some embodiments of the present disclosure at different stages. FIG. 1B, FIG. 2B, FIG. 3B, FIG. 4B, FIG. 5B, FIG. 6B, FIG. 7B, FIG. 8B, FIG. 9B, FIG. 10B, FIG. 11B, FIG. 12B, FIG. 13B, and FIG. 14B illustrate cross-sectional views at different stages of a method for manufacturing a memory device according to some embodiments of the present disclosure. FIG. 14C is a cross-sectional view taken along line segment S2-S2 in FIG. 14A. FIG. 15 illustrates a top view of a memory device according to some embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100: Memory device

110: Substrate

120: Isolation layer

130: First conductive layer

131,271,281,311,321: Top

140: First dielectric layer

150: Second dielectric layer

160: Third dielectric layer

170: Second conductive layer

190: barrier layer

195: Blocking structure

210: Dielectric layer

230:Memory device

232: barrier layer

234: Memory storage layer

236: Tunneling layer

240: Channel layer

250: Dielectric filling structure

260: Conductive plug

270: Pillar structure

270U,CSU:Upper part

270L,CSL:lower part

275: Bottom

280: Isolation layer

300: Bottom electrode layer

310: Pad layer

320:Electrode layer

330: Gate layer

AR: Array Area

BS: Bottom source structure

CH: Channel structure

CS: Contact structure

D1: First direction

D2: Second direction

DS: Dielectric stack structure

MS: memory structure

O1: Opening

R2: Groove

SR: Stairway area

ST: Slit groove

Claims (10)

A memory device comprises: a substrate; a bottom source structure disposed on the substrate, wherein the bottom source structure comprises a bottom electrode layer, a dielectric stack structure and a blocking structure; a plurality of gate layers and a plurality of dielectric layers stacked alternately on the bottom source structure; a contact structure passing through the gate layers and the dielectric layers and extending to the bottom source structure; and A plurality of pillar structures pass through the gate layers and the dielectric layers and extend to the bottom source structure, wherein the dielectric stack structure of the bottom source structure surrounds each of the pillar structures, and wherein the blocking structure of the bottom source structure is disposed between one of the pillar structures and the contact structure. A memory device as described in claim 1, wherein the blocking structure contacts the dielectric stack structure and the contact structure. The memory device as described in claim 1, wherein the bottom-source structure further includes a first conductive layer and a second conductive layer disposed on the first conductive layer, and the blocking structure is disposed between the first conductive layer and the second conductive layer. A memory device as described in claim 1, wherein the contact structure extends along a first direction, and a first portion of the blocking structure is adjacent to a section of the contact structure along the first direction. A memory device as described in claim 4, wherein the blocking structure further includes a second portion, and the second portion of the blocking structure extends along a second direction perpendicular to the first direction. The memory device as described in claim 4 further comprises: A memory structure passing through the gate layers and the dielectric layers above an array region, wherein the contact structure extends along the first direction above the array region and a step region including the pillar structures. A memory device comprises: a substrate; a bottom source structure disposed on the substrate, wherein the bottom source structure comprises a bottom electrode layer and a dielectric stack structure; a plurality of gate layers and a plurality of dielectric layers stacked alternately on the bottom source structure; a contact structure passing through the gate layers and the dielectric layers and extending to the bottom source structure; and a pillar structure passing through the gate layers and the dielectric layers and extending to the bottom source structure, wherein the dielectric stack structure of the bottom source structure is laterally located between a lower portion of the contact structure and a lower portion of the pillar structure. A memory device as described in claim 7, wherein the bottom source structure further includes a blocking structure, which is laterally adjacent to the dielectric stack structure. A memory device as described in claim 7, wherein a bottom surface of the pillar structure is below a bottom surface of the dielectric stack structure. A method for manufacturing a memory device, comprising: Sequentially forming a first conductive layer, a dielectric stack structure and a second conductive layer on a substrate, wherein the substrate has an array region and a step region; Forming a blocking layer on the second conductive layer, wherein the blocking layer above the step region further passes through the second conductive layer and the dielectric stack structure; Forming a plurality of dielectric layers and a plurality of sacrificial material layers alternately stacked on the blocking layer; Forming a memory structure downward through the dielectric layers, the sacrificial material layers, the blocking layer, the second conductive layer and the dielectric stack structure above the array region, wherein the memory structure includes a memory element and a channel layer on the memory element; Forming a pillar structure downward through the dielectric layers, the sacrificial material layers, the blocking layer, the second conductive layer and the dielectric stack structure above the step region; Forming a slit trench downward through the dielectric layers and the sacrificial material layers above the array region and the step region; Etching the blocking layer and the second conductive layer above the array region from the slit trench to expose the dielectric stack structure; Etching the dielectric stack structure and the memory element of the memory structure above the array region to expose the channel layer of the memory structure; Forming a bottom electrode layer electrically connected to the channel layer of the memory structure; Replacing the sacrificial material layers with a plurality of gate layers; and Forming a contact structure in the slit trench.

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