TWI847082B - Vertical hall magnetic device - Google Patents
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Abstract
Description
本發明涉及一種霍爾磁場感測元件,特別是垂直型霍爾磁場感測元件。The present invention relates to a Hall magnetic field sensing element, in particular to a vertical Hall magnetic field sensing element.
近年來,隨著半導體製程的蓬勃發展,導致各種電子元件的微小化、積體化已不再是夢想。In recent years, with the rapid development of semiconductor manufacturing processes, the miniaturization and integration of various electronic components are no longer a dream.
一般而言,傳統的霍爾感測元件主要是以勞侖茲力(Lorentz force)為主要的原理。其原理是當有一個外加電流沿水平軸施加時,會在垂直軸之間產生霍爾電壓,其電壓大小會隨著霍爾感測元件的厚度、截面積、外加電流與磁場大小而改變。倘若要感測較小的磁場,可以藉由提升外加電流、改變厚度或者改變載子濃度來實現。目前市售的霍爾感測元件大都以雙極性接面型電晶體(Bipolar Junction Transistor, BJT)技術或磁性材料製成,其讀出電路與訊號處理電路無法結合,故需要個別製造,再行整合,如此將導致製造成本提高、產品體積增大等缺點。另一方面,由於霍爾感測元件的輸出信號通常很小,所以需要低輸入偏移電壓及低雜訊特性。因此,如何有效減少體積且增加整合電路的方便性,便成為各家廠商急欲解決的問題之一。Generally speaking, traditional Hall sensors are based on the principle of Lorentz force. The principle is that when an external current is applied along the horizontal axis, a Hall voltage will be generated between the vertical axes, and the voltage will change with the thickness, cross-sectional area, external current and magnetic field of the Hall sensor. If a smaller magnetic field is to be sensed, it can be achieved by increasing the external current, changing the thickness or changing the carrier concentration. Most of the Hall sensors currently on the market are made of bipolar junction transistor (BJT) technology or magnetic materials. The readout circuit and signal processing circuit cannot be combined, so they need to be manufactured separately and then integrated, which will lead to disadvantages such as increased manufacturing costs and increased product size. On the other hand, since the output signal of the Hall sensor element is usually very small, it requires low input offset voltage and low noise characteristics. Therefore, how to effectively reduce the size and increase the convenience of integrated circuits has become one of the problems that manufacturers are eager to solve.
綜上所述,可知先前技術中一直存在感測靈敏度不佳及電路整合不便之問題,因此實有必要提出改進的技術手段,來解決此一問題。In summary, it can be seen that the prior art has always had problems with poor sensing sensitivity and inconvenient circuit integration, so it is necessary to propose improved technical means to solve this problem.
首先,本發明揭露一種垂直型霍爾磁場感測元件,係以標準互補式金氧半導體(Complementary Metal-Oxide-Semiconductor, CMOS)製程製作完成,此元件包含:半導體基板、多個淺層佈植層及電流阻擋層。其中,所述半導體基板上設置相互平行的二個深層佈植層以作為電流傳導的載體層;多個淺層佈植層分別設置在不同的深層佈植層的同一側之上表面,並且每一個淺層佈植層分別以N型井區(N-well)環繞,用以形成與深層佈植層電性連接的多個導體接墊,以及允許電流經由導體接墊通過深層佈植層中間相連之通道形成垂直型電流路徑,並且根據深層佈植層與淺層佈植層間的製程深度之差異生成不同軸向的磁場感測平面;以及電流阻擋層以保護環(Guard Ring)結構覆蓋深層佈植層作為阻擋電流的阻擋物。First, the present invention discloses a vertical Hall magnetic field sensing element, which is manufactured by a standard complementary metal-oxide-semiconductor (CMOS) process. The element includes: a semiconductor substrate, a plurality of shallow implanted layers and a current blocking layer. Two deep implanted layers parallel to each other are arranged on the semiconductor substrate as a carrier layer for current conduction; the plurality of shallow implanted layers are respectively arranged on the same side of different deep implanted layers, and each shallow implanted layer is respectively surrounded by an N-well region to form a current blocking layer with the deep implanted layers. A plurality of conductive pads electrically connected to each other in the layer, and a channel allowing current to pass through the conductive pads through the middle of the deep implant layer to form a vertical current path, and a magnetic field sensing plane in different axial directions is generated according to the difference in process depth between the deep implant layer and the shallow implant layer; and a current blocking layer covers the deep implant layer with a guard ring structure as a barrier to block the current.
本發明所揭露之元件如上,與先前技術的差異在於本發明是透過在半導體基板上設置相互平行的二個深層佈植層作為電流傳導的載體層,以及在不同的深層佈植層分別設置多個以N型井區環繞的淺層佈植層,用以形成與深層佈植層電性連接的多個導體接墊,並且允許電流經由導體接墊通過中間相連之通道形成垂直型電流路徑,以便根據深層佈植層與淺層佈植層間的製程深度之差異生成不同軸向的磁場感測平面。The device disclosed in the present invention is as described above. The difference from the prior art is that the present invention is to set two parallel deep implanted layers on the semiconductor substrate as the carrier layer for current conduction, and to set a plurality of shallow implanted layers surrounded by N-type well regions on different deep implanted layers to form a plurality of conductive pads electrically connected to the deep implanted layers, and to allow the current to pass through the conductive pads through the middle connected channels to form a vertical current path, so as to generate magnetic field sensing planes with different axial directions according to the difference in process depth between the deep implanted layer and the shallow implanted layer.
透過上述的技術手段,本發明可以達成提高感測靈敏度及電路整合的便利性之技術功效。Through the above-mentioned technical means, the present invention can achieve the technical effect of improving the sensing sensitivity and the convenience of circuit integration.
以下將配合圖式及實施例來詳細說明本發明之實施方式,藉此對本發明如何應用技術手段來解決技術問題並達成技術功效的實現過程能充分理解並據以實施。The following will be used in conjunction with drawings and embodiments to explain the implementation of the present invention in detail, so that the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.
在說明本發明所揭露之垂直型霍爾磁場感測元件之前,先對本發明所所使用的「電性連接」一詞進行說明;實際上,「電性連接」可以是任何直接或間接的電性連接手段。舉例來說,若文中描述與深層佈植層電性連接的多個導體接墊,則應該被解釋為深層佈植層可以直接連接於導體接墊,或者深層佈植層可以透過其他元件或某種連接手段而間接地連接至導體接墊。另外,本發明圖式中使用相同的網點或元件符號即代表相同的元件、材料或架構。Before explaining the vertical Hall magnetic field sensing element disclosed in the present invention, the term "electrical connection" used in the present invention is explained first; in fact, "electrical connection" can be any direct or indirect electrical connection means. For example, if the text describes multiple conductive pads electrically connected to the deep implant layer, it should be interpreted that the deep implant layer can be directly connected to the conductive pad, or the deep implant layer can be indirectly connected to the conductive pad through other components or some connection means. In addition, the same dots or component symbols used in the drawings of the present invention represent the same components, materials or structures.
以下配合圖式對本發明垂直型霍爾磁場感測元件做進一步說明,請先參閱「第1圖」。「第1圖」為本發明垂直型霍爾磁場感測元件的俯視圖,所述垂直型霍爾磁場感測元件100係以標準 CMOS 製程製作完成,其包含:半導體基板110、多個淺層佈植層(121~126)及電流阻擋層130。其中,半導體基板110上設置相互平行的二個深層佈植層(111、112)以作為電流傳導的載體層。在實際實施上,所述深層佈植層(111、112)為 T-well 佈植層(抽屜層)。The vertical Hall magnetic field sensing element of the present invention is further described below with reference to the drawings. Please refer to "Figure 1" first. "Figure 1" is a top view of the vertical Hall magnetic field sensing element of the present invention. The vertical Hall magnetic
多個淺層佈植層(121~126)分別設置在不同的深層佈植層(111、112)的同一側之上表面,並且每一淺層佈植層(121~126)分別以 N 型井區(131~136)環繞,用以形成與深層佈植層(111、112)電性連接的多個導體接墊(141~146),以第一個淺層佈植層121為例,其以 N 型井區131環繞形成導體接墊141;以第二個淺層佈植層122為例,其以N型井區132環繞形成導體接墊142,並以此類推,形成六個導體接墊(141~146)。接著,允許電流經由導體接墊(141~146)通過深層佈植層(111、112)中間相連之通道(151、152)形成垂直型電流路徑,並且根據深層佈植層(111、112)與淺層佈植層(121~126)間的製程深度之差異生成不同軸向的磁場感測平面,以便感測磁場變化。在實際實施上,所述淺層佈植層(121~126)為 N+ 佈植層,係用以改變載子(Carrier)的導通方向、增加阻值及縮小厚度;所述通道(151、152)係為導線、導電線(如:金屬導線);所述導體接墊(141~146)的長度及寬度係可分別在 15μm 至 90μm 之中任選其一,例如:選擇 30μm × 30μm 作為導體接墊(141~146)的尺寸。另外,所述導體接墊(141~146)可包含設置在深層佈植層其中之一(如:深層佈植層112)的第一導體接墊(即:導體接墊141)、第二導體接墊(即:導體接墊142)、第三導體接墊(即:導體接墊143),以及設置在另一所述深層佈植層(如:深層佈植層111)的第四導體接墊(即:導體接墊144)、第五導體接墊(即:導體接墊145)及第六導體接墊(即:導體接墊146),其中,第一導體接墊(即:導體接墊141)電性連接第四導體接墊(即:導體接墊144),並且作為第一電壓感測端(V
H1),第五導體接墊(即:導體接墊145)為電流源輸入端及第二導體接墊(即:導體接墊142)為電流源輸出端,第三導體接墊(即:導體接墊143)電性連接第六導體接墊(即:導體接墊146)作為第二電壓感測端(V
H2)。
A plurality of shallow implantation layers (121-126) are respectively arranged on the upper surface of the same side of different deep implantation layers (111, 112), and each shallow implantation layer (121-126) is respectively surrounded by an N-type well region (131-136) to form a plurality of conductive pads (141-146) electrically connected to the deep implantation layers (111, 112). Taking the first
電流阻擋層130以保護環結構覆蓋深層佈植層(111、112)作為阻擋電流的阻擋物。在實際實施上,所述電流阻擋層130為 P+ 保護環結構。另外,所述垂直型霍爾磁場感測元件100更可包含讀出電路及供給垂直型霍爾磁場感測元件100的直流電源,所述讀出電路以差值放大器將垂直型霍爾磁場感測元件100的電壓放大。The
接著,為了凸顯垂直型霍爾磁場感測元件100與平面型霍爾磁場感測元件(包含:十字埋層霍爾磁場感測元件及雙E型霍爾磁場感測元件)的差異,以下配合「第2圖」至「第3D圖」,針對平面型霍爾磁場感測元件的不同實施例進行如下說明。首先,請參閱「第2圖」,「第2圖」為十字埋層霍爾磁場感測元件的十字架構之示意圖。在實際實施上,由於製程上阻抗較高且較為穩定,所以霍爾平面係採用多晶矽(Polysilicon)層,而在電流源輸出入端(I
bias+、I
bias-)和電壓感測端(V
H1、V
H2)則可以垂直設置形成十字型架構200(即:多晶矽層),此十字型架構200可以使用三種尺寸規格,例如,寬度分別為30μm、60μm 及 90μm 等。另外,電流源輸出入端(I
bias+、I
bias-)和電壓感測端(V
H1、V
H2)垂直排列所形成的角(或稱為「轉角201」),可延伸成三種弧度,舉例來說,第一種弧度如「第2A圖」所示。「第2A圖」為十字埋層霍爾磁場感測元件的第一實施例之示意圖,其在電流源輸出入端(I
bias+、I
bias-)和電壓感測端(V
H1、V
H2)鄰近的兩個角,拉出一條直線並往內縮形成一個弧形(以下稱為圓弧形211),然後以此方式類推形成圓弧形十字架構210;第二種弧度與第一種弧度大同小異,其差異僅在於弧線的兩端位置並非在角的端點,而是如「第2B圖」所示。「第2B圖」為十字埋層霍爾磁場感測元件的第二實施例之示意圖,其在邊長的一半位置拉出一條直線,並且將拉出的直線往內縮形成一個弧形(以下稱為半弧形221),同樣地,以此方式類推形成半弧形十字架構220;第三種弧度如「第2C圖」所示。「第2C圖」為十字埋層霍爾磁場感測元件的第三實施例之示意圖,其在邊長的四分之一位置拉出一條直線,然後同樣將拉出的直線往內縮形成一個弧形231,再以此方式類推形成如「第2C圖」所示的弧形十字架構230。要補充說明的是,在十字型的基礎上,亦可如「第2D圖」所示。「第2D圖」為十字埋層霍爾磁場感測元件的第四實施例之示意圖,其在電流源輸出入端(I
bias+、I
bias-)和電壓感測端(V
H1、V
H2)鄰近的兩個角拉出一條直線,並以此類推,產生四條分布呈現菱形的直線241,而整體觀之則成為八邊形架構240。
Next, in order to highlight the difference between the vertical Hall magnetic
接著,以圓弧形十字架構210為例,其可使用三種佈植架構:(1) N 型井區覆蓋 P+ 佈植層,以 N-well 佈植層為電流傳導的載體,並且利用 N+ 佈植層作為連接 N-well 佈植層的導體接墊,元件之間的絕緣以 P+ 保護環的電流阻擋層(或稱為隔離層)作為阻擋電流阻擋物;(2)使用 T-well 佈植層覆蓋 P+ 佈植層,並且藉由 N+ 佈植層作為連接 N-well 佈植層的導體接墊,元件之間的絕緣同樣以 P+ 保護環架構的電流阻擋層作為阻擋電流阻擋物;(3)使用 P 型井區(P-well)覆蓋 N+ 佈植層,其採用 P-well 佈植層當作電流傳導載體,以 N+作為阻擋電流的阻擋物。同樣地,半弧形十字架構220、弧形十字架構230及八邊形架構240亦可使用上述三種佈植架構。Next, taking the arc-
接下來,以 1.8V 定電壓對上述不同佈植結構進行量測,其量測結果如表1所示,其中,「X」代表電流傳導載體失效,致使量測未果:Next, the above different implant structures were measured at a constant voltage of 1.8V. The measurement results are shown in Table 1, where "X" represents the failure of the current conduction carrier, resulting in measurement failure:
表1: 十字埋層霍爾磁場感測元件之 1.8V 定電壓量測參數比較
由表1可以得知,使用 T-well 佈植層作為電流傳導載體之佈植架構,於電壓靈敏度的表現較為出色;於三種弧度之架構比較下,菱形設計的電壓靈敏度明顯優於其他弧度,而於相同佈值架構下與 NW/P+_60μm 同尺寸之圓弧形比較,同樣也是菱形表現較佳。From Table 1, we can see that the implantation structure using the T-well implantation layer as the current conduction carrier has a better performance in voltage sensitivity. In the comparison of the three curvature structures, the voltage sensitivity of the diamond design is significantly better than that of the other curvatures. In the same layout value structure, when compared with the circular arc of the same size of NW/P+_60μm, the diamond design also performs better.
接著,表2係使用 0.1mA 定電流方式進行量測及分析,包含以電流傳導載體 N-well 佈植層,覆蓋 P+ 層作為阻擋物的三種尺寸之個別量測,以及以電流傳導載體層 T-well 佈植層,覆蓋 P+ 層作為阻擋物的三種尺寸之量測結果,其中,「X」代表電流傳導載體失效,致使量測未果:Next, Table 2 is the measurement and analysis using the 0.1mA constant current method, including individual measurements of three sizes using the current conduction carrier N-well implantation layer covering the P+ layer as a barrier, and the measurement results of three sizes using the current conduction carrier layer T-well implantation layer covering the P+ layer as a barrier. Among them, "X" represents the failure of the current conduction carrier, resulting in measurement failure:
表2:十字埋層霍爾磁場感測元件定電流量測參數比較
從表2可清楚得知,使用 T-well 佈植層作為電流傳導載體之佈植架構,於電流靈敏度的表現明顯優於其他佈植層;而於三種弧度之架構比較下,結果不同於定電壓量測,弧形與半弧形效果雷同,而兩者之電流靈敏度皆較菱形高,該結果同樣優於相同佈值架構下之 NW/P+_60μm 同尺寸圓弧形。From Table 2, it can be clearly seen that the current sensitivity of the implant structure using the T-well implant layer as the current conduction carrier is significantly better than that of other implant layers. In the comparison of the three arc structures, the results are different from the constant voltage measurement. The arc and semi-arc have similar effects, and the current sensitivity of both is higher than that of the diamond. The result is also better than the NW/P+_60μm arc of the same size under the same layout structure.
請參閱「第3A圖」,「第3A圖」為雙E型霍爾磁場感測元件的第一實施例之示意圖。除了前述形成十字型架構之外,平面型霍爾磁場感測元件還可使用如「第3A圖」所示的雙E型架構300,基於上述十字埋層霍爾磁場感測元件在不同邊長與轉角弧度之定電壓與定電流量測參數比較,兩者在使用 30μm 尺寸架構設計時,其電壓與電流靈敏度表現最佳,故雙E型霍爾磁場感測元件也可以使用 30μm 作為導體接墊寬度及電流路徑長度的標準尺寸,並且將霍爾磁場感測元件設計為正方形之佈局架構,其中,每一個導體接墊皆包含 N+ 佈植層303及 N-well 佈植層304,並且以電流阻擋層305覆蓋底層301。接著,在轉角弧度設計的部分,則將底層301(T-well)之電流路徑轉角由直角改為弧形角度,以降低電流受磁場介入時載子偏轉而撞擊佈植層之機率,例如:將轉角以半徑 1.8μm 設計轉角R角,所述轉角以弧度方式繪製已於前述十字埋層架構實體量測中實證有助於電流偏轉時之載子流動。實際上,還可如「第3B圖」所示的雙E型架構310,「第3B圖」為雙E型霍爾磁場感測元件的第二實施例之示意圖,其改變導體接墊寬度與邊長,例如:修改為15μm,甚至如「第3C圖」所示的雙E型架構320,「第3C圖」為雙E型霍爾磁場感測元件的第三實施例之示意圖,其維持導體接墊寬度 30μm、取消 30μm 邊長,僅留轉角R角 1.8μm 弧度,或是如「第3D圖」所示的雙E型架構330,「第3D圖」為雙E型霍爾磁場感測元件的第四實施例之示意圖,其將導體接墊寬度縮減為 15μm、取消邊長僅留轉角R角 1.8μm 弧度。在實際實施上,所述雙E型霍爾磁場感測元件的佈植層架構係採用較深層之 T-well 佈植層作為主要電流傳導之載體層,並且藉由使用 N+、N-well 佈植層作為導體接墊,再以 P+ 佈植層設置外圈之保護環,實現電流阻擋層以阻擋電流,其基於磁電阻效應(Magnetoresistance, MR)所設計,並且為新型Z軸垂直方向的一維雙E型霍爾磁場感測元件。Please refer to "FIG. 3A", which is a schematic diagram of the first embodiment of the dual E-type Hall magnetic field sensing element. In addition to the aforementioned cross-shaped structure, the planar Hall magnetic field sensing element can also use the double
本發明垂直型霍爾磁場感測元件係基於上述雙E型霍爾磁場感測元件的改良,同樣藉由較深層之T-well(即:深層佈植層)作為電流傳導載體層,導體接墊尺寸可使用 30μm × 30μm,但此架構設計不以平面電流偏轉方式實現,而是改藉由電流直下型架構之佈植層深度差值,從 N+ 與 N-well 建立與 T-well 連接的導體接墊,電流直接灌入深層的 T-well,通過中間相連的 T-well 通道即轉直上,進而建立垂直型電流路徑模型。接著,將本發明垂直型霍爾磁場感測元件與「第3A圖」至「第3D圖」所示的雙E型架構(300~330)的規格列於下表3:The vertical Hall magnetic field sensing element of the present invention is based on the improvement of the above-mentioned double E-type Hall magnetic field sensing element. It also uses a deeper T-well (i.e., a deep implantation layer) as a current conduction carrier layer. The size of the conductor pad can be 30μm × 30μm. However, this structure design is not implemented by a planar current deflection method. Instead, it uses the implantation layer depth difference of the current direct-down structure to establish a conductor pad connected to the T-well from N+ and N-well. The current is directly injected into the deep T-well and turns straight up through the T-well channel connected in the middle, thereby establishing a vertical current path model. Next, the specifications of the vertical Hall magnetic field sensor of the present invention and the double E-shaped structure (300-330) shown in "Figure 3A" to "Figure 3D" are listed in the following Table 3:
表3:霍爾磁場感測元件之規格列表
接下來,以定電壓量測為主,透過微磁場量測系統在X軸方向量測垂直型霍爾磁場感測元件,與在Z軸方向量測平面型霍爾磁場感測元件,量測之磁場範圍在 -3.03 到 +3.03 高斯(Gs)之間,評估磁場感測元件各架構之靈敏度與線性誤差。以下分別係使用 1.8V 與 3.3V 定電壓的量測參數:Next, we mainly use constant voltage measurement to measure the vertical Hall effect magnetic field sensor in the X-axis direction and the planar Hall effect magnetic field sensor in the Z-axis direction through the micro magnetic field measurement system. The measured magnetic field range is between -3.03 and +3.03 Gauss (Gs), and the sensitivity and linear error of each structure of the magnetic field sensor are evaluated. The following are the measurement parameters using 1.8V and 3.3V constant voltages respectively:
表4:垂直型架構之量測參數
接著,在平面型霍爾磁場感測元件的定電壓量測方面,在使用1.8V及3.3V定電壓施以垂直於晶片裝載半導體基板之Z軸方向磁場變化之量測結果的基礎上,兩者的定電壓量測參數分別如表5、表6所示:Next, in the constant voltage measurement of the planar Hall magnetic field sensor, based on the measurement results of the magnetic field change in the Z-axis direction perpendicular to the chip-mounting semiconductor substrate using 1.8V and 3.3V constant voltages, the constant voltage measurement parameters of the two are shown in Table 5 and Table 6 respectively:
表5:1.8V 定電壓量測參數比較
表6:3.3V 定電壓量測參數比較
上表5及表6各為1.8V與3.3V定電壓量測參數結果比較,在平面型的五種架構(「F15_1.8P」為並聯「F15_1.8」的架構)中,磁場感測元件代號「F30_31.8」與「F15_16.8」之電流靈敏度表現最佳,其中又以「F15_16.8」所占面積最小,而且線性誤差與對稱誤差表現較為突出。另以工作電壓差異進行比較,將電壓從1.8V提升至3.3V,對於電壓靈敏度與電流靈敏度不僅沒有提升,甚至使得靈敏度大幅下降。雖然本發明垂直型霍爾磁場感測元件的電壓靈敏度及電流靈敏度並非表現最佳,但是兩者仍然達成100 mV/mT之目標,並且其負磁場方向之線性誤差表現優良。Tables 5 and 6 above are comparisons of the measurement parameters at 1.8V and 3.3V. Among the five planar structures ("F15_1.8P" is a parallel "F15_1.8" structure), the current sensitivity of the magnetic field sensing element code "F30_31.8" and "F15_16.8" is the best, and the "F15_16.8" occupies the smallest area, and the linear error and symmetry error are more prominent. Another comparison is made based on the difference in working voltage. Increasing the voltage from 1.8V to 3.3V not only does not improve the voltage sensitivity and current sensitivity, but even causes a significant decrease in sensitivity. Although the voltage sensitivity and current sensitivity of the vertical Hall magnetic field sensor of the present invention are not the best, both still reach the target of 100 mV/mT, and the linear error in the negative magnetic field direction is excellent.
綜上所述,可知本發明與先前技術之間的差異在於透過在半導體基板上設置相互平行的二個深層佈植層作為電流傳導的載體層,以及在不同的深層佈植層分別設置多個以N型井區環繞的淺層佈植層,用以形成與深層佈植層電性連接的多個導體接墊,並且允許電流經由導體接墊通過中間相連之通道形成垂直型電流路徑,以便根據深層佈植層與淺層佈植層間的製程深度之差異生成不同軸向的磁場感測平面,藉由此一技術手段可以解決先前技術所存在的問題,進而達成提高感測靈敏度及電路整合的便利性之技術功效。In summary, the difference between the present invention and the prior art is that two parallel deep implanted layers are arranged on the semiconductor substrate as carrier layers for current conduction, and a plurality of shallow implanted layers surrounded by N-type well regions are arranged on different deep implanted layers to form a plurality of conductive pads electrically connected to the deep implanted layers, and to allow The current passes through the conductive pads through the middle connected channels to form a vertical current path, so as to generate magnetic field sensing planes in different axial directions according to the difference in process depth between the deep implantation layer and the shallow implantation layer. This technical means can solve the problems existing in the previous technology, thereby achieving the technical effect of improving the sensing sensitivity and the convenience of circuit integration.
雖然本發明以前述之實施例揭露如上,然其並非用以限定本發明,任何熟習相像技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之專利保護範圍須視本說明書所附之申請專利範圍所界定者為準。Although the present invention is disclosed as above by the aforementioned embodiments, they are not used to limit the present invention. Anyone skilled in similar techniques can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of patent protection of the present invention shall be subject to the scope of the patent application attached to this specification.
100:垂直型霍爾磁場感測元件
110:半導體基板
111,112:深層佈植層
121~126:淺層佈植層
130:電流阻擋層
131~136:N型井區
141~146:導體接墊
151,152:通道
200:十字型架構
201:轉角
210:圓弧形十字架構
211:圓弧形
220:半弧形十字架構
221:半弧形
230:弧形十字架構
231:弧形
240:八邊形架構
241:菱形的直線
300,310,320,330:雙E型架構
301:底層
303:N+ 佈植層
304:N-well 佈植層
305:電流阻擋層100: vertical Hall magnetic field sensor
110: semiconductor substrate
111,112:
第1圖為本發明垂直型霍爾磁場感測元件的俯視圖。 第2圖為十字埋層霍爾磁場感測元件的十字架構之示意圖。 第2A圖為十字埋層霍爾磁場感測元件的第一實施例之示意圖。 第2B圖為十字埋層霍爾磁場感測元件的第二實施例之示意圖。 第2C圖為十字埋層霍爾磁場感測元件的第三實施例之示意圖。 第2D圖為十字埋層霍爾磁場感測元件的第四實施例之示意圖。 第3A圖為雙E型霍爾磁場感測元件的第一實施例之示意圖。 第3B圖為雙E型霍爾磁場感測元件的第二實施例之示意圖。 第3C圖為雙E型霍爾磁場感測元件的第三實施例之示意圖。 第3D圖為雙E型霍爾磁場感測元件的第四實施例之示意圖。Figure 1 is a top view of the vertical Hall magnetic field sensing element of the present invention. Figure 2 is a schematic diagram of the cross structure of the cross-buried Hall magnetic field sensing element. Figure 2A is a schematic diagram of the first embodiment of the cross-buried Hall magnetic field sensing element. Figure 2B is a schematic diagram of the second embodiment of the cross-buried Hall magnetic field sensing element. Figure 2C is a schematic diagram of the third embodiment of the cross-buried Hall magnetic field sensing element. Figure 2D is a schematic diagram of the fourth embodiment of the cross-buried Hall magnetic field sensing element. Figure 3A is a schematic diagram of the first embodiment of the double E-type Hall magnetic field sensing element. Figure 3B is a schematic diagram of the second embodiment of the double E-type Hall magnetic field sensing element. Figure 3C is a schematic diagram of the third embodiment of the double E-type Hall magnetic field sensing element. FIG. 3D is a schematic diagram of a fourth embodiment of a dual E-type Hall magnetic field sensing element.
100:垂直型霍爾磁場感測元件 100: Vertical Hall magnetic field sensing element
110:半導體基板 110:Semiconductor substrate
111,112:深層佈植層 111,112: Deep implantation layer
121~126:淺層佈植層 121~126: Shallow planting layer
130:電流阻擋層 130: Current blocking layer
131~136:N型井區 131~136: N-type well area
141~146:導體接墊 141~146: Conductor pads
151,152:通道 151,152: Channel
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