TWI846308B - Circuit board for semiconductor testing and manufacturing method thereof - Google Patents

Abstract

A circuit board for semiconductor testing includes a first and a second substrate, a first and a second interlayer respectively attached to the lower surface of the first substrate and the upper surface of the second substrate, an adhesive layer attached between the first and the second interlayers, a first and a second welding unit respectively disposed in the first and the second through holes of the first and the second interlayers and including a chemical tinning layer and a flux, and a copper core ball disposed in a third through hole of the adhesive layer connected to the first and the second through holes, the copper core ball being electrically connected to the conductive contacts of the first and the second substrates through the first and the second welding units. The present invention further provides a method for manufacturing the aforementioned circuit board. Thus, the present invention can improve the electrical open circuit problem caused by connecting multiple substrates through an interlayer, thereby improving the circuit integrity.

Description

Circuit board for semiconductor testing and manufacturing method thereof

The present invention relates to a circuit board, and in particular to a circuit board for semiconductor testing and a method for manufacturing the same.

In the field of semiconductor testing, a probe card is used as an interface between the tester and the object to be tested (such as the die on the wafer). The probe card mainly includes a circuit board and multiple probes. A space converter may also be set between the circuit board and the probes. When the probe card is testing the object to be tested, the probe will touch the conductive contacts of the object to be tested, and the circuit board will be electrically connected to the tester, so that the circuit board receives the test signal output by the tester and then transmits it to the object to be tested through the probe, or receives the test result of the object to be tested through the probe and then transmits it to the tester through the circuit board.

In the manufacturing process of the circuit board, there is a certain aspect ratio limitation when drilling holes in the substrate. Therefore, it is difficult to reduce the hole diameter of a thick substrate, making it difficult for the area of the circuit board to meet the requirements of miniaturization. To solve this problem, a circuit board is known to replace a single thick substrate with a structure of stacking multiple substrates. For example, the circuit board 10 shown in FIG. 1 includes a first substrate 11, a second substrate 12, and an intermediate layer 13 disposed between the first and second substrates 11, 12. The first and second substrates 11, 12 and the intermediate layer 13 are drilled as required before being stacked on each other, and the upper and lower surfaces 112, 114 of the first substrate 11 and the upper and lower surfaces 122, 124 of the second substrate 12 are respectively provided with conductive contacts 14 as required. When the first and second substrates 11, 12 and the interposer 13 are stacked, the lower surface 132 of the interposer 13 is first attached to the upper surface 122 of the second substrate 12, and a tin-containing conductive material 15 is placed in the through-hole of the interposer 13. Then, the lower surface 114 of the first substrate 11 is attached to the upper surface 134 of the interposer 13, and the conductive material 15 is reflowed. In this way, the first and second substrates 11, 12 can be bonded to each other by using the interposer 13 as a bonding material, and the circuits of the first and second substrates 11, 12 are electrically connected by using the conductive material 15 in the through-hole of the interposer 13. Although this method can produce a thick and small circuit board under the aspect ratio limit of drilling processing, there will be a problem that the interlayer and the first or second substrate cannot be smoothly attached, which will cause an electrical open circuit problem, as described below.

Referring to FIG. 1 and FIG. 2 , the circuit board 10 can be divided into a central area 16 (also called a BGA area) located in the center of the circuit board 10 and a peripheral area 17 (also called a pogo area) adjacent to the periphery of the circuit board 10 by its upper surface (i.e., the upper surface 112 of the first substrate 11) or lower surface (i.e., the lower surface 124 of the second substrate 12). The upper surface 112 of the circuit board 10 is the tester side, and the conductive contacts 14 located in the peripheral area 17 of the upper surface 112 of the circuit board 10 are electrically connected to the tester (not shown). The lower surface 124 of the circuit board 10 is the side of the object to be tested. The conductive contacts 14 of the lower surface 124 of the circuit board 10 in the central area 16 are directly electrically connected to the probe (not shown) or indirectly electrically connected to the probe through a space converter (not shown). Based on the aforementioned electrical connection relationship, the conductive contacts 14 in the central area 16 of the circuit board 10 of the probe card are arranged more densely than the conductive contacts 14 in the peripheral area 17, so the spacing of the conductive contacts 14 in the central area 16 is smaller than the spacing of the conductive contacts 14 in the peripheral area 17.

As can be seen from the above, the lower surface 114 of the first substrate 11 and the upper surface 122 of the second substrate 12 present a more dense arrangement of the conductive contacts 14 in the central area 16 than in the peripheral area 17, that is, there will be an uneven copper layer pattern. Although the intermediate layer 13 can be made of a flexible material to absorb the unevenness of the mating surface, it is difficult to solve the problem that both mating surfaces are uneven. More specifically, when the lower surface 132 of the interposer 13 is attached to the upper surface 122 of the second substrate 12, the unevenness of the upper surface 122 of the second substrate 12 can be absorbed, so that the conductive material 15 in the through hole of the interposer 13 can be attached to the conductive contact 14 on the upper surface 122 of the second substrate 12. However, when the lower surface 114 of the first substrate 11 is attached to the upper surface 134 of the interposer 13, the interposer 13 cannot absorb the unevenness of the lower surface 114 of the first substrate 11, so that the conductive material 15 in the through hole of the interposer 13 cannot be attached to the conductive contact 14 on the lower surface 114 of the first substrate 11, resulting in the circuit of the first substrate 11 and the circuit of the second substrate 12 being unable to be electrically connected to each other, resulting in an electrical open circuit problem.

In view of the above shortcomings, the main purpose of the present invention is to provide a circuit board for semiconductor testing and a manufacturing method thereof, which can improve the electrical open circuit problem caused by connecting multiple substrates through an interposer, thereby improving the circuit integrity.

To achieve the above-mentioned purpose, the circuit board for semiconductor testing provided by the present invention includes a first substrate, a second substrate, a first interposer, a second interposer, an adhesive layer, a first welding unit, a second welding unit, and a copper core ball. The first substrate includes a lower surface and a first conductive contact located on the lower surface of the first substrate. The second substrate includes an upper surface and a second conductive contact located on the upper surface of the second substrate. The first interposer includes an upper surface, a lower surface, and a first through hole. The upper surface of the first interposer is attached to the lower surface of the first substrate. The first through hole includes an upper end and a lower end. The upper end of the first through hole is directly connected to the first conductive contact, and the lower end of the first through hole is located on the lower surface of the first interposer. The second intermediary layer includes an upper surface, a lower surface and a second through hole. The lower surface of the second intermediary layer is attached to the upper surface of the second substrate. The second through hole includes an upper end and a lower end. The lower end of the second through hole is directly connected to the second conductive contact. The upper end of the second through hole is located on the upper surface of the second intermediary layer. The adhesive layer includes an upper surface, a lower surface and a third through hole. The upper surface and the lower surface of the adhesive layer are attached to the lower surface of the first intermediary layer and the upper surface of the second intermediary layer respectively. The third through hole is connected to the first through hole and the second through hole. The first welding unit is arranged in the first through hole. The first welding unit includes a first chemical tinning layer arranged on the first conductive contact and a first flux. The second welding unit is disposed in the second through hole, and the second welding unit includes a second chemical tin plating layer disposed on the second conductive contact, and a second flux. The copper core ball is disposed in the third through hole, and the copper core ball is electrically connected to the first conductive contact and the second conductive contact through the first welding unit and the second welding unit, respectively.

To achieve the above-mentioned purpose, the present invention provides a method for manufacturing a circuit board for semiconductor testing, the steps of which include: providing a first substrate and a second substrate, the first substrate including a lower surface and a first conductive contact located on the lower surface of the first substrate, the second substrate including an upper surface and a second conductive contact located on the upper surface of the second substrate; attaching an upper surface of a first interposer to the lower surface of the first substrate, and drilling a first through hole in the first interposer, so that an upper end of the first through hole is directly connected to the first conductive contact, and a lower end of the first through hole is located on a lower surface of the first interposer; attaching a lower surface of a second interposer to the upper surface of the second substrate, and drilling a second through hole in the second interposer, so that a lower end of the second through hole is directly connected to the second conductive contact, and an upper end of the second through hole is located on a lower surface of the second interposer. a first soldering unit is disposed in the first through hole, the first soldering unit includes a first chemical tinning layer disposed on the first conductive contact, and a first flux; a second soldering unit is disposed in the second through hole, the second soldering unit includes a second chemical tinning layer disposed on the second conductive contact, and a second flux; a lower surface of an adhesive layer is attached to the upper surface of the second intermediate layer, the adhesive layer includes Contains a third through hole connected to the second through hole; A copper core ball is placed in the third through hole, and a first reflow is performed, so that the copper core ball is electrically connected to the second conductive contact through the second welding unit; and the lower surface of the first intermediate layer is attached to an upper surface of the adhesive layer, so that the first through hole is connected to the third through hole, and a second reflow is performed, so that the copper core ball is electrically connected to the first conductive contact through the first welding unit.

Thus, the aforementioned manufacturing method can manufacture the aforementioned circuit board. During the manufacturing process, the upper surface of the first interlayer can absorb the unevenness of the lower surface of the first substrate, and the lower surface of the second interlayer can absorb the unevenness of the upper surface of the second substrate. Therefore, the lower surface of the first interlayer and the upper surface of the second interlayer are bonded to the adhesive layer quite flatly, so that the copper core ball can be electrically connected to the first conductive contact and the second conductive contact reliably, thereby avoiding the problem of electrical open circuit after the circuit board is manufactured. Moreover, if the first and second interlayers are not sticky enough after being attached to the first and second substrates respectively, the first and second interlayers cannot be attached to each other. However, the present invention provides an adhesive layer between the first and second interlayers to ensure that the first and second interlayers can be attached through the adhesive layer. In this way, all layers of the circuit board can be attached flatly and stably.

In addition, the first and second chemical tin plating layers are provided on the first and second conductive contacts. Compared with the mass of the copper core ball, the first and second chemical tin plating layers only need to have a very small mass to ensure that the copper core ball can be bonded to the first and second conductive contacts during the first and second reflows, and can increase the bonding area, so that the copper core ball can be electrically connected to the first and second conductive contacts reliably, thereby improving the circuit integrity. Moreover, when the copper core ball is set in the third through hole but has not yet been reflowed, the bottom of the copper core ball may (but not limited to) be set in the second through hole. The third through hole or the second and third through holes will accommodate most of the volume of the copper core ball and effectively limit the position of the copper core ball, so as to prevent the copper core ball from leaving its predetermined position due to static electricity or other factors and causing the adjacent first conductive contact to short-circuit. After the first reflow is completed, the copper core ball is fixed to the second conductive contact and will no longer move due to static electricity or other factors. Since the copper core ball is solid, the top of the copper core ball can be protruded above the third through hole at this time, so as to facilitate the top of the copper core ball to enter the first through hole and then be electrically connected to the first conductive contact in the subsequent steps.

Furthermore, the first and second through holes are provided with the first and second fluxing agents. Compared with the conventional method of reflowing with tin-containing conductive materials, the contact area between the copper core ball and the first and second conductive contacts used in the present invention is small, so the amount of the first and second fluxing agents required is relatively small, which can improve the bonding effect between the copper core ball and the first and second chemically tinned layers during the first and second reflowing.

Preferably, the width of the third through hole is greater than the width of the first through hole. This makes it easier to place the copper core ball in the third through hole and also makes it easier to align the first through hole with the third through hole when the lower surface of the first intermediate layer is attached to the upper surface of the adhesive layer.

Preferably, the width of the first through hole is equal to the width of the second through hole. In this way, the width of the third through hole is also greater than the width of the second through hole, so that when the lower surface of the adhesive layer is attached to the upper surface of the second intermediate layer, it is easier to align the third through hole with the second through hole. Moreover, since the copper core ball is a sphere, its top and bottom widths are small and equal, so the first through hole and the second through hole can be designed to match the copper core ball and have equal widths and only slightly greater than the top and bottom widths of the copper core ball, so as to just accommodate the top and bottom of the copper core ball, and the middle part of the copper core ball has a relatively large width, which can be accommodated by the third through hole with a relatively large width.

Preferably, the width of the third through hole is greater than the width of the second through hole. This makes it easier to align the third through hole with the second through hole when the lower surface of the adhesive layer is attached to the upper surface of the second intermediate layer.

The detailed structure, features, assembly or use of the circuit board for semiconductor testing and the manufacturing method thereof provided by the present invention will be described in the detailed description of the implementation method to be described later. However, a person with ordinary knowledge in the field of the present invention should understand that the detailed description and the specific embodiments listed in the implementation of the present invention are only used to illustrate the present invention and are not used to limit the scope of the patent application of the present invention.

10: Circuit board

11: First substrate

112: Upper surface

114: Lower surface

12: Second substrate

122: Upper surface

124: Lower surface

13: Intermediate layer

132: Lower surface

134: Upper surface

14: Conductive contacts

15: Conductive materials

16: Central area

17: Outer area

20: Circuit board

30: First substrate

31: Lower surface

32: First conductive contact

33: Board

34: Longitudinal vias

35: Upper surface

36: First conductive contact

37: Conductive inner wall

38: Insulation Body

40: First intermediate layer

41: Upper surface

42: First through hole

421: Top

422: Lower end

43: Lower surface

50: Second intermediate layer

51: Lower surface

52: Second through hole

521: Lower end

522: Top

53: Upper surface

60: Second substrate

61: Upper surface

62: Second conductive contact

63: Plate

64: Longitudinal vias

65: Lower surface

66: Second conductive contact

67: Conductive inner wall

68: Insulation Body

70: Adhesive layer

71: Lower surface

72: The third through hole

73: Upper surface

80: Conductive connection structure

81: First welding unit

811: First chemical tinning layer

812: First flux

82: Second welding unit

821: Second chemical tinning layer

822: Second flux

83: Copper core ball

831: Copper Core

832: Tin shell

W1,W2,W3:Width

Figure 1 is a schematic cross-sectional view of a circuit board commonly used for semiconductor testing.

Figure 2 is a top view schematic diagram of a circuit board commonly used for semiconductor testing.

Figures 3 to 8 are cross-sectional schematic diagrams of a method for manufacturing a circuit board for semiconductor testing provided by a preferred embodiment of the present invention.

The applicant first explains that in the embodiments and drawings to be introduced below, the same reference numbers represent the same or similar elements or their structural features. It should be noted that the elements and structures in the drawings are drawn for the convenience of illustration and are not based on the actual proportions and quantities, and if possible in practice, the features of different embodiments can be applied interchangeably. Secondly, when it is mentioned that an element is set on another element, it means that the aforementioned element is directly set on the other element, or the aforementioned element is indirectly set on the other element, that is, one or more other elements are set between the two elements. When it is mentioned that an element is "directly" set on another element, it means that there are no other elements between the two elements.

Please refer to Figures 3 to 8. A circuit board 20 for semiconductor testing provided by a preferred embodiment of the present invention (as shown in Figure 8) includes a first substrate 30, a first interlayer 40, an adhesive layer 70, a second interlayer 50 and a second substrate 60 stacked from top to bottom, and a plurality of conductive connection structures 80 (the number is not limited). Each conductive connection structure 80 includes a first welding unit 81, a second welding unit 82, and a copper core ball 83.

The following describes the manufacturing method of the circuit board 20 and the detailed structure of each component of the circuit board 20. The steps of the manufacturing method of the present invention are not limited to the following sequence. If it is possible to implement, the steps can be changed or performed alternately. The steps of the manufacturing method of the circuit board 20 include:

a) As shown in FIG. 3 , a first substrate 30 and a second substrate 60 are provided. The first substrate 30 includes a lower surface 31 and a plurality of first conductive contacts 32 (the number is not limited) located on the lower surface 31. The second substrate 60 includes an upper surface 61 and a plurality of second conductive contacts 62 (the number is not limited) located on the upper surface 61.

It should be noted that the first substrate 30 and the second substrate 60 shown in the drawings of the present invention respectively include a plate body 33, 63, and a plurality of longitudinal conductive holes 34, 64. In fact, the first substrate 30 and the second substrate 60 are respectively a multi-layer circuit board formed by laminating multiple layers of substrates, the substrates are made of dielectric materials, and the surfaces of some of the substrates connected are provided with transverse conductive lines (not shown in the figure). After the substrates and the transverse conductive lines are manufactured, the longitudinal conductive holes 34, 64 are provided. In other words, each plate 33, 63 is actually composed of multiple layers of substrate, and each plate 33, 63 is provided with a transverse conductive line inside, but this part is not related to the technical features of the present invention. In order to simplify the diagram and facilitate explanation, the diagram of the present invention draws each plate 33, 63 as a whole and does not draw the transverse conductive line.

The aforementioned longitudinal conductive holes 34, 64 are usually electroplated through holes, which are first drilled through the plate bodies 33, 63 by means of mechanical drilling or laser drilling, and then copper is plated on the hole walls and openings at both ends of the through holes. Thus, the longitudinal conductive holes 34 of the first substrate 30 include not only the aforementioned first conductive contact 32 located on the lower surface 31, but also a first conductive contact 36 located on the upper surface 35, and a conductive inner wall 37 that electrically connects the first conductive contact 32 to the first conductive contact 36. Similarly, the longitudinal conductive hole 64 of the second substrate 60 includes not only the aforementioned second conductive contact 62 located on the upper surface 61, but also a second conductive contact 66 located on the lower surface 65, and a conductive inner wall 67 that electrically connects the second conductive contact 62 and the second conductive contact 66. In addition, the interior of each longitudinal conductive hole 34, 64 can be filled with an insulator 38, 68.

b) As shown in FIG. 4 , an upper surface 41 of the first interposer 40 is attached to the lower surface 31 of the first substrate 30 , and a plurality of first through holes 42 (the number is the same as the conductive connection structure 80 ) are drilled in the first interposer 40 , so that an upper end 421 of the first through hole 42 is directly connected to the first conductive contact 32 , and a lower end 422 of the first through hole 42 is located on a lower surface 43 of the first interposer 40 .

c) As shown in FIG. 4 , a lower surface 51 of the second interposer 50 is attached to an upper surface 61 of the second substrate 60 , and a plurality of second through holes 52 (the same number as the first through holes 42 ) are drilled in the second interposer 50 , so that a lower end 521 of the second through hole 52 is directly connected to the second conductive contact 62 , and an upper end 522 of the second through hole 52 is located on an upper surface 53 of the second interposer 50 .

In detail, the first and second interlayers 40 and 50 are flexible and sticky when attached to the first and second substrates 30 and 60. The upper surface 41 of the first interlayer 40 is directly attached to the lower surface 31 of the first substrate 30 and covers the first conductive contact 32. Although the first conductive contact 32 protrudes from the lower surface 31 of the first substrate 30 and makes the joint surface between the first substrate 30 and the first interlayer 40 uneven, the first interlayer 40 can absorb this unevenness by its flexibility. Similarly, the lower surface 51 of the second interposer 50 is directly attached to the upper surface 61 of the second substrate 60 and covers the second conductive contact 62. Although the second conductive contact 62 protrudes from the upper surface 61 of the second substrate 60, making the joint surface between the second substrate 60 and the second interposer 50 uneven, the second interposer 50 can absorb the unevenness due to its flexibility. Therefore, after the first and second interposers 40 and 50 are attached to the first and second substrates 30 and 60 respectively, the lower surface 43 of the first interposer 40 and the upper surface 53 of the second interposer 50 can still maintain flatness. For example, the first and second interlayers 40 and 50 may be build-up films, such as Ajinomoto build-up films (ABF) or other build-up films, which may be bonded to the first and second substrates 30 and 60 and then be in a flat solidified state (C-stage) by heat pressing. After the first and second interlayers 40 and 50 are bonded to the first and second substrates 30 and 60, the first through hole 42 and the second through hole 52 may be formed by, for example, mechanical drilling or laser drilling.

d) As shown in FIG. 5 , a first welding unit 81 is disposed in the first through hole 42. The first welding unit 81 includes a first chemical tin plating layer 811 disposed on the first conductive contact 32, and a first flux 812, which will be described in detail below.

e) As shown in FIG. 5 , a second welding unit 82 is disposed in the second through hole 52 , and the second welding unit 82 includes a second chemical tin plating layer 821 disposed on the second conductive contact 62 , and a second flux 822 , which will be described in detail below.

f) As shown in FIG. 6 , a lower surface 71 of the adhesive layer 70 is attached to the upper surface 53 of the second intermediate layer 50 , and the adhesive layer 70 includes a plurality of third through holes 72 (the number is the same as the second through holes 52 ) connected to the second through holes 52 .

Specifically, the adhesive layer 70 may be an insulating sheet made of a pre-impregnated material (also called pre-preg), which is in a semi-cured state (B-stage) with adhesiveness when attached to the second intermediate layer 50. Before attaching the adhesive layer 70 to the second intermediate layer 50, the adhesive layer 70 may pre-form third through holes 72 corresponding to the positions of the second through holes 52 (and also corresponding to the positions of the first through holes 42). In this embodiment, the width W1 of the third through hole 72 of the adhesive layer 70 is greater than the width W2 of the second through hole 52 of the second intermediary layer 50, so that when the lower surface 71 of the adhesive layer 70 is attached to the upper surface 53 of the second intermediary layer 50, it is easier to align the third through hole 72 with the second through hole 52, and in the subsequent step g), the copper core ball 83 can be more easily set in the third through hole 72, but the present invention is not limited to W1>W2.

g) As shown in FIG. 7 , the copper core ball 83 is placed in the third through hole 72 and the first reflow is performed so that the copper core ball 83 is electrically connected to the second conductive contact 62 through the second welding unit 82 . The copper core ball 83 has a copper core 831 and a tin shell 832 covering the copper core 831 .

In detail, during the first reflow in step g), the second chemical tin plating layer 821 (as shown in FIG. 5 ) of the second welding unit 82 is used as solder to weld the bottom of the tin shell 832 of the copper core ball 83 and the second conductive contact 62 to each other, so that the copper core ball 83 and the second conductive contact 62 are electrically connected, and the second flux 822 (as shown in FIG. 5 ) of the second welding unit 82 can ensure the bonding effect between the tin shell 832 of the copper core ball 83 and the second conductive contact 62. Since the copper core ball 83 is solid, the top of the copper core ball 83 can be protruded above the third through hole 72, as shown in FIG. 7, so as to facilitate the top of the copper core ball 83 to enter the first through hole 42 and then be electrically connected to the first conductive contact 32 in the subsequent step h).

h) As shown in FIG. 8 , the lower surface 43 of the first interposer 40 is attached to an upper surface 73 of the adhesive layer 70 so that the first through hole 42 is connected to the third through hole 72, and a second reflow is performed so that the copper core ball 83 is electrically connected to the first conductive contact 32 through the first welding unit 81.

Specifically, during the second reflow in step h), the first chemical tin plating layer 811 (as shown in FIG. 5 ) of the first welding unit 81 is used as solder to weld the top of the tin shell 832 (as shown in FIG. 7 ) of the copper core ball 83 to the first conductive contact 32 , so that the copper core ball 83 is electrically connected to the first conductive contact 32 , and then the first conductive contact 32 is electrically connected to the second conductive contact 62 , and the first flux 812 (as shown in FIG. 5 ) of the first welding unit 81 can ensure the bonding effect between the tin shell 832 of the copper core ball 83 and the first conductive contact 32 .

In step g) of the present embodiment, as shown in FIG. 7 , the copper core ball 83 is not only disposed in the third through hole 72, but the bottom of the copper core ball 83 is also disposed in the second through hole 52, but the present invention is not limited thereto. Before the copper core ball 83 undergoes the first reflow, the second and third through holes 52, 72 (or only the third through hole 72) will accommodate most of the volume of the copper core ball 83 and effectively limit the position of the copper core ball 83, thereby preventing the copper core ball 83 from leaving its predetermined position due to static electricity or other factors and causing the adjacent first conductive contact 32 to short-circuit. After the first reflow is completed, the copper core ball 83 is fixed to the second conductive contact 62 and will no longer move due to static electricity or other factors, so that step h) can be carried out smoothly.

As shown in FIG. 4 , in this embodiment, the width W3 of the first through hole 42 of the first intermediate layer 40 is equal to the width W2 of the second through hole 52 of the second intermediate layer 50, so the width W1 of the third through hole 72 of the adhesive layer 70 is also greater than the width W3 of the first through hole 42 of the first intermediate layer 40. With the feature of W1>W3, when the lower surface 43 of the first intermediate layer 40 is attached to the upper surface 73 of the adhesive layer 70 in step h), it is easier to align the first through hole 42 with the third through hole 72, but the present invention is not limited to W1>W3. In addition, since the copper core ball 83 is a sphere, its top and bottom widths are small and equal, the first through hole 42 and the second through hole 52 can be designed to match the copper core ball 83 and have equal widths (i.e. W3=W2) and only slightly larger than the top and bottom widths of the copper core ball 83, so as to just accommodate the top and bottom of the copper core ball 83. The middle part of the copper core ball 83 has a relatively large width, which can be accommodated by the third through hole 72 with a relatively large width, i.e. W1>W2=W3, but the present invention is not limited to this.

By the aforementioned steps a) to h), the circuit board 20 shown in FIG8 can be manufactured. As mentioned above, the lower surface 43 of the first interposer 40 and the upper surface 53 of the second interposer 50 will not be affected by the unevenness of the surfaces of the first and second substrates 30 and 60, so the lower surface 43 of the first interposer 40 and the upper surface 53 of the second interposer 50 are quite flatly attached to the adhesive layer 70, so that the copper core ball 83 can be electrically connected to the first conductive contact 32 and the second conductive contact 62, thereby avoiding the problem of electrical open circuit after the circuit board 20 is manufactured, thereby improving the circuit integrity. Moreover, if the first and second intermediate layers 40 and 50 have insufficient adhesiveness after being attached to the first and second substrates 30 and 60, respectively, the first and second intermediate layers 40 and 50 cannot be attached to each other. However, the present invention provides an adhesive layer 70 between the first and second intermediate layers 40 and 50 to ensure that the first and second intermediate layers 40 and 50 can be attached through the adhesive layer 70. In this way, the layers of the circuit board 20 can be attached flatly and stably.

In addition, the first and second chemical tin plating layers 811 and 821 are provided on the first and second conductive contacts 32 and 62 to improve the welding effect between the copper core ball 83 and the first and second conductive contacts 32 and 62. Without the first and second chemical tin plating layers 811 and 821, when the copper core ball 83 is reflowed for the first and second times, part of the tin will leave the place where the tin shell 832 is connected to the first and second conductive contacts 32 and 62, resulting in a poor welding effect. Compared to the mass of the copper core ball 83, the first and second chemical tin plating layers 811 and 821 only need a very small mass to ensure that the copper core ball 83 can be bonded to the first and second conductive contacts 32 and 62 during the first and second reflows, and the bonding area can be increased. This can also ensure that the copper core ball 83 is electrically connected to the first and second conductive contacts 32 and 62, thereby improving the circuit integrity.

Furthermore, the first and second through holes 42 and 52 are provided with the first and second fluxes 812 and 822. Compared with the conventional method of reflowing with tin-containing conductive materials, the contact area between the copper core ball 83 and the first and second conductive contacts 32 and 62 used in the present invention is small, so the amount of the first and second fluxes 812 and 822 required is relatively small, which can improve the bonding effect between the copper core ball 83 and the first and second chemically tinned layers 811 and 821 during the first and second reflows.

Finally, it must be reiterated that the components disclosed in the above-mentioned embodiments of the present invention are only for illustration and are not intended to limit the scope of the present invention. Replacements or changes of other equivalent components should also be covered by the scope of the patent application of this case.

20: Circuit board

30: First substrate

31: Lower surface

32: First conductive contact

40: First intermediate layer

41: Upper surface

42: First through hole

421: Top

422: Lower end

43: Lower surface

50: Second intermediate layer

51: Lower surface

52: Second through hole

521: Lower end

522: Top

53: Upper surface

60: Second substrate

61: Upper surface

62: Second conductive contact

70: Adhesive layer

71: Lower surface

72: The third through hole

73: Upper surface

80: Conductive connection structure

81: First welding unit

82: Second welding unit

83: Copper core ball

Claims (8)

A circuit board for semiconductor testing, comprising: A first substrate, comprising a lower surface, and a first conductive contact located on the lower surface of the first substrate; A second substrate, comprising an upper surface, and a second conductive contact located on the upper surface of the second substrate; A first interposer, comprising an upper surface, a lower surface, and a first through hole, the upper surface of the first interposer being attached to the lower surface of the first substrate, the first through hole comprising an upper end and a lower end, the upper end of the first through hole being directly connected to the first conductive contact, and the lower end of the first through hole being located on the lower surface of the first interposer; A second intermediary layer, comprising an upper surface, a lower surface and a second through hole, the lower surface of the second intermediary layer is attached to the upper surface of the second substrate, the second through hole comprises an upper end and a lower end, the lower end of the second through hole is directly connected to the second conductive contact, and the upper end of the second through hole is located on the upper surface of the second intermediary layer; A bonding layer, comprising an upper surface, a lower surface and a third through hole, the upper surface and the lower surface of the bonding layer are attached to the lower surface of the first intermediary layer and the upper surface of the second intermediary layer respectively, and the third through hole is connected to the first through hole and the second through hole; A first welding unit is disposed in the first through hole, the first welding unit comprises a first chemical tinning layer disposed on the first conductive contact, and a first flux; A second welding unit is disposed in the second through hole, the second welding unit includes a second chemical tinning layer disposed on the second conductive contact, and a second flux; and A copper core ball has a copper core and a tin shell covering the copper core, the copper core ball is disposed in the third through hole, and the copper core ball is electrically connected to the first conductive contact and the second conductive contact through the first welding unit and the second welding unit respectively. A circuit board for semiconductor testing as described in claim 1, wherein the width of the third through hole is greater than the width of the first through hole. A circuit board for semiconductor testing as described in claim 1 or 2, wherein the width of the first through hole is equal to the width of the second through hole. A circuit board for semiconductor testing as described in claim 1, wherein the width of the third through hole is greater than the width of the second through hole. A method for manufacturing a circuit board for semiconductor testing, the steps of which include: Providing a first substrate and a second substrate, the first substrate including a lower surface and a first conductive contact on the lower surface of the first substrate, the second substrate including an upper surface and a second conductive contact on the upper surface of the second substrate; Bonding an upper surface of a first interposer to the lower surface of the first substrate, and drilling a first through hole in the first interposer, so that an upper end of the first through hole is directly connected to the first conductive contact, and a lower end of the first through hole is located on a lower surface of the first interposer; Bonding a lower surface of a second interposer to the upper surface of the second substrate, and drilling a second through hole in the second interposer, so that a lower end of the second through hole is directly connected to the second conductive contact, and an upper end of the second through hole is located on an upper surface of the second interposer; A first welding unit is arranged in the first through hole, the first welding unit includes a first chemical tinning layer arranged on the first conductive contact, and a first flux; A second welding unit is arranged in the second through hole, the second welding unit includes a second chemical tinning layer arranged on the second conductive contact, and a second flux; A lower surface of an adhesive layer is attached to the upper surface of the second intermediate layer, the adhesive layer includes a third through hole connected to the second through hole; A copper core ball having a copper core and a tin shell covering the copper core is arranged in the third through hole, and a first reflow is performed, so that the copper core ball is electrically connected to the second conductive contact through the second welding unit; and The lower surface of the first intermediate layer is attached to an upper surface of the adhesive layer so that the first through hole is connected to the third through hole, and a second reflow is performed so that the copper core ball is electrically connected to the first conductive contact through the first welding unit. A method for manufacturing a circuit board for semiconductor testing as described in claim 5, wherein the width of the third through hole is greater than the width of the first through hole. A method for manufacturing a circuit board for semiconductor testing as described in claim 5 or 6, wherein the width of the first through hole is equal to the width of the second through hole. A method for manufacturing a circuit board for semiconductor testing as described in claim 5, wherein the width of the third through hole is greater than the width of the second through hole.

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