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TWI824495B - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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TWI824495B
TWI824495B TW111115009A TW111115009A TWI824495B TW I824495 B TWI824495 B TW I824495B TW 111115009 A TW111115009 A TW 111115009A TW 111115009 A TW111115009 A TW 111115009A TW I824495 B TWI824495 B TW I824495B
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TW202324759A (en
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楊謹嘉
陳文斌
陳祖偉
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友達光電股份有限公司
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Abstract

A semiconductor device includes a substrate, a metal oxide semiconductor layer, a first gate, a source and a drain. The material of the metal oxide semiconductor layer includes at least one of indium zinc oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc tin oxide, indium gallium tin oxide, and indium gallium zinc tin oxide. The metal oxide semiconductor layer includes a first doped region, a second doped region, a channel region between the first doped region and the second doped region, a first crystalline region located in the first doped region, and a second crystalline region located in the second doped region. The crystallinity of the first crystalline region and the second crystalline region is greater than the crystallinity of the channel region. The source and the drain are respectively electrically connected to the first crystalline region and the second crystalline region.

Description

半導體裝置及其製造方法Semiconductor device and manufacturing method thereof

本發明是有關於一種半導體裝置，且特別是有關於一種包含金屬氧化物半導體層的半導體裝置及其製造方法。 The present invention relates to a semiconductor device, and in particular, to a semiconductor device including a metal oxide semiconductor layer and a manufacturing method thereof.

目前，常見的薄膜電晶體通常以非晶矽半導體作為通道，其中非晶矽半導體由於製程簡單且成本低廉，因此已廣泛的應用於各種薄膜電晶體中。 At present, common thin film transistors usually use amorphous silicon semiconductors as channels. Amorphous silicon semiconductors have been widely used in various thin film transistors due to their simple manufacturing process and low cost.

氧化銦鎵鋅(indium gallium zinc oxide，IGZO)同時具有面積小以及載子遷移率高的優點，因此被視為一種重要的新型半導體材料。然而，在氧化銦鎵鋅製備的電晶體中，電極與氧化銦鎵鋅的接觸不佳，影響了能夠通過電晶體的電流流量。因此，目前亟需一種可以解決前述問題的方法。 Indium gallium zinc oxide (IGZO) has the advantages of small area and high carrier mobility, so it is regarded as an important new semiconductor material. However, in transistors made of indium gallium zinc oxide, the electrodes have poor contact with the indium gallium zinc oxide, which affects the flow of current that can pass through the transistor. Therefore, a method that can solve the aforementioned problems is urgently needed.

本發明提供一種半導體裝置，可以改善金屬氧化物半導體層與源極以及之間以及金屬氧化物半導體層與汲極之間接觸不 佳的問題。 The present invention provides a semiconductor device that can improve the contact tightness between a metal oxide semiconductor layer and a source electrode and between a metal oxide semiconductor layer and a drain electrode. Good question.

本發明提供一種半導體裝置的製造方法，可以改善金屬氧化物半導體層與源極以及之間以及金屬氧化物半導體層與汲極之間接觸不佳的問題。 The present invention provides a method for manufacturing a semiconductor device, which can improve the problem of poor contact between a metal oxide semiconductor layer and a source electrode and between a metal oxide semiconductor layer and a drain electrode.

本發明的至少一實施例提供一種半導體裝置。半導體裝置包括基板、金屬氧化物半導體層、第一閘極、源極以及汲極。金屬氧化物半導體層位於基板之上。金屬氧化物半導體層的材料包括銦鋅氧化物、銦鎢氧化物、銦鎢鋅氧化物、銦鋅錫氧化物、銦鎵錫氧化物以及銦鎵鋅錫氧化物中的至少一者。金屬氧化物半導體層包括第一摻雜區、第二摻雜區、位於第一摻雜區與第二摻雜區之間的通道區、位於第一摻雜區中的第一結晶區以及位於第二摻雜區中的第二結晶區。第一結晶區與第二結晶區的結晶度大於通道區的結晶度。通道區的載子遷移率為30cm2/Vs至100cm2/Vs，且通道區的銦濃度為25mol%至40mol%。第一閘極重疊於金屬氧化物半導體層的通道區。源極以及汲極分別電性連接第一結晶區與第二結晶區。 At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a metal oxide semiconductor layer, a first gate, a source and a drain. A metal oxide semiconductor layer is located on the substrate. The material of the metal oxide semiconductor layer includes at least one of indium zinc oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc tin oxide, indium gallium tin oxide and indium gallium zinc tin oxide. The metal oxide semiconductor layer includes a first doped region, a second doped region, a channel region located between the first doped region and the second doped region, a first crystallized region located in the first doped region, and a channel region located between the first doped region and the second doped region. A second crystallized region in the second doped region. The crystallinity of the first crystallization region and the second crystallization region is greater than the crystallinity of the channel region. The carrier mobility of the channel region is 30 cm 2 /Vs to 100 cm 2 /Vs, and the indium concentration of the channel region is 25 mol% to 40 mol%. The first gate overlaps the channel region of the metal oxide semiconductor layer. The source electrode and the drain electrode are electrically connected to the first crystal region and the second crystal region respectively.

本發明的至少一實施例提供一種半導體裝置的製造方法，包括：形成金屬氧化物層於基板之上，且金屬氧化物層的材料包括銦鋅氧化物、銦鎢氧化物、銦鎢鋅氧化物、銦鋅錫氧化物、銦鎵錫氧化物以及銦鎵鋅錫氧化物中的至少一者；形成第一閘極，第一閘極重疊於金屬氧化物層；對金屬氧化物層執行摻雜製程，以形成經摻雜的金屬氧化物層；形成源極以及汲極，源極以 及汲極分別連接經摻雜的金屬氧化物層；對經摻雜的金屬氧化物層執行退火製程，以形成金屬氧化物半導體層，其中金屬氧化物半導體層包括第一摻雜區、第二摻雜區、位於第一摻雜區與第二摻雜區之間的通道區位於第一摻雜區中的第一結晶區以及位於第二摻雜區中的第二結晶區，且第一結晶區與第二結晶區的結晶度大於通道區的結晶度，其中通道區的載子遷移率為30cm2/Vs至100cm2/Vs，且通道區的銦濃度為25mol%至40mol%。 At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, including: forming a metal oxide layer on a substrate, and the material of the metal oxide layer includes indium zinc oxide, indium tungsten oxide, and indium tungsten zinc oxide. , at least one of indium zinc tin oxide, indium gallium tin oxide and indium gallium zinc tin oxide; forming a first gate, the first gate overlapping the metal oxide layer; performing doping on the metal oxide layer process to form a doped metal oxide layer; form a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively connected to the doped metal oxide layer; perform an annealing process on the doped metal oxide layer to A metal oxide semiconductor layer is formed, wherein the metal oxide semiconductor layer includes a first doping region, a second doping region, and a channel region located between the first doping region and the second doping region and is located in the first doping region. The first crystallization region and the second crystallization region located in the second doped region, and the crystallinity of the first crystallization region and the second crystallization region is greater than the crystallinity of the channel region, wherein the carrier mobility of the channel region is 30 cm 2 /Vs to 100cm 2 /Vs, and the indium concentration in the channel area is 25mol% to 40mol%.

10,20,30,40,50:半導體裝置 10,20,30,40,50:Semiconductor device

100:基板 100:Substrate

102:介電層 102:Dielectric layer

110:閘介電層 110: Gate dielectric layer

110a,120a:介電層 110a,120a: dielectric layer

120:層間介電層 120: Interlayer dielectric layer

210:金屬氧化物半導體層 210: Metal oxide semiconductor layer

210’:經摻雜的金屬氧化物層 210’: Doped metal oxide layer

210”:金屬氧化物層 210”: Metal oxide layer

212:第一結晶區 212: First crystallization zone

214:第一摻雜區 214: First doped region

215:通道區 215: Passage area

216:第二摻雜區 216: Second doping region

218:第二結晶區 218: Second crystallization zone

220,220A:第一閘極 220,220A: first gate

220B:第二閘極 220B: Second gate

242:源極 242:Source

243:第一氧化物層 243: First oxide layer

244:汲極 244:Jiji

245:第二氧化物層 245: Second oxide layer

P:摻雜製程 P: doping process

R:區域 R:Region

TH1:第一通孔 TH1: first through hole

TH2:第二通孔 TH2: Second through hole

圖1A是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 1A is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

圖1B是圖1A的半導體裝置的局部上視示意圖。 FIG. 1B is a partial top view of the semiconductor device of FIG. 1A .

圖2A至圖2E是圖1A的半導體裝置的製造方法的剖面示意圖。 2A to 2E are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 1A .

圖3是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 FIG. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

圖4A至圖4D是圖3的半導體裝置的製造方法的剖面示意圖。 4A to 4D are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 3 .

圖5是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 FIG. 5 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

圖6是依照本發明的一實施例的一種半導體裝置的剖面示意 圖。 FIG. 6 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. Figure.

圖7A是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 FIG. 7A is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

圖7B是圖7A的半導體裝置的局部上視示意圖。 FIG. 7B is a partial top view of the semiconductor device of FIG. 7A.

圖8是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 FIG. 8 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

圖9是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 FIG. 9 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

圖10是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 FIG. 10 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

圖11A是依照本發明的一實施例的一種半導體裝置的高解析率穿透式電子顯微鏡照片。 FIG. 11A is a high-resolution transmission electron microscope photograph of a semiconductor device according to an embodiment of the present invention.

圖11B是圖11A的區域R的奈米束電子繞射照片。 FIG. 11B is a nanobeam electron diffraction photograph of the region R in FIG. 11A .

圖12A是依照本發明的一實施例的一種半導體裝置的高解析率穿透式電子顯微鏡照片。 FIG. 12A is a high-resolution transmission electron microscope photograph of a semiconductor device according to an embodiment of the present invention.

圖12B是圖12A的區域R的奈米束電子繞射(nano beam electron diffraction，NBED)照片。 FIG. 12B is a nanobeam electron diffraction (NBED) photograph of the region R in FIG. 12A .

圖1A是依照本發明的一實施例的一種半導體裝置的剖面示意圖。圖1B是圖1A的半導體裝置的局部上視示意圖。圖1B繪示了介電層102、金屬氧化物半導體層210以及第一閘極220， 並省略繪示其他構件。 1A is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 1B is a partial top view of the semiconductor device of FIG. 1A . FIG. 1B illustrates the dielectric layer 102, the metal oxide semiconductor layer 210 and the first gate 220. Other components are omitted from the drawing.

請參考圖1A與圖1B，半導體裝置10包括基板100、金屬氧化物半導體層210、第一閘極220、源極242以及汲極244。在本實施例中，半導體裝置10還包括第一氧化物層243、第二氧化物層245、介電層102、閘介電層110、以及層間介電層120。 Referring to FIGS. 1A and 1B , the semiconductor device 10 includes a substrate 100 , a metal oxide semiconductor layer 210 , a first gate 220 , a source 242 and a drain 244 . In this embodiment, the semiconductor device 10 further includes a first oxide layer 243, a second oxide layer 245, a dielectric layer 102, a gate dielectric layer 110, and an interlayer dielectric layer 120.

基板100的材料例如為玻璃、石英、有機聚合物或不透光/反射材料(例如：導電材料、金屬、晶圓、陶瓷或其他可適用的材料)或是其他可適用的材料。在一些實施例中，基板100包括硬質基板或可撓性基板。 The material of the substrate 100 is, for example, glass, quartz, organic polymer, opaque/reflective material (such as conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. In some embodiments, the substrate 100 includes a rigid substrate or a flexible substrate.

介電層102形成於基板100上。介電層102包括單層或多層結構。在一些實施例中，介電層102的材料例如為氧化矽、氮化矽、氮氧化矽、氧化鋁、氧化鉿、有機絕緣材料或其他合適的絕緣材料。在一些實施例中，介電層102與基板100之間還包括其他金屬材料(未示出)或吸光材料(未示出)，但本發明不以此為限。 The dielectric layer 102 is formed on the substrate 100 . Dielectric layer 102 includes a single layer or a multi-layer structure. In some embodiments, the material of the dielectric layer 102 is, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, organic insulating materials or other suitable insulating materials. In some embodiments, other metal materials (not shown) or light-absorbing materials (not shown) are also included between the dielectric layer 102 and the substrate 100, but the invention is not limited thereto.

金屬氧化物半導體層210位於基板100之上。在本實施例中，金屬氧化物半導體層210形成於介電層102上。金屬氧化物半導體層210包括第一摻雜區214、第二摻雜區216、位於第一摻雜區214與第二摻雜區216之間的通道區215、位於第一摻雜區214中的第一結晶區212以及位於第二摻雜區216中的第二結晶區218。第一結晶區212與第二結晶區218的結晶度大於通道區215的結晶度。在一些實施例中，第一結晶區212與第二結晶區218 的結晶度大於第一摻雜區214與第二摻雜區216的結晶度。在一些實施例中，通道區215、第一摻雜區214與第二摻雜區216皆為非晶質。 The metal oxide semiconductor layer 210 is located on the substrate 100 . In this embodiment, the metal oxide semiconductor layer 210 is formed on the dielectric layer 102 . The metal oxide semiconductor layer 210 includes a first doped region 214, a second doped region 216, a channel region 215 located between the first doped region 214 and the second doped region 216, and a channel region 215 located in the first doped region 214. The first crystallized region 212 and the second crystallized region 218 located in the second doped region 216. The crystallinity of the first crystallization region 212 and the second crystallization region 218 is greater than the crystallinity of the channel region 215 . In some embodiments, the first crystallization region 212 and the second crystallization region 218 The crystallinity is greater than the crystallinity of the first doped region 214 and the second doped region 216 . In some embodiments, the channel region 215, the first doped region 214 and the second doped region 216 are all amorphous.

在本實施例中，第一結晶區212被第一摻雜區214所環繞，且第一結晶區212分離於金屬氧化物半導體層210的側壁。類似地，第二結晶區218被第二摻雜區216所環繞，且第二結晶區218分離於金屬氧化物半導體層210的側壁。 In this embodiment, the first crystallized region 212 is surrounded by the first doped region 214 , and the first crystallized region 212 is separated from the sidewall of the metal oxide semiconductor layer 210 . Similarly, the second crystallized region 218 is surrounded by the second doped region 216 , and the second crystallized region 218 is separated from the sidewall of the metal oxide semiconductor layer 210 .

在一些實施例中，第一摻雜區214、第二摻雜區216、第一結晶區212以及第二結晶區218為經氫摻雜的區域，且第一摻雜區214、第二摻雜區216、第一結晶區212以及第二結晶區218的氫濃度大於通道區215的氫濃度。 In some embodiments, the first doped region 214 , the second doped region 216 , the first crystallized region 212 and the second crystallized region 218 are hydrogen-doped regions, and the first doped region 214 , the second doped region 216 and the second crystallized region 218 are hydrogen-doped regions. The hydrogen concentration of the impurity region 216 , the first crystallization region 212 and the second crystallization region 218 is greater than the hydrogen concentration of the channel region 215 .

金屬氧化物半導體層210的材料包括銦鋅氧化物(indium zinc oxide，IZO)、銦鎢氧化物(indium tungsten oxide，IWO)、銦鎢鋅氧化物(indium tungsten zinc oxide，IWZO)、銦鋅錫氧化物(indium zinc tin oxide，IZTO)、銦鎵錫氧化物(indium gallium tin oxide，IGTO)以及銦鎵鋅錫氧化物(indium gallium zinc tin oxide，IGZTO)中的至少一者。在本實施例中，相較於一般的銦鎵鋅氧化物(indium gallium zinc oxide，IGZO)，金屬氧化物半導體層210具有較高的載子遷移率。 The material of the metal oxide semiconductor layer 210 includes indium zinc oxide (IZO), indium tungsten oxide (IWO), indium tungsten zinc oxide (IWZO), indium zinc tin At least one of indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), and indium gallium zinc tin oxide (IGZTO). In this embodiment, compared with general indium gallium zinc oxide (IGZO), the metal oxide semiconductor layer 210 has higher carrier mobility.

在一些實施例中，第一結晶區212以及第二結晶區218的載子遷移率大於第一摻雜區214以及第二摻雜區216的載子遷移率，且第一摻雜區214以及第二摻雜區216的載子遷移率大於 通道區215的載子遷移率。 In some embodiments, the carrier mobility of the first crystallized region 212 and the second crystallized region 218 is greater than the carrier mobility of the first doped region 214 and the second doped region 216 , and the first doped region 214 and The carrier mobility of the second doped region 216 is greater than Carrier mobility in channel region 215.

在一些實施例中，第一結晶區212以及第二結晶區218的銦濃度大於第一摻雜區214以及第二摻雜區216的銦濃度以及通道區215的銦濃度。在一些實施例中，第一結晶區212以及第二結晶區218的銦濃度為30mol%至50mol%，第一摻雜區214以及第二摻雜區216的銦濃度為25mol%至40mol%，且通道區215的銦濃度為25mol%至40mol%。 In some embodiments, the indium concentration of the first crystallized region 212 and the second crystallized region 218 is greater than the indium concentration of the first doped region 214 and the second doped region 216 and the indium concentration of the channel region 215 . In some embodiments, the indium concentration of the first crystallized region 212 and the second crystallized region 218 is 30 mol% to 50 mol%, and the indium concentration of the first doped region 214 and the second doped region 216 is 25 mol% to 40 mol%. And the indium concentration of the channel area 215 is 25 mol% to 40 mol%.

在一些實施例中，金屬氧化物半導體層210的厚度為100埃至500埃。 In some embodiments, metal oxide semiconductor layer 210 has a thickness of 100 angstroms to 500 angstroms.

閘介電層110形成於金屬氧化物半導體層210上。閘介電層110為單層或多層結構。在本實施例中，閘介電層110包覆金屬氧化物半導體層210的頂面以及側面，且具有重疊於部分第一摻雜區214以及部分第二摻雜區216的通孔。在一些實施例中，閘介電層110的材料例如為氧化矽、氮化矽、氮氧化矽、氧化鋁、氧化鉿、有機絕緣材料或其他合適的絕緣材料。在一些實施例中，閘介電層110的厚度為50奈米至300奈米。 The gate dielectric layer 110 is formed on the metal oxide semiconductor layer 210 . The gate dielectric layer 110 has a single-layer or multi-layer structure. In this embodiment, the gate dielectric layer 110 covers the top surface and side surfaces of the metal oxide semiconductor layer 210 and has a through hole overlapping a portion of the first doped region 214 and a portion of the second doped region 216 . In some embodiments, the material of the gate dielectric layer 110 is, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, organic insulating materials or other suitable insulating materials. In some embodiments, the gate dielectric layer 110 has a thickness of 50 nanometers to 300 nanometers.

第一閘極220形成於閘介電層110上。第一閘極220重疊於金屬氧化物半導體層210的通道區215。金屬氧化物半導體層210位於第一閘極220與基板100之間。在一些實施例中，第一閘極220的材料包括金屬，例如銀、銅、鉬、鋁、鈦、金、鉑或上述金屬的合金或上述金屬的堆疊層或其他材料。 The first gate 220 is formed on the gate dielectric layer 110 . The first gate 220 overlaps the channel region 215 of the metal oxide semiconductor layer 210 . The metal oxide semiconductor layer 210 is located between the first gate 220 and the substrate 100 . In some embodiments, the material of the first gate 220 includes metal, such as silver, copper, molybdenum, aluminum, titanium, gold, platinum or alloys of the above metals or stacked layers of the above metals or other materials.

層間介電層120形成於閘介電層110上，且具有重疊於 部分第一摻雜區214以及部分第二摻雜區216的通孔。層間介電層120包覆第一閘極220。在一些實施例中，層間介電層120的材料例如為氧化矽、氮化矽、氮氧化矽、氧化鋁、氧化鉿、有機絕緣材料或其他合適的絕緣材料或上述材料的堆疊層。在一些實施例中，層間介電層120的厚度為50奈米至600奈米。 The interlayer dielectric layer 120 is formed on the gate dielectric layer 110 and has an overlapping Through holes of part of the first doped region 214 and part of the second doped region 216 . The interlayer dielectric layer 120 covers the first gate 220 . In some embodiments, the material of the interlayer dielectric layer 120 is, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, organic insulating materials or other suitable insulating materials or stacked layers of the above materials. In some embodiments, the interlayer dielectric layer 120 has a thickness of 50 nanometers to 600 nanometers.

源極242以及汲極244形成於層間介電層120，並填入層間介電層120以及閘介電層110的第一通孔TH1與第二通孔TH2，以分別電性連接金屬氧化物半導體層210的第一結晶區212與第二結晶區218。第一通孔TH1在基板100的頂面的法線方向上重疊於第一結晶區212，且第二通孔TH2在基板100的頂面的法線方向上重疊於第二結晶區218。在一些實施例中，第一通孔TH1的底部於基板100上的垂直投影面積小於第一結晶區212於基板100上的垂直投影面積，且第二通孔TH2的底部於基板100上的垂直投影面積小於第二結晶區218於基板100上的垂直投影面積。 The source electrode 242 and the drain electrode 244 are formed in the interlayer dielectric layer 120 and filled in the first through hole TH1 and the second through hole TH2 of the interlayer dielectric layer 120 and the gate dielectric layer 110 to electrically connect the metal oxide respectively. The first crystallization region 212 and the second crystallization region 218 of the semiconductor layer 210 . The first through hole TH1 overlaps the first crystallization region 212 in the normal direction of the top surface of the substrate 100 , and the second through hole TH2 overlaps the second crystallization region 218 in the normal direction of the top surface of the substrate 100 . In some embodiments, the vertical projected area of the bottom of the first through hole TH1 on the substrate 100 is smaller than the vertical projected area of the first crystal region 212 on the substrate 100 , and the vertical projected area of the bottom of the second through hole TH2 on the substrate 100 is smaller than the vertical projected area of the bottom of the first through hole TH1 on the substrate 100 . The projected area is smaller than the vertical projected area of the second crystal region 218 on the substrate 100 .

第一氧化物層243位於源極242與第一結晶區212之間，且第二氧化物層245位於汲極244與第二結晶區218之間。 The first oxide layer 243 is located between the source electrode 242 and the first crystallized region 212 , and the second oxide layer 245 is located between the drain electrode 244 and the second crystallized region 218 .

在一些實施例中，源極242以及汲極244的材料包括鈦元素。舉例來說，源極242以及汲極244各自為鈦金屬、鈦金屬/鋁金屬/鈦金屬的堆疊層、鈦合金或其他合適的材料。在一些實施例中，第一氧化物層243與第二氧化物層245包含氧元素以及源極242與汲極244中的金屬元素(例如鈦元素)。舉例來說，第一 氧化物層243與第二氧化物層245包含氧化鈦。 In some embodiments, the source electrode 242 and the drain electrode 244 are made of titanium. For example, the source electrode 242 and the drain electrode 244 are each made of titanium metal, a stacked layer of titanium metal/aluminum metal/titanium metal, titanium alloy, or other suitable materials. In some embodiments, the first oxide layer 243 and the second oxide layer 245 include oxygen and metal elements (such as titanium) in the source electrode 242 and the drain electrode 244 . For example, first The oxide layer 243 and the second oxide layer 245 include titanium oxide.

基於上述，藉由第一結晶區212與第二結晶區218的存在，源極242與金屬氧化物半導體層210之間的接觸以及汲極244與金屬氧化物半導體層210之間的接觸可以改善，藉此提升通過半導體裝置10的電流量。在一些實施例中，第一氧化物層243與第二氧化物層245本身為不導電的材料，藉由第一氧化物層243與第二氧化物層245中的穿隧效應，使源極242與金屬氧化物半導體層210之間以及汲極244與金屬氧化物半導體層210之間具有歐姆接觸。 Based on the above, through the existence of the first crystallization region 212 and the second crystallization region 218, the contact between the source electrode 242 and the metal oxide semiconductor layer 210 and the contact between the drain electrode 244 and the metal oxide semiconductor layer 210 can be improved. , thereby increasing the amount of current passing through the semiconductor device 10 . In some embodiments, the first oxide layer 243 and the second oxide layer 245 themselves are non-conductive materials. Through the tunneling effect in the first oxide layer 243 and the second oxide layer 245, the source electrode There are ohmic contacts between 242 and the metal oxide semiconductor layer 210 and between the drain electrode 244 and the metal oxide semiconductor layer 210 .

圖2A至圖2E是圖1A的半導體裝置的製造方法的剖面示意圖。 2A to 2E are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 1A .

請參考圖2A，形成金屬氧化物層210”於基板100之上。在本實施例中，金屬氧化物層210”形成於介電層102上。金屬氧化物層210”的材料包括銦鋅氧化物、銦鎢氧化物、銦鎢鋅氧化物、銦鋅錫氧化物、銦鎵錫氧化物以及銦鎵鋅錫氧化物中的至少一者。 Referring to FIG. 2A , a metal oxide layer 210 ″ is formed on the substrate 100 . In this embodiment, the metal oxide layer 210 ″ is formed on the dielectric layer 102 . The material of the metal oxide layer 210″ includes at least one of indium zinc oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc tin oxide, indium gallium tin oxide, and indium gallium zinc tin oxide.

請參考圖2B，形成閘介電層110於金屬氧化物層210”上。接著形成第一閘極220於閘介電層110上，其中第一閘極220在基板100的頂面的法線方向上重疊於金屬氧化物層210”。 Referring to FIG. 2B , a gate dielectric layer 110 is formed on the metal oxide layer 210 ″. Then a first gate electrode 220 is formed on the gate dielectric layer 110 , wherein the first gate electrode 220 is at the normal line of the top surface of the substrate 100 direction overlaps the metal oxide layer 210".

請參考圖2C，對金屬氧化物層210”執行摻雜製程P，以形成經摻雜的金屬氧化物層210’，其中經摻雜的金屬氧化物層210’包含第一摻雜區214、第二摻雜區216以及通道區215。在本實施例中，以第一閘極220為罩幕，對金屬氧化物層210”執行摻 雜製程P，因此通道區215重疊於第一閘極220。在一些實施例中，摻雜製程P包括氫電漿製程、離子植入製程或其他合適的製程。 Referring to FIG. 2C, a doping process P is performed on the metal oxide layer 210" to form a doped metal oxide layer 210', wherein the doped metal oxide layer 210' includes a first doped region 214, The second doped region 216 and the channel region 215. In this embodiment, the first gate 220 is used as a mask to perform doping on the metal oxide layer 210″. Due to the miscellaneous process P, the channel region 215 overlaps the first gate 220 . In some embodiments, the doping process P includes a hydrogen plasma process, an ion implantation process, or other suitable processes.

請參考圖2D，形成層間介電層120於閘介電層110上，並於層間介電層120與閘介電層110中形成第一通孔TH1以及第二通孔TH2。第一通孔TH1以及第二通孔TH2分別重疊於經摻雜的金屬氧化物層210’的第一摻雜區214以及第二摻雜區216。 Referring to FIG. 2D , an interlayer dielectric layer 120 is formed on the gate dielectric layer 110 , and a first through hole TH1 and a second through hole TH2 are formed in the interlayer dielectric layer 120 and the gate dielectric layer 110 . The first through hole TH1 and the second through hole TH2 respectively overlap the first doped region 214 and the second doped region 216 of the doped metal oxide layer 210'.

需說明的是，雖然在本實施例中，藉由圖2C所示的摻雜製程P摻雜金屬氧化物層210”，但本發明不以此為限。在其他實施例中，層間介電層120中包含氫元素，且在形成層間介電層120之後，透過熱處理使層間介電層120中的氫元素擴散至金屬氧化物層210”以形成經摻雜的金屬氧化物層210’，接著才於層間介電層120與閘介電層110中形成第一通孔TH1以及第二通孔TH2。 It should be noted that, although in this embodiment, the metal oxide layer 210″ is doped through the doping process P shown in FIG. 2C, the present invention is not limited to this. In other embodiments, the interlayer dielectric The layer 120 contains hydrogen element, and after the interlayer dielectric layer 120 is formed, the hydrogen element in the interlayer dielectric layer 120 is diffused to the metal oxide layer 210" through heat treatment to form the doped metal oxide layer 210', Then, the first through hole TH1 and the second through hole TH2 are formed in the interlayer dielectric layer 120 and the gate dielectric layer 110 .

請參考圖2E，形成源極242以及汲極244。源極242以及汲極244分別填入第一通孔TH1以及第二通孔TH2，且源極242以及汲極244分別連接經摻雜的金屬氧化物層210’的第一摻雜區214與第二摻雜區216。 Referring to FIG. 2E , a source electrode 242 and a drain electrode 244 are formed. The source electrode 242 and the drain electrode 244 are respectively filled in the first through hole TH1 and the second through hole TH2, and the source electrode 242 and the drain electrode 244 are respectively connected to the first doped region 214 of the doped metal oxide layer 210' and The second doped region 216.

在形成源極242以及汲極244的同時或在形成源極242以及汲極244之後，對經摻雜的金屬氧化物層210’執行退火製程，以形成金屬氧化物半導體層210，如圖1A所示。具體地說，源極242以及汲極244在退火製程中會與第一摻雜區214中的氧以及第二摻雜區216中的氧進行反應，並於第一摻雜區214中以及第二摻雜區216中分別形成氧濃度較低的第一結晶區212以及第二結 晶區218。第一結晶區212與第二結晶區218的結晶度大於通道區215的結晶度。在一些實施例中，退火製程包括在250℃至500℃的溫度範圍內加熱經摻雜的金屬氧化物層210’持續0.5小時至4小時。 While forming the source electrode 242 and the drain electrode 244 or after forming the source electrode 242 and the drain electrode 244, an annealing process is performed on the doped metal oxide layer 210' to form the metal oxide semiconductor layer 210, as shown in FIG. 1A shown. Specifically, the source electrode 242 and the drain electrode 244 will react with oxygen in the first doped region 214 and the oxygen in the second doped region 216 during the annealing process, and will react with the oxygen in the first doped region 214 and the second doped region 216 . A first crystalline region 212 with a lower oxygen concentration and a second junction are respectively formed in the two doped regions 216. Crystal area 218. The crystallinity of the first crystallization region 212 and the second crystallization region 218 is greater than the crystallinity of the channel region 215 . In some embodiments, the annealing process includes heating the doped metal oxide layer 210' in a temperature range of 250°C to 500°C for 0.5 hours to 4 hours.

在退火製程時，經摻雜的金屬氧化物層210’中的氧元素與源極242以及汲極244進行反應，以形成第一氧化物層243以及第二氧化物層245，其中第一氧化物層243位於源極242與第一結晶區212之間，且第二氧化物層245位於汲極244與第二結晶區218之間。至此，半導體裝置10大致完成。 During the annealing process, the oxygen element in the doped metal oxide layer 210' reacts with the source electrode 242 and the drain electrode 244 to form the first oxide layer 243 and the second oxide layer 245, wherein the first oxide layer 243 and the second oxide layer 245 are formed. The material layer 243 is located between the source electrode 242 and the first crystallized region 212 , and the second oxide layer 245 is located between the drain electrode 244 and the second crystallized region 218 . At this point, the semiconductor device 10 is substantially completed.

圖3是依照本發明的一實施例的一種半導體裝置的剖面示意圖。在此必須說明的是，圖3的實施例沿用圖1A和圖1B的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 FIG. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 3 follows the component numbers and part of the content of the embodiment of FIG. 1A and FIG. 1B , where the same or similar numbers are used to represent the same or similar elements, and references with the same technical content are omitted. instruction. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

圖3的半導體裝置20與圖1A的半導體裝置10的主要差異在於：半導體裝置20的層間介電層120接觸金屬氧化物半導體層210的第一摻雜區214以及第二摻雜區216，且第一通孔TH1以及第二通孔TH2形成於層間介電層120中而未形成於閘介電層110中。 The main difference between the semiconductor device 20 of FIG. 3 and the semiconductor device 10 of FIG. 1A is that the interlayer dielectric layer 120 of the semiconductor device 20 contacts the first doped region 214 and the second doped region 216 of the metal oxide semiconductor layer 210, and The first through hole TH1 and the second through hole TH2 are formed in the interlayer dielectric layer 120 but not in the gate dielectric layer 110 .

圖4A至圖4D是圖3的半導體裝置的製造方法的剖面示意圖。 4A to 4D are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 3 .

請參考圖4A，接續圖2B所示的結構，以第一閘極220 為罩幕圖案化閘介電層110，以暴露出金屬氧化物層210”。 Please refer to FIG. 4A, continuing the structure shown in FIG. 2B, with the first gate 220 Gate dielectric layer 110 is patterned for masking to expose metal oxide layer 210".

請參考圖4B，對金屬氧化物層210”執行摻雜製程P，以形成經摻雜的金屬氧化物層210’，其中經摻雜的金屬氧化物層210’包含第一摻雜區214、第二摻雜區216以及通道區215。在本實施例中，以第一閘極220為罩幕，對金屬氧化物層210”執行摻雜製程P，因此通道區215重疊於第一閘極220。在一些實施例中，摻雜製程P包括氫電漿製程、離子植入製程或其他合適的製程。 Referring to FIG. 4B, a doping process P is performed on the metal oxide layer 210" to form a doped metal oxide layer 210', wherein the doped metal oxide layer 210' includes a first doped region 214, The second doping region 216 and the channel region 215. In this embodiment, the first gate 220 is used as a mask to perform the doping process P on the metal oxide layer 210″, so the channel region 215 overlaps the first gate. 220. In some embodiments, the doping process P includes a hydrogen plasma process, an ion implantation process, or other suitable processes.

請參考圖4C，形成層間介電層120於金屬氧化物層210’上，並於層間介電層120中形成第一通孔TH1以及第二通孔TH2。第一通孔TH1以及第二通孔TH2分別重疊於經摻雜的金屬氧化物層210’的第一摻雜區214以及第二摻雜區216。 Referring to FIG. 4C, an interlayer dielectric layer 120 is formed on the metal oxide layer 210', and a first through hole TH1 and a second through hole TH2 are formed in the interlayer dielectric layer 120. The first through hole TH1 and the second through hole TH2 respectively overlap the first doped region 214 and the second doped region 216 of the doped metal oxide layer 210'.

需說明的是，雖然在本實施例中，藉由圖4B所示的摻雜製程P摻雜金屬氧化物層210”，但本發明不以此為限。在其他實施例中，層間介電層120中包含氫元素，且在形成層間介電層120之後，藉由熱處理使層間介電層120中的氫元素擴散至金屬氧化物層210”以形成經摻雜的金屬氧化物層210’，接著才於層間介電層120中形成第一通孔TH1以及第二通孔TH2。 It should be noted that, although in this embodiment, the metal oxide layer 210″ is doped through the doping process P shown in FIG. 4B, the present invention is not limited to this. In other embodiments, the interlayer dielectric The layer 120 contains hydrogen element, and after the interlayer dielectric layer 120 is formed, the hydrogen element in the interlayer dielectric layer 120 is diffused to the metal oxide layer 210" through heat treatment to form the doped metal oxide layer 210' , and then the first through hole TH1 and the second through hole TH2 are formed in the interlayer dielectric layer 120 .

請參考圖4D，形成源極242以及汲極244。源極242以及汲極244分別填入第一通孔TH1以及第二通孔該TH2，且源極242以及汲極244分別連接經摻雜的金屬氧化物層210’。 Referring to FIG. 4D , source 242 and drain 244 are formed. The source electrode 242 and the drain electrode 244 are respectively filled in the first through hole TH1 and the second through hole TH2, and the source electrode 242 and the drain electrode 244 are respectively connected to the doped metal oxide layer 210'.

在形成源極242以及汲極244的同時或在形成源極242以及汲極244之後，對經摻雜的金屬氧化物層210’執行退火製程， 以形成金屬氧化物半導體層210，如圖3所示。具體地說，源極242以及汲極244在退火製程中會與第一摻雜區214中的氧以及第二摻雜區216中的氧進行反應，並於第一摻雜區214中以及第二摻雜區216中分別形成氧濃度較低的第一結晶區212以及第二結晶區218。第一結晶區212與第二結晶區218的結晶度大於通道區215的結晶度。在一些實施例中，退火製程包括在250℃至500℃的溫度範圍內加熱經摻雜的金屬氧化物層210’持續0.5小時至4小時。 While forming the source electrode 242 and the drain electrode 244 or after forming the source electrode 242 and the drain electrode 244, an annealing process is performed on the doped metal oxide layer 210', To form a metal oxide semiconductor layer 210, as shown in FIG. 3 . Specifically, the source electrode 242 and the drain electrode 244 will react with oxygen in the first doped region 214 and the oxygen in the second doped region 216 during the annealing process, and will react with the oxygen in the first doped region 214 and the second doped region 216 . A first crystallized region 212 and a second crystallized region 218 with a lower oxygen concentration are respectively formed in the two doped regions 216 . The crystallinity of the first crystallization region 212 and the second crystallization region 218 is greater than the crystallinity of the channel region 215 . In some embodiments, the annealing process includes heating the doped metal oxide layer 210' in a temperature range of 250°C to 500°C for 0.5 hours to 4 hours.

在退火製程時，經摻雜的金屬氧化物層210’中的氧元素與源極242以及汲極244進行反應，以形成第一氧化物層243以及第二氧化物層245，其中第一氧化物層243位於源極242與第一結晶區212之間，且第二氧化物層245位於汲極244與第二結晶區218之間。至此，半導體裝置20大致完成。 During the annealing process, the oxygen element in the doped metal oxide layer 210' reacts with the source electrode 242 and the drain electrode 244 to form the first oxide layer 243 and the second oxide layer 245, wherein the first oxide layer 243 and the second oxide layer 245 are formed. The material layer 243 is located between the source electrode 242 and the first crystallized region 212 , and the second oxide layer 245 is located between the drain electrode 244 and the second crystallized region 218 . At this point, the semiconductor device 20 is substantially completed.

圖5是依照本發明的一實施例的一種半導體裝置的剖面示意圖。在此必須說明的是，圖5的實施例沿用圖1A和圖1B的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 FIG. 5 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 5 follows the component numbers and part of the content of the embodiment of FIG. 1A and FIG. 1B , where the same or similar numbers are used to represent the same or similar elements, and references with the same technical content are omitted. instruction. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

圖5的半導體裝置30與圖1A的半導體裝置10的主要差異在於：半導體裝置10為頂部閘極型薄膜電晶體，而半導體裝置30為底部閘極型薄膜電晶體。 The main difference between the semiconductor device 30 of FIG. 5 and the semiconductor device 10 of FIG. 1A is that the semiconductor device 10 is a top gate thin film transistor, while the semiconductor device 30 is a bottom gate thin film transistor.

請參考圖5，半導體裝置30的第一閘極220位於金屬氧 化物半導體層210與基板100之間。 Referring to FIG. 5 , the first gate 220 of the semiconductor device 30 is located on the metal oxide between the compound semiconductor layer 210 and the substrate 100 .

請參考圖5，第一閘極220形成於基板100之上。閘介電層110形成於第一閘極220上。金屬氧化物半導體層210形成於閘介電層110上。介電層110a形成於金屬氧化物半導體層210上。 Referring to FIG. 5 , the first gate 220 is formed on the substrate 100 . The gate dielectric layer 110 is formed on the first gate 220 . The metal oxide semiconductor layer 210 is formed on the gate dielectric layer 110 . The dielectric layer 110a is formed on the metal oxide semiconductor layer 210.

圖6是依照本發明的一實施例的一種半導體裝置的剖面示意圖。在此必須說明的是，圖6的實施例沿用圖1A和圖1B的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 FIG. 6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 6 follows the component numbers and part of the content of the embodiment of FIG. 1A and FIG. 1B , where the same or similar numbers are used to represent the same or similar elements, and references with the same technical content are omitted. instruction. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

圖6的半導體裝置40與圖1A的半導體裝置10的主要差異在於：半導體裝置10為頂部閘極型薄膜電晶體，而半導體裝置40為雙閘極型薄膜電晶體。 The main difference between the semiconductor device 40 of FIG. 6 and the semiconductor device 10 of FIG. 1A is that the semiconductor device 10 is a top gate thin film transistor, while the semiconductor device 40 is a double gate thin film transistor.

請參考圖6，半導體裝置40包括第一閘極220A以及第二閘極220B，金屬氧化物半導體層210位於第一閘極220A與第二閘極220B之間。介電層110a位於金屬氧化物半導體層210與第一閘極220A之間。閘介電層110位於金屬氧化物半導體層210與第二閘極220B之間。 Referring to FIG. 6 , the semiconductor device 40 includes a first gate 220A and a second gate 220B, and the metal oxide semiconductor layer 210 is located between the first gate 220A and the second gate 220B. The dielectric layer 110a is located between the metal oxide semiconductor layer 210 and the first gate 220A. The gate dielectric layer 110 is located between the metal oxide semiconductor layer 210 and the second gate electrode 220B.

圖7A是依照本發明的一實施例的一種半導體裝置的剖面示意圖。圖7B是圖7A的半導體裝置的局部上視示意圖。圖7B會示了介電層102、金屬氧化物半導體層210以及第一閘極220，並省略繪示其他構件。在此必須說明的是，圖7A與圖7B的實施例沿用圖1A和圖1B的實施例的元件標號與部分內容，其中採用 相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 FIG. 7A is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 7B is a partial top view of the semiconductor device of FIG. 7A. FIG. 7B shows the dielectric layer 102, the metal oxide semiconductor layer 210 and the first gate 220, and other components are omitted. It must be noted here that the embodiment of FIGS. 7A and 7B follows the component numbers and part of the content of the embodiment of FIGS. 1A and 1B , where the The same or similar reference numerals are used to represent the same or similar elements, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

圖7A的半導體裝置50與圖1A的半導體裝置10的主要差異在於：半導體裝置50的源極242與汲極244重疊於金屬氧化物半導體層210的部分側壁。 The main difference between the semiconductor device 50 of FIG. 7A and the semiconductor device 10 of FIG. 1A is that the source electrode 242 and the drain electrode 244 of the semiconductor device 50 overlap part of the sidewall of the metal oxide semiconductor layer 210 .

請參考圖7A與圖7B，層間介電層120以及閘介電層110的第一通孔TH1與第二通孔TH2在基板100的頂面的法線方向上重疊於金屬氧化物半導體層210的部分側壁。在本實施例中，第一結晶區212位於金屬氧化物半導體層210的部分側壁，且第二結晶區218位於金屬氧化物半導體層210的部分側壁。第一氧化物層243與第二氧化物層245覆蓋金屬氧化物半導體層210的部分側壁。 Please refer to FIGS. 7A and 7B , the first through hole TH1 and the second through hole TH2 of the interlayer dielectric layer 120 and the gate dielectric layer 110 overlap the metal oxide semiconductor layer 210 in the normal direction of the top surface of the substrate 100 part of the side wall. In this embodiment, the first crystallization region 212 is located on part of the sidewall of the metal oxide semiconductor layer 210 , and the second crystallization region 218 is located on part of the sidewall of the metal oxide semiconductor layer 210 . The first oxide layer 243 and the second oxide layer 245 cover part of the sidewalls of the metal oxide semiconductor layer 210 .

圖8是依照本發明的一實施例的一種半導體裝置的剖面示意圖。在此必須說明的是，圖8的實施例沿用圖5的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 FIG. 8 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 8 follows the component numbers and part of the content of the embodiment of FIG. 5 , where the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

圖8的半導體裝置60與圖5的半導體裝置30的主要差異在於：半導體裝置60的源極242與汲極244是採用背通道蝕刻(back channel etch，BCE)製程形成的。 The main difference between the semiconductor device 60 of FIG. 8 and the semiconductor device 30 of FIG. 5 is that the source electrode 242 and the drain electrode 244 of the semiconductor device 60 are formed using a back channel etch (BCE) process.

請參考圖8，源極242與汲極244的製造方法例如包括： 沉積金屬材料於金屬氧化物半導體層210上，接著蝕刻金屬材料以形成彼此分離的源極242與汲極244。最後，於源極242與汲極244上形成介電層120a。 Referring to FIG. 8 , the manufacturing method of the source 242 and the drain 244 includes, for example: Metal material is deposited on the metal oxide semiconductor layer 210, and then the metal material is etched to form the source electrode 242 and the drain electrode 244 that are separated from each other. Finally, a dielectric layer 120a is formed on the source electrode 242 and the drain electrode 244.

圖9是依照本發明的一實施例的一種半導體裝置的剖面示意圖。在此必須說明的是，圖9的實施例沿用圖8的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 FIG. 9 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 9 follows the component numbers and part of the content of the embodiment of FIG. 8 , where the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

圖9的半導體裝置70與圖8的半導體裝置60的主要差異在於：半導體裝置70更包括第一蝕刻停止層ESL1。 The main difference between the semiconductor device 70 of FIG. 9 and the semiconductor device 60 of FIG. 8 is that the semiconductor device 70 further includes a first etching stop layer ESL1.

請參考圖9，在形成源極242與汲極244之前，形成第一蝕刻停止層ESL1於金屬氧化物半導體層210的通道區215上，藉此避免形成源極242與汲極244時所使用的蝕刻製程對通道區215造成損傷。在一些實施例中，源極242與汲極244覆蓋部分第一蝕刻停止層ESL1。在一些實施例中，第一蝕刻停止層ESL1還覆蓋部分第一摻雜區214以及第二摻雜區216。在一些實施例中，第一結晶區212以及第二結晶區218延伸至第一蝕刻停止層ESL1下方。 Please refer to FIG. 9 . Before forming the source electrode 242 and the drain electrode 244 , a first etching stop layer ESL1 is formed on the channel region 215 of the metal oxide semiconductor layer 210 , thereby avoiding the need for use in forming the source electrode 242 and the drain electrode 244 . The etching process causes damage to the channel area 215. In some embodiments, the source electrode 242 and the drain electrode 244 cover part of the first etch stop layer ESL1. In some embodiments, the first etch stop layer ESL1 also covers part of the first doped region 214 and the second doped region 216 . In some embodiments, the first crystallization region 212 and the second crystallization region 218 extend below the first etch stop layer ESL1.

圖10是依照本發明的一實施例的一種半導體裝置的剖面示意圖。在此必須說明的是，圖10的實施例沿用圖9的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的 說明可參考前述實施例，在此不贅述。 FIG. 10 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 10 follows the component numbers and part of the content of the embodiment of FIG. 9 , where the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. About omitting parts For description, reference may be made to the foregoing embodiments, and details are not repeated here.

圖10的半導體裝置80與圖9的半導體裝置70的主要差異在於：半導體裝置80更包括第二蝕刻停止層ESL2。 The main difference between the semiconductor device 80 of FIG. 10 and the semiconductor device 70 of FIG. 9 is that the semiconductor device 80 further includes a second etching stop layer ESL2.

請參考圖10，在形成源極242與汲極244之前，形成第一蝕刻停止層ESL1以及第二蝕刻停止層ESL2於金屬氧化物半導體層210的通道區215上，藉此避免形成源極242與汲極244時所使用的蝕刻製程對通道區215造成損傷。在一些實施例中，第一蝕刻停止層ESL1以及第二蝕刻停止層ESL2還覆蓋部分第一摻雜區214以及第二摻雜區216。在一些實施例中，第一結晶區212以及第二結晶區218延伸至第一蝕刻停止層ESL1以及第二蝕刻停止層ESL2下方。 Referring to FIG. 10 , before forming the source electrode 242 and the drain electrode 244 , a first etching stop layer ESL1 and a second etching stop layer ESL2 are formed on the channel region 215 of the metal oxide semiconductor layer 210 , thereby avoiding the formation of the source electrode 242 The etching process used when connecting the drain electrode 244 causes damage to the channel region 215 . In some embodiments, the first etching stop layer ESL1 and the second etching stop layer ESL2 also cover parts of the first doped region 214 and the second doped region 216 . In some embodiments, the first crystallization region 212 and the second crystallization region 218 extend below the first etching stop layer ESL1 and the second etching stop layer ESL2.

圖11A是依照本發明的一實施例的一種半導體裝置的高解析率穿透式電子顯微鏡照片。圖11B是圖11A的區域R的奈米束電子繞射照片。圖12A是依照本發明的一實施例的一種半導體裝置的高解析率穿透式電子顯微鏡照片。圖12B是圖12A的區域R的奈米束電子繞射照片。 FIG. 11A is a high-resolution transmission electron microscope photograph of a semiconductor device according to an embodiment of the present invention. FIG. 11B is a nanobeam electron diffraction photograph of the region R in FIG. 11A . FIG. 12A is a high-resolution transmission electron microscope photograph of a semiconductor device according to an embodiment of the present invention. FIG. 12B is a nanobeam electron diffraction photograph of the region R in FIG. 12A .

舉例來說，圖11A與圖11B對應了圖1A之半導體裝置10在通道區215周圍的位置，且圖12A與圖12B對應了圖1A之半導體裝置10在第一氧化物層243或第二氧化物層245周圍的位置。 For example, FIGS. 11A and 11B correspond to the position of the semiconductor device 10 of FIG. 1A around the channel region 215 , and FIGS. 12A and 12B correspond to the position of the semiconductor device 10 of FIG. 1A in the first oxide layer 243 or the second oxide layer 215 . The location around the object layer 245.

由圖11B可以得知，金屬氧化物半導體層210的通道區215為非晶質。由圖12B可以得知，金屬氧化物半導體層210的 第一結晶區212與第二結晶區218為結晶質。換句話說，第一結晶區212與第二結晶區218中的至少部分晶格沿著相同的方向排列。 It can be known from FIG. 11B that the channel region 215 of the metal oxide semiconductor layer 210 is amorphous. It can be seen from FIG. 12B that the metal oxide semiconductor layer 210 The first crystallization region 212 and the second crystallization region 218 are crystalline. In other words, at least part of the crystal lattices in the first crystallization region 212 and the second crystallization region 218 are aligned in the same direction.

綜上所述，本發明藉由第一結晶區與第二結晶區的存在，源極與金屬氧化物半導體層之間的接觸以及汲極與金屬氧化物半導體層之間的接觸可以改善，藉此提升通過半導體裝置的電流量。 In summary, the present invention can improve the contact between the source electrode and the metal oxide semiconductor layer and the contact between the drain electrode and the metal oxide semiconductor layer through the existence of the first crystallization region and the second crystallization region. This increases the amount of current flowing through the semiconductor device.

10:半導體裝置 10:Semiconductor device

100:基板 100:Substrate

102:介電層 102:Dielectric layer

110:閘介電層 110: Gate dielectric layer

120:層間介電層 120: Interlayer dielectric layer

210:金屬氧化物半導體層 210: Metal oxide semiconductor layer

212:第一結晶區 212: First crystallization zone

214:第一摻雜區 214: First doped region

215:通道區 215: Passage area

216:第二摻雜區 216: Second doping region

218:第二結晶區 218: Second crystallization zone

220:第一閘極 220: first gate

242:源極 242:Source

243:第一氧化物層 243: First oxide layer

244:汲極 244:Jiji

245:第二氧化物層 245: Second oxide layer

TH1:第一通孔 TH1: first through hole

TH2:第二通孔 TH2: Second through hole

Claims (15)

一種半導體裝置，包括：一基板；一金屬氧化物半導體層，位於該基板之上，且該金屬氧化物半導體層的材料包括銦鋅氧化物、銦鎢氧化物、銦鎢鋅氧化物、銦鋅錫氧化物、銦鎵錫氧化物以及銦鎵鋅錫氧化物中的至少一者，且該金屬氧化物半導體層包括一第一摻雜區、一第二摻雜區、位於該第一摻雜區與該第二摻雜區之間的一通道區、位於第一摻雜區中的一第一結晶區以及位於該第二摻雜區中的一第二結晶區，且該第一結晶區與該第二結晶區的結晶度大於該通道區的結晶度，其中該通道區的載子遷移率為30cm2/Vs至100cm2/Vs，且該通道區的銦濃度為25mol%至40mol%，其中該第一結晶區與該第二結晶區的銦濃度大於該通道區的銦濃度；一第一閘極，重疊於該金屬氧化物半導體層的該通道區；以及一源極以及一汲極，分別電性連接該第一結晶區與該第二結晶區。 A semiconductor device includes: a substrate; a metal oxide semiconductor layer located on the substrate, and the material of the metal oxide semiconductor layer includes indium zinc oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc At least one of tin oxide, indium gallium tin oxide and indium gallium zinc tin oxide, and the metal oxide semiconductor layer includes a first doped region, a second doped region, located on the first doped region. a channel region between the region and the second doped region, a first crystallized region located in the first doped region, and a second crystallized region located in the second doped region, and the first crystallized region The crystallinity of the second crystalline region is greater than the crystallinity of the channel region, wherein the carrier mobility of the channel region is 30cm 2 /Vs to 100cm 2 /Vs, and the indium concentration of the channel region is 25mol% to 40mol% , wherein the indium concentration of the first crystallization region and the second crystallization region is greater than the indium concentration of the channel region; a first gate overlaps the channel region of the metal oxide semiconductor layer; and a source electrode and a drain electrode The poles are electrically connected to the first crystallization region and the second crystallization region respectively. 如請求項1所述的半導體裝置，其中該第一結晶區與該第二結晶區中的至少部分晶格沿著相同的方向排列。 The semiconductor device of claim 1, wherein at least part of the crystal lattices in the first crystallization region and the second crystallization region are arranged along the same direction. 如請求項1所述的半導體裝置，其中該第一閘極位於該金屬氧化物半導體層與該基板之間，或該金屬氧化物半導體層位於該第一閘極與該基板之間。 The semiconductor device of claim 1, wherein the first gate is located between the metal oxide semiconductor layer and the substrate, or the metal oxide semiconductor layer is located between the first gate and the substrate. 如請求項1所述的半導體裝置，更包括：一第二閘極，其中該金屬氧化物半導體層位於該第一閘極與該第二閘極之間。 The semiconductor device of claim 1, further comprising: a second gate, wherein the metal oxide semiconductor layer is located between the first gate and the second gate. 如請求項1所述的半導體裝置，其中該通道區為非晶質。 The semiconductor device according to claim 1, wherein the channel region is amorphous. 如請求項1所述的半導體裝置，其中該金屬氧化物半導體層的厚度為100埃至500埃。 The semiconductor device according to claim 1, wherein the metal oxide semiconductor layer has a thickness of 100 angstroms to 500 angstroms. 如請求項1所述的半導體裝置，其中該源極以及該汲極的材料包括鈦元素。 The semiconductor device of claim 1, wherein the source electrode and the drain electrode include titanium. 如請求項1所述的半導體裝置，更包括：一第一氧化物層，位於該源極與該第一結晶區之間；以及一第二氧化物層，位於該汲極與該第二結晶區之間。 The semiconductor device of claim 1, further comprising: a first oxide layer located between the source electrode and the first crystalline region; and a second oxide layer located between the drain electrode and the second crystalline region. between districts. 如請求項8所述的半導體裝置，其中該第一氧化物層與該第二氧化物層覆蓋該金屬氧化物半導體層的部分側壁。 The semiconductor device of claim 8, wherein the first oxide layer and the second oxide layer cover part of the sidewalls of the metal oxide semiconductor layer. 如請求項1所述的半導體裝置，更包括：一介電層，位於該金屬氧化物半導體層上，且具有重疊於該第一結晶區的一第一通孔以及重疊於該第二結晶區的一第二通孔，其中該源極與該汲極分別填入該第一通孔以及該第二通孔，且其中該第一通孔的底部於該基板上的垂直投影面積小於該第一結晶區於該基板上的垂直投影面積，且該第二通孔的底部於該基板上的垂直投影面積小於該第二結晶區於該基板上的垂直投影面積。 The semiconductor device of claim 1, further comprising: a dielectric layer located on the metal oxide semiconductor layer and having a first through hole overlapping the first crystallization region and overlapping the second crystallization region. a second through hole, wherein the source electrode and the drain electrode are respectively filled in the first through hole and the second through hole, and wherein the vertical projected area of the bottom of the first through hole on the substrate is smaller than the third through hole. The vertical projected area of a crystallized region on the substrate, and the vertical projected area of the bottom of the second through hole on the substrate is smaller than the vertical projected area of the second crystallized region on the substrate. 如請求項1所述的半導體裝置，其中該第一結晶區與該第二結晶區分離於該金屬氧化物半導體層的側壁。 The semiconductor device of claim 1, wherein the first crystalline region and the second crystalline region are separated from sidewalls of the metal oxide semiconductor layer. 如請求項1所述的半導體裝置，其中該第一摻雜區、該第二摻雜區、該第一結晶區以及該第二結晶區的氫濃度大於該通道區的氫濃度。 The semiconductor device of claim 1, wherein the hydrogen concentration of the first doped region, the second doped region, the first crystallized region and the second crystallized region is greater than the hydrogen concentration of the channel region. 一種半導體裝置的製造方法，包括：形成一金屬氧化物層於一基板之上，且該金屬氧化物層的材料包括銦鋅氧化物、銦鎢氧化物、銦鎢鋅氧化物、銦鋅錫氧化物、銦鎵錫氧化物以及銦鎵鋅錫氧化物中的至少一者；形成一第一閘極，該第一閘極重疊於該金屬氧化物層；對該金屬氧化物層執行一摻雜製程，以形成經摻雜的金屬氧化物層；形成一源極以及一汲極，該源極以及該汲極分別連接該經摻雜的金屬氧化物層；以及對該經摻雜的金屬氧化物層執行一退火製程，以形成金屬氧化物半導體層，其中該金屬氧化物半導體層包括一第一摻雜區、一第二摻雜區、位於該第一摻雜區與該第二摻雜區之間的一通道區、位於第一摻雜區中的一第一結晶區以及位於該第二摻雜區中的一第二結晶區，且該第一結晶區與該第二結晶區的結晶度大於該通道區的結晶度，其中該通道區的載子遷移率為30cm2/Vs至100cm2/Vs，且該通道區的銦濃度為25mol%至40mol%，其中該第一結晶區與該第二結晶區的銦濃度大於該通道區的銦濃度。 A method of manufacturing a semiconductor device, including: forming a metal oxide layer on a substrate, and the material of the metal oxide layer includes indium zinc oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc tin oxide At least one of indium gallium tin oxide and indium gallium zinc tin oxide; forming a first gate that overlaps the metal oxide layer; performing a doping on the metal oxide layer A process to form a doped metal oxide layer; form a source electrode and a drain electrode, the source electrode and the drain electrode are respectively connected to the doped metal oxide layer; and oxidize the doped metal The material layer performs an annealing process to form a metal oxide semiconductor layer, wherein the metal oxide semiconductor layer includes a first doped region, a second doped region, located between the first doped region and the second doped region. a channel region between the regions, a first crystallization region located in the first doping region and a second crystallization region located in the second doping region, and the first crystallization region and the second crystallization region The crystallinity is greater than the crystallinity of the channel region, wherein the carrier mobility of the channel region is 30cm 2 /Vs to 100cm 2 /Vs, and the indium concentration of the channel region is 25mol% to 40mol%, wherein the first crystallization region The indium concentration in the second crystallization region is greater than the indium concentration in the channel region. 如請求項13所述的半導體裝置的製造方法，其中該退火製程包括在250℃至500℃的溫度範圍內加熱該經摻雜的金屬氧化物層持續0.5小時至4小時。 The method of manufacturing a semiconductor device as claimed in claim 13, wherein the annealing process includes heating the doped metal oxide layer in a temperature range of 250°C to 500°C for 0.5 hours to 4 hours. 如請求項13所述的半導體裝置的製造方法，其中在該退火製程時，該經摻雜的金屬氧化物層中的氧元素與該源極以及該汲極進行反應，以形成一第一氧化物層以及一第二氧化物層，其中該第一氧化物層位於該源極與該第一結晶區之間，且該第二氧化物層位於該汲極與該第二結晶區之間。 The method of manufacturing a semiconductor device according to claim 13, wherein during the annealing process, the oxygen element in the doped metal oxide layer reacts with the source electrode and the drain electrode to form a first oxide material layer and a second oxide layer, wherein the first oxide layer is located between the source electrode and the first crystallization region, and the second oxide layer is located between the drain electrode and the second crystallization region.
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