TWI819313B - Circuit board and method for manufacturing the same - Google Patents
Circuit board and method for manufacturing the same Download PDFInfo
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- TWI819313B TWI819313B TW110119908A TW110119908A TWI819313B TW I819313 B TWI819313 B TW I819313B TW 110119908 A TW110119908 A TW 110119908A TW 110119908 A TW110119908 A TW 110119908A TW I819313 B TWI819313 B TW I819313B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title claims abstract description 7
- 239000004020 conductor Substances 0.000 claims abstract description 171
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 230000000149 penetrating effect Effects 0.000 claims abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 40
- 239000011810 insulating material Substances 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 30
- 239000011889 copper foil Substances 0.000 claims description 27
- 229910052802 copper Inorganic materials 0.000 claims description 13
- 239000010949 copper Substances 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 238000009413 insulation Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 248
- 230000005540 biological transmission Effects 0.000 description 6
- 238000003698 laser cutting Methods 0.000 description 5
- 239000004696 Poly ether ether ketone Substances 0.000 description 4
- 239000004721 Polyphenylene oxide Substances 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 229920002530 polyetherether ketone Polymers 0.000 description 4
- -1 polyethylene terephthalate Polymers 0.000 description 4
- 229920006380 polyphenylene oxide Polymers 0.000 description 4
- 229920000106 Liquid crystal polymer Polymers 0.000 description 3
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 3
- 229920000139 polyethylene terephthalate Polymers 0.000 description 3
- 239000005020 polyethylene terephthalate Substances 0.000 description 3
- 239000004810 polytetrafluoroethylene Substances 0.000 description 3
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 3
- 239000004698 Polyethylene Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- JUPQTSLXMOCDHR-UHFFFAOYSA-N benzene-1,4-diol;bis(4-fluorophenyl)methanone Chemical compound OC1=CC=C(O)C=C1.C1=CC(F)=CC=C1C(=O)C1=CC=C(F)C=C1 JUPQTSLXMOCDHR-UHFFFAOYSA-N 0.000 description 2
- 239000013039 cover film Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229920000573 polyethylene Polymers 0.000 description 2
- 239000011112 polyethylene naphthalate Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Diaphragms For Electromechanical Transducers (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
本申請涉及電路電子技術領域,尤其涉及一種電路板及其製作方法。The present application relates to the field of circuit electronics technology, and in particular to a circuit board and a manufacturing method thereof.
為滿足電子產品高集成度、小型化的發展需要,電路板也朝著輕薄化和小型化的趨勢發展。現有一種解決方案是設計多層電路板。然而,隨著導體層的增加,電路板的厚度增加。In order to meet the development needs of high integration and miniaturization of electronic products, circuit boards are also developing towards the trend of thinning, lightness and miniaturization. One existing solution is to design multi-layer circuit boards. However, as the conductor layers are added, the thickness of the circuit board increases.
有鑑於此,有必要提供一種能夠解決上述技術問題的電路板及其製作方法。In view of this, it is necessary to provide a circuit board and a manufacturing method thereof that can solve the above technical problems.
本申請提供一種電路板,包括電路基板。所述電路基板包括基材層、第一導電線路層、第二導電線路層、第一導體層、第一絕緣層和第二導體層。所述第一導電線路層和所述第二導電線路層設置於所述基材層相對的兩表面,所述電路基板設有貫通所述基材層和所述第一導電線路層的第一凹槽,所述第二導電線路層從所述第一凹槽露出,所述第一導體層設置於所述第一凹槽中並與所述第一導電線路層和所述第二導電線路層相連接,所述第一導體層開設有第二凹槽,所述第一絕緣層設置於所述第二凹槽中並開設有第三凹槽,所述第二導體層設置於所述第三凹槽中。This application provides a circuit board, including a circuit substrate. The circuit substrate includes a base material layer, a first conductive circuit layer, a second conductive circuit layer, a first conductor layer, a first insulating layer and a second conductor layer. The first conductive circuit layer and the second conductive circuit layer are provided on two opposite surfaces of the base material layer, and the circuit substrate is provided with a first conductive circuit layer penetrating the base material layer and the first conductive circuit layer. Groove, the second conductive circuit layer is exposed from the first groove, the first conductor layer is disposed in the first groove and connected with the first conductive circuit layer and the second conductive circuit The layers are connected, the first conductor layer is provided with a second groove, the first insulating layer is provided in the second groove and has a third groove, the second conductor layer is provided in the in the third groove.
本申請還提供一種電路板的製作方法,包括以下步驟: 提供雙面覆銅板,所述雙面覆銅板包括基材層和設置於所述基材層相對的兩表面上的第一銅箔層和第二銅箔層; 在所述雙面覆蓋板上形成第一凹槽。所述第一凹槽貫通所述基材層和所述第一銅箔層,且部分所述第二銅箔層從所述第一凹槽中露出; 在所述第一凹槽中填充第一導電材料,並去除部分第一導電材料形成第二凹槽,以得到第一導體層; 在所述第二凹槽中填充第一絕緣材料,並去除部分第一絕緣材料形成第三凹槽,得到第一絕緣層; 在所述第三凹槽中填充第二導電材料,並去除部分第二導電材料形成第四凹槽,得到第二導體層; 在所述第四凹槽中填充第二絕緣材料,並去除部分第二絕緣材料形成第五凹槽,得到第二絕緣層; 在所述第五凹槽中填充第三導電材料,得到第三導體層; 在所述第一銅箔層和第二銅箔層上進行線路製作,形成第一導電線路層和第二導電線路層,得到電路基板。 This application also provides a method for manufacturing a circuit board, which includes the following steps: A double-sided copper clad laminate is provided, the double-sided copper clad laminate comprising a base material layer and a first copper foil layer and a second copper foil layer disposed on two opposite surfaces of the base material layer; A first groove is formed on the double-sided cover plate. The first groove penetrates the base material layer and the first copper foil layer, and part of the second copper foil layer is exposed from the first groove; Fill the first groove with a first conductive material, and remove part of the first conductive material to form a second groove to obtain a first conductor layer; Fill the second groove with a first insulating material, and remove part of the first insulating material to form a third groove to obtain a first insulating layer; Fill the third groove with a second conductive material, and remove part of the second conductive material to form a fourth groove to obtain a second conductor layer; Fill the fourth groove with a second insulating material, and remove part of the second insulating material to form a fifth groove to obtain a second insulating layer; Fill the fifth groove with a third conductive material to obtain a third conductor layer; Conduct circuit fabrication on the first copper foil layer and the second copper foil layer to form a first conductive circuit layer and a second conductive circuit layer to obtain a circuit substrate.
本申請電路板及其製作方法,通過在雙面電路基板上開設第一凹槽,並在第一凹槽中設置多個導體層,使得該雙面電路基板具有多層電路基板的功效,降低了電路基板的厚度,有利於薄型化。The circuit board and its manufacturing method of the present application, by opening a first groove on the double-sided circuit substrate and arranging a plurality of conductor layers in the first groove, make the double-sided circuit substrate have the effect of a multi-layer circuit substrate and reduce the cost of the circuit board. The thickness of the circuit board is conducive to thinning.
下面將對本發明實施方式中的技術方案進行清楚、完整地描述,顯然,所描述的實施方式僅僅是本發明一部分實施方式,而不是全部的實施方式。基於本發明中的實施方式,本領域普通技術人員在沒有付出創造性勞動前提下所獲得的所有其他實施方式,都屬於本發明保護的範圍。The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.
需要說明的是,除非另有定義,本文所使用的所有的技術和科學術語與屬於本發明的技術領域的技術人員通常理解的含義相同。在本發明實施方式中使用的術語是僅僅出於描述特定實施方式的目的,而非旨在限制本發明。It should be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the technical field belonging to the present invention. The terminology used in the embodiments of the present invention is for the purpose of describing particular embodiments only and is not intended to limit the present invention.
本申請一實施方式提供一種電路板的製作方法,其包括以下步驟。An embodiment of the present application provides a method for manufacturing a circuit board, which includes the following steps.
步驟S1,請參閱圖1,提供雙面覆銅板10。所述雙面覆銅板10包括基材層11和設置於所述基材層11相對的兩表面上的第一銅箔層13和第二銅箔層14。In step S1, please refer to Figure 1 to provide a double-sided
在一些實施方式中,所述基材層11的材質選自聚醯亞胺(polyimide,PI)、聚對苯二甲酸乙二醇酯(polyethylene terephthalate,PET)、聚萘二甲酸乙二醇酯(polyethylene naphthalate,PEN)、聚乙烯(polyethylene,PE)中至少一種。In some embodiments, the material of the
步驟S2,請參閱圖2,在所述雙面覆銅板10上形成第一凹槽101。所述第一凹槽101貫通所述基材層11和所述第一銅箔層13,且部分所述第二銅箔層14從所述第一凹槽101中露出。本實施方式中,通過鐳射切割方式去除部分第一銅箔層13和部分基材層11,以形成所述第一凹槽101。在其他實施方式中,還可通過其他方式去除部分第一銅箔層13和部分基材層11。In step S2, please refer to FIG. 2 to form a
在一些實施方式中,所述第一凹槽101的截面形狀為U形。In some embodiments, the cross-sectional shape of the
步驟S3,請參閱圖3,在所述第一凹槽101中填充第一導電材料20。所述第一導電材料20完全填滿所述第一凹槽101。本實施方式中,通過印刷方式將第一導電材料20填充於第一凹槽101中。在其他實施方式中,還可以通過其他方式將第一導電材料20填充於所述第一凹槽101中。Step S3, please refer to FIG. 3 , filling the
步驟S4,請參閱圖4,去除部分第一導電材料20形成第二凹槽21,以得到第一導體層22。去除了部分的第一導電材料20作為所述第一導體層22,被去除的部分第一導電材料20所在空間作為所述第二凹槽21。本實施方式中,通過鐳射切割方式去除部分第一導電材料20。在其他實施方式中,還可以採用其他方式去除部分第一導電材料20。In step S4, please refer to FIG. 4, part of the first
在一些實施方式中,所述第二凹槽21的截面形狀為U形,即,所述第一導體層22的截面形狀為U形。In some embodiments, the cross-sectional shape of the
步驟S5,請參閱圖5,在所述第二凹槽21中填充第一絕緣材料30。所述第一絕緣材料30填滿所述第二凹槽21。本實施方式中,通過印刷方式將所述第一絕緣材料30填充於所述第二凹槽21中。Step S5 , please refer to FIG. 5 , filling the first
步驟S6,請參閱圖6,去除部分第一絕緣材料30形成第三凹槽31,得到第一絕緣層32。去除了部分的的第一絕緣材料30作為所述第一絕緣層32,被去除的部分第一絕緣材料30所在空間作為所述第三凹槽31。本實施方式中,通過鐳射切割方式去除部分第一絕緣材料30。In step S6 , please refer to FIG. 6 , part of the first
在一些實施方式中,所述第三凹槽31的截面形狀為U形,即所述第一絕緣層32的截面形狀為U形。In some embodiments, the cross-sectional shape of the
步驟S7,請參閱圖7,在所述第三凹槽31中填充第二導電材料40。所述第二導電材料40填滿所述第三凹槽31。本實施方式中,通過印刷方式將所述第二導電材料40填充於所述第三凹槽31中。Step S7, please refer to FIG. 7, filling the
步驟S8,請參閱圖8,去除部分第二導電材料40形成第四凹槽41,得到第二導體層42。去除了部分的第二導電材料40作為所述第二導體層42,被去除的部分第二導電材料40所在空間作為所述第四凹槽41。本實施方式中,通過鐳射切割方式去除部分第二導電材料40。In step S8 , please refer to FIG. 8 , part of the second
在一些實施方式中,所述第四凹槽41的截面形狀為U形,即,所述第二導體層42的截面形狀為U形。In some embodiments, the cross-sectional shape of the
步驟S9,請參閱圖9,在所述第四凹槽41中填充第二絕緣材料50。所述第二絕緣材料50填滿所述第四凹槽41。本實施方式中,通過印刷方式將所述第二絕緣材料50填充於所述第四凹槽41中。In step S9 , please refer to FIG. 9 , filling the
步驟S10,請參閱圖10,去除部分第二絕緣材料50形成第五凹槽51,得到第二絕緣層52。去除了部分的第二絕緣材料50作為所述第二絕緣層52,被去除的部分第二絕緣材料50所在空間作為所述第五凹槽51。本實施方式中,通過鐳射切割方式去除部分第二絕緣材料50。In step S10 , please refer to FIG. 10 , part of the second
在一些實施方式中,所述第五凹槽51的截面形狀為U形,即,所述第二絕緣層52的截面形狀為U形。In some embodiments, the cross-sectional shape of the
步驟S11,請參閱圖11,在所述第五凹槽51中填充第三導電材料,得到第三導體層60。填充在所述第五凹槽51中的第三導電材料固化後,形成所述第三導體層60。本實施方式中,通過印刷方式將所述第三導電材料填充於所述第五凹槽51中。In step S11 , please refer to FIG. 11 , filling the
所述第三導體層60大致位於所述第一凹槽101的中心位置。所述第三導體層60的截面形狀大致為矩形。所述第一導體層22的二側壁分別與第一銅箔層13相連接,所述第一導體層22的底壁與所述第二銅箔層14相連接。The
所述第一導體層22具有露出於所述雙面覆銅板10外的暴露面221,所述第一絕緣層32具有露出於所述雙面覆銅板10外的暴露面321,所述第二導體層42具有露出於所述雙面覆銅板10外的暴露面421,所述第二絕緣層52具有露出於所述雙面覆銅板10外的暴露面521,所述第三導體層60具有露出於所述雙面覆銅板10外的暴露面61,其中,各個暴露面均與所述第一銅箔層13背離所述基材層11的表面相平齊。The
在一些實施方式中,所述第一導電材料20、所述第二導電材料40以及所述第三導電材料均選自導電銅膏或導電銀膏中的至少一種。In some embodiments, the first
在一些實施方式中,所述第一絕緣材料30、所述第二絕緣材料50均選用高頻材料,例如液晶高分子聚合物(liquid crystal polymer,LCP)、聚四氟乙烯(polytetrafluoroethylene,PTFE)、聚醚醚酮(poly-ether-ether-ketone,PEEK)、聚苯醚(polyphenylene oxide,PPO)等。In some embodiments, the first insulating
可以理解的是,位於所述第一凹槽101中的導體層的數量可根據實際需要設置,相鄰導體層之間通過絕緣層隔離。It can be understood that the number of conductor layers located in the
步驟S12,請參閱圖12,在所述第一銅箔層13和第二銅箔層14上進行線路製作,形成第一導電線路層131和第二導電線路層141,得到電路基板100。Step S12, please refer to FIG. 12. Circuit fabrication is performed on the first
所述第一導電線路層131與位於所述第一凹槽101中所述第一導體層22的二側壁相連接,所述第二導電線路層141與所述第一導體層22的底壁相連接。The first
本實施方式中,通過影像轉移技術在所述第一銅箔層13和第二銅箔層14上進行線路製作。In this embodiment, circuit production is performed on the first
請參閱圖13a,在一些實施方式中,所述電路基板100還包括形成在所述第一導體層22、所述第二導體層42以及所述第三導體層60中至少二者的暴露面上的導電層110,以連接相應的導體層。如圖13a所示,所述導電層110形成在所述第一導體層22、所述第一絕緣層32、所述第二導體層42的暴露面上,以連接所述第一導體層22和所述第二導體層42。如圖13b所示,所述導電層110形成在所述第二導體層42、所述第二絕緣層52以及所述第三導體層60的暴露面上,以連接所述第二導體層42和所述第三導體層60。如圖13c所示,所述導電層110形成在所述第一導體層22、所述第一絕緣層32、所述第二導體層42、所述第二絕緣層52以及所述第三導體層60的暴露面上,以連接所述第一導體層22、所述第二導體層42和所述第三導體層60。Referring to FIG. 13a, in some embodiments, the
步驟S13,請參閱圖14,在所述第一導電線路層131、所述第一導體層22、所述第二導體層42以及所述第三導體層60背離所述第二導電線路層141的表面形成圖案化的金屬層70。Step S13, please refer to FIG. 14, when the first
圖案化的金屬層70包括間隔設置的多個連接墊71,每個連接墊71設置於相應的第一導電線路層131、所述第一導體層22、所述第二導體層42以及所述第三導體層60。本實施方式中,所述金屬層70的材料為錫。The patterned
步驟S14,請參閱圖15,在所述第一導電線路層131的線路間隙和相鄰連接墊71之間的間隙中填充絕緣材料形成第三絕緣層80,並在所述第二導電線路層141背離所述第一導電線路層131的一側覆蓋一覆蓋膜90,得到層疊結構200。本實施方式中,通過印刷方式將絕緣材料填充於第一導電線路層131的線路間隙和圖案化的金屬層70的間隙中。Step S14, please refer to FIG. 15, filling the insulating material in the gap between the line gaps of the first
所述第三絕緣層80的材質選自LCP、PTFE、PEEK、PPO中的至少一種。The third insulating
步驟S15,請參閱圖16,提供另一層疊結構200,並將該另一層疊結構200對接在所述金屬層70背離所述基材層11的一側,得到電路板300。二覆蓋膜90位於所述電路板100的外側。Step S15 , please refer to FIG. 16 , provide another
二層疊結構200中,二第一導體層22的位置相對應並通過相應的連接墊71相連接,二第二導體層42的位置相對應並通過相應的連接墊71相連接,二第三導體層60的位置相對應並通過相應的連接墊71相連接,從而形成“回”型傳輸線。In the two-
在一些實施方式中,所述第一導體層22、所述第二導體層42、所述第三導體層60同軸設置,所述第三導體層60為高頻傳輸線,所述第二導體層42為遮罩層,所述第一導體層22為傳輸線或電源線。相連接的二第二導體層42環繞相連接的二第三導體層60設置,形成全包覆遮罩。In some embodiments, the
在另一些實施方式中,所述第二導體層42為傳輸線,所述第一導體層22為遮罩層,使得所述電路板300中具有二獨立的傳輸線,互不干擾。In other embodiments, the
請再次參閱圖16,本申請一實施方式提供一種電路板300,包括二電路基板100以及設置於二電路基板100之間的金屬層70以及第三絕緣層80。Please refer to FIG. 16 again. An embodiment of the present application provides a
每個電路基板100包括基材層11、第一導電線路層131、第二導電線路層141、第一導體層22、第一絕緣層32、第二導體層42、第二絕緣層52以及第三導體層60。所述第一導電線路層131和所述第二導電線路層141分別設置於所述基材層11相對的兩表面上。所述電路基板100開設有第一凹槽101,所述第一凹槽101貫通所述基材層11和所述第一導電線路層131,所述第二導電線路層141從所述第一凹槽101露出。Each
所述第一導體層22設置於所述第一凹槽101中,並與所述第一導電線路層131和所述第二導電線路層141相連接。所述第一導體層22開設有第二凹槽21,所述第一絕緣層32設置於所述第二凹槽21中。所述第一絕緣層32開設有第三凹槽31,所述第二導體層42設置於所述第三凹槽31中。所述第二導體層42開設有第四凹槽41,所述第二絕緣層52設置於所述第四凹槽41中。所述第二絕緣層52開設有第五凹槽51,所述第三導體層60設置於所述第五凹槽51中。The
在一些實施方式中,所述第一凹槽101、所述第一導體層22、所述第二凹槽21、所述第一絕緣層32、所述第三凹槽31、所述第二導體層42、所述第四凹槽41、所述第二絕緣層52以及所述第五凹槽51的截面形狀均為U形,所述第三導體層60的截面形狀為矩形。In some embodiments, the
所述第一導體層22具有露出於所述電路基板100外的暴露面221,所述第一絕緣層32具有露出於所述電路基板100外的暴露面321,所述第二導體層42具有露出於所述電路基板100外的暴露面421,所述第二絕緣層52具有露出於所述電路基板100外的暴露面521,所述第三導體層60具有露出於所述電路基板100外的暴露面61,其中,各個暴露面均與所述第一導電線路層131背離所述基材層11的表面相平齊。The
所述金屬層70包括間隔設置的多個連接墊71,每個連接墊71設置於相應的第一導電線路層131、所述第一導體層22、所述第二導體層42以及所述第三導體層60的暴露面上。The
所述第三絕緣層80填充於所述第一導電線路層131的線路間隙和相鄰連接墊71之間的間隙中。The third insulating
二電路基板100中,二第一導體層22的位置相對應並通過相應的連接墊71相連接,二第二導體層42的位置相對應並通過相應的連接墊71相連接,二第三導體層60的位置相對應並通過相應的連接墊71相連接,從而形成“回”型傳輸線。In the two
所述電路板300相對的二表面設置有覆蓋膜90。所述覆蓋膜90包括層疊設置的膠粘層91和覆蓋層92。所述膠粘層91覆蓋所述第二導電線路層141。所述膠粘層91的材質為常用膠粘劑,所述覆蓋層的材料為PET。Covering
本申請提供的電路板300及其製作方法,通過在雙面電路基板上開設第一凹槽101,並在第一凹槽101中設置多個導體層,使得該雙面電路基板具有多層電路基板的功效,降低了電路基板的厚度,有利於薄型化。The
另外,本領域技術人員還可在本發明精神內做其它變化,當然,這些依據本發明精神所做的變化,都應包含在本發明所要求保護的範圍內。In addition, those skilled in the art can also make other changes within the spirit of the present invention. Of course, these changes made based on the spirit of the present invention should be included in the scope of protection claimed by the present invention.
10:雙面覆銅板
11:基材層
13:第一銅箔層
14:第二銅箔層
101:第一凹槽
20:第一導電材料
21:第二凹槽
22:第一導體層
30:第一絕緣材料
31:第三凹槽
32:第一絕緣層
40:第二導電材料
41:第四凹槽
42:第二導體層
50:第二絕緣材料
51:第五凹槽
52:第二絕緣層
60:第三導體層
221、321、421、521、61:暴露面
131:第一導電線路層
141:第二導電線路層
110:導電層
70:金屬層
71:連接墊
80:第三絕緣層
90:覆蓋膜
200:層疊結構
91:膠粘層
92:覆蓋層
300:電路板
100:電路基板
10:Double-sided copper clad laminate
11:Substrate layer
13: First copper foil layer
14: Second copper foil layer
101: First groove
20: First conductive material
21: Second groove
22: First conductor layer
30:The first insulating material
31:Third groove
32: First insulation layer
40: Second conductive material
41:Fourth groove
42: Second conductor layer
50: Second insulation material
51:Fifth groove
52: Second insulation layer
60:
圖1為本申請一實施方式提供的雙面覆銅板的截面圖。Figure 1 is a cross-sectional view of a double-sided copper-clad laminate provided by an embodiment of the present application.
圖2為在圖1所示雙面覆銅板上形成凹槽後的截面圖。Figure 2 is a cross-sectional view after forming grooves on the double-sided copper-clad board shown in Figure 1.
圖3為在圖2所示凹槽中形成第一導電材料後的截面圖。FIG. 3 is a cross-sectional view after forming the first conductive material in the groove shown in FIG. 2 .
圖4為去除圖3所示部分第一導電材料形成第一導體層後的截面圖。FIG. 4 is a cross-sectional view after removing part of the first conductive material shown in FIG. 3 to form a first conductor layer.
圖5為在圖4所示第一導體層上形成第一絕緣材料後的截面圖。FIG. 5 is a cross-sectional view after forming the first insulating material on the first conductor layer shown in FIG. 4 .
圖6為去除圖5所示部分絕緣材上形成第一絕緣層後的截面圖。FIG. 6 is a cross-sectional view after removing the first insulating layer formed on the part of the insulating material shown in FIG. 5 .
圖7為在圖6所示第一絕緣層上形成第一導電材料後的截面圖。FIG. 7 is a cross-sectional view after forming the first conductive material on the first insulating layer shown in FIG. 6 .
圖8為去除圖7所示部分第一導電材料形成第二導體層後的截面圖。FIG. 8 is a cross-sectional view after removing part of the first conductive material shown in FIG. 7 to form a second conductor layer.
圖9為在第二導體層上形成第一絕緣材料後的截面圖。Figure 9 is a cross-sectional view after forming the first insulating material on the second conductor layer.
圖10為去除圖9所示部分第一絕緣材料形成第二絕緣層後的截面圖。FIG. 10 is a cross-sectional view after removing part of the first insulating material shown in FIG. 9 to form a second insulating layer.
圖11為在圖10所示第二絕緣層上形成第三導體層後的截面示意圖。FIG. 11 is a schematic cross-sectional view after forming a third conductor layer on the second insulating layer shown in FIG. 10 .
圖12為對圖11所示結構進行線路製作後的截面示意圖。Figure 12 is a schematic cross-sectional view of the structure shown in Figure 11 after circuit production.
圖13a為本申請一實施方式提供的電路基板的截面示意圖。Figure 13a is a schematic cross-sectional view of a circuit substrate provided by an embodiment of the present application.
圖13b為本申請另一實施方式提供的電路基板的截面示意圖。Figure 13b is a schematic cross-sectional view of a circuit substrate provided by another embodiment of the present application.
圖13c為本申請又一實施方式提供的電路基板的截面示意圖。Figure 13c is a schematic cross-sectional view of a circuit substrate provided by another embodiment of the present application.
圖14為在圖12所示導電層的表面形成金屬層後的截面示意圖。FIG. 14 is a schematic cross-sectional view after forming a metal layer on the surface of the conductive layer shown in FIG. 12 .
圖15為在圖14所示結構上設置第三絕緣層和覆蓋膜後的截面示意圖。FIG. 15 is a schematic cross-sectional view after a third insulating layer and a cover film are provided on the structure shown in FIG. 14 .
圖16為本申請一實施方式提供的電路板的截面示意圖。Figure 16 is a schematic cross-sectional view of a circuit board provided by an embodiment of the present application.
無without
11:基材層 11:Substrate layer
101:第一凹槽 101: First groove
21:第二凹槽 21: Second groove
22:第一導體層 22: First conductor layer
31:第三凹槽 31:Third groove
32:第一絕緣層 32: First insulation layer
41:第四凹槽 41:Fourth groove
42:第二導體層 42: Second conductor layer
51:第五凹槽 51:Fifth groove
52:第二絕緣層 52: Second insulation layer
60:第三導體層 60:Third conductor layer
221、321、421、521、61:暴露面 221, 321, 421, 521, 61: exposed surface
131:第一導電線路層 131: First conductive circuit layer
141:第二導電線路層 141: Second conductive circuit layer
100:電路基板 100:Circuit substrate
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JP2012186377A (en) * | 2011-03-07 | 2012-09-27 | Ube Ind Ltd | Method for manufacturing polyimide metal laminate |
TW202031104A (en) * | 2018-11-27 | 2020-08-16 | 日商日東電工股份有限公司 | Wiring circuit board and manufacturing method thereof |
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JP2006310783A (en) * | 2005-03-30 | 2006-11-09 | Sanyo Electric Co Ltd | Circuit device |
US9113565B2 (en) * | 2012-06-19 | 2015-08-18 | Shennan Circuits Co., Ltd | Method for processing printed circuit board, printed circuit board and electronic apparatus |
CN103517584A (en) * | 2012-06-27 | 2014-01-15 | 富葵精密组件(深圳)有限公司 | Manufacturing method of multilayer circuit board |
CN104349574B (en) * | 2013-07-31 | 2018-02-02 | 鹏鼎控股(深圳)股份有限公司 | Circuit board and preparation method thereof |
CN105792501B (en) * | 2014-12-23 | 2018-10-30 | 鹏鼎控股(深圳)股份有限公司 | Circuit board and preparation method thereof |
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JP2012186377A (en) * | 2011-03-07 | 2012-09-27 | Ube Ind Ltd | Method for manufacturing polyimide metal laminate |
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