TWI817998B - Predictive sample queueing for time-shared adc in a multiphase pwm controller - Google Patents

Abstract

In one or more embodiments, an efficient scheme is provided for sampling inductor currents in a digital multiphase PWM controller used for high-bandwidth voltage regulation. Some embodiments use the data from the PWM modulator along with weighted states based on the PWM waveform and past conversions in order to prioritize which current sense input should be sampled for each conversion. In these and other embodiments, a single ADC is used to sample inductor currents from two or more phases in a multiphase PWM controller, thereby providing power and area savings, for example.

Description

Predictive sample queuing for time-shared ADCs in polyphase PWM controllers

Cross-references to related applications

This patent application claims priority from U.S. Provisional Application No. 62/645,624, filed on March 20, 2018, the contents of which are incorporated herein by reference in their entirety.

Embodiments of the present invention relate generally to power converters, and more particularly to prioritizing sample distribution of time-shared analog-to-digital converters (ADCs) between phases in a multiphase PWM controller.

Polyphase PWM controllers generally use a common PWM period in all phases and stagger the PWM so that the pulses of each phase are equally spaced in time within a PWM period. Utilizing high-bandwidth inductor current information can improve voltage regulation performance. For digital controllers, this may require a high sample rate ADC to convert the analog inductor current signal into a digital representation. The area and energy consumption of this ADC function is high, usually proportional to the sampling rate. Therefore, these and other issues need to be addressed.

In one or more embodiments, an efficient scheme for sampling inductor current in a digital polyphase PWM controller for high bandwidth voltage regulation is provided. Some embodiments use data from the PWM modulator and weighted states based on the PWM waveform and past transitions to prioritize which current sense input should be sampled for each transition. In these and other embodiments, a single ADC is used to sample inductor current from two or more phases in a multiphase PWM controller, thereby achieving power and area savings, for example.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which are provided as illustrative examples of embodiments to enable those skilled in the art to practice the embodiments and alternatives apparent to those skilled in the art. It is important to note that the drawings and examples are not meant to limit the scope of embodiments of the invention to a single embodiment, but that other embodiments may be obtained by interchanging some or all of the described or illustrated elements. Furthermore, in the case where certain elements of embodiments of the present invention can be partially or fully implemented using known elements, only those parts of such known elements that are necessary for understanding the embodiments of the present invention will be described and omitted Other parts of such known elements are described in detail so as not to obscure the embodiments of the present invention. As will be apparent to those skilled in the art, embodiments described as implemented in software should not be limited thereto, but may include embodiments implemented in hardware or a combination of software and hardware, and vice versa, unless otherwise stated herein. . In this specification, embodiments showing a single component should not be considered limiting; rather, other embodiments including plurals of the same component, and vice versa, are intended to cover unless otherwise expressly stated herein. Furthermore, the applicant does not intend to give unusual or special meaning to any term in the specification or claims unless expressly stated otherwise. Furthermore, embodiments of the present invention include both currently known and future known equivalents of known components mentioned herein by way of illustration.

According to certain aspects, embodiments of the invention provide an efficient scheme for sampling inductor current in a digital polyphase PWM controller for high bandwidth voltage regulation. Some embodiments use data from the PWM modulator and weighted states based on the PWM waveform and past transitions to prioritize which current sense input should be sampled for each transition.

As a background art, an input voltage VIN is typically converted into a regulated output required by one or more load devices via a switching voltage regulator or buck regulator, also known as a voltage converter, point of load regulator or power converter. voltage V _OUT to perform DC-DC voltage conversion. More generally, voltage regulators and current regulators are collectively referred to as power converters, and as used herein, the term power converter is meant to encompass all such devices. Switching voltage regulators typically use two or more power transistors to convert energy from one voltage to another. Figure 1 illustrates a common example of such a voltage regulator 100, often referred to as a "buck regulator." Buck regulator 100 is a switching regulator (or switching power converter) that typically switches a pair of power transistors (138 and 140) connected between V _IN and ground to generate power at the transistors' common node SW. Wave. The resulting square wave can be smoothed using an LC circuit including inductor 142 and capacitor 144 to produce the desired voltage V _OUT . Includes error amplifier 146, proportional-integral-derivative (PID) control filter 132, pulse width modulator (PWM) 134, and output control circuit 136 including drivers for driving the high and low sides of FETs 138 and 140, respectively. The feedback control loop of the circuit) can be configured to control the duty cycle of the output square wave and therefore the resulting value of V _OUT based on the input voltage V _IN . It should be noted that although embodiments of the present invention are described in connection with the example application of a buck regulator, they are not limited thereto. Conversely, embodiments of the invention may also be implemented as other types of regulators, such as buck-boost and boost regulators.

Voltage regulators, such as regulator 100, are sometimes included in current sharing configurations in which power is distributed via a shared supply voltage. Distributing power via shared load feed points has several notable advantages over single load feed points or regulators. Distributing power or current sharing can be used to accommodate the increasing current demands associated with low voltage applications via higher efficiency over a wider output current range, reliability via redundancy, and distributed cooling.

Figure 2 illustrates an example of a current sharing configuration. As shown in Figure 2, polyphase regulator 280 includes multiple output stages (secondary stages 154 and 156 are shown in this example) with FET pairs (172/174 and 176/178) and inductors (153 and 155). The output stages 154, 156 provide a single output voltage V _OUT (e.g., across capacitor 160 to example load 162) using a single controller (e.g., controller IC 152) and a single input of voltage feedback V _FB , a single compensator (i.e., , PID) and multiple PWM outputs. Multiple PWM outputs may be provided to various output stages (ie, drive circuits) 154 and 156. In some embodiments, the output stages may be implemented collectively via a single circuit or IC, or the output stages may be included in the controller IC 152 . Phase-to-phase communication busses in the multiphase regulator 280 may be included in the controller 152, allowing for high bandwidth current sharing among digital controllers. Although only two output stages are illustrated in the embodiment of Figure 2, various embodiments may include more output stages similarly arranged in the manner shown. Those skilled in the art will understand that the various illustrations of converters (or voltage regulators) and voltage regulator systems disclosed herein are intended to cover all possible implementations in accordance with the principles required herein.

In many regulators, information about the current (i.e., the inductor current, e.g., the current in inductor 142 in voltage supply/regulator 100) is required in a PWM controller (e.g., PWM controller 134 in Figure 1). It is indispensable for many functions of the service. These features include voltage accuracy, transient response, current balancing, circuit error protection and telemetry. Obtaining high-quality inductor current information to support these functions can be one of the many challenging requirements of controller IC design. Quality can be quantified in precision, accuracy, bandwidth and latency. High quality comes from high precision, high accuracy, high bandwidth and/or low latency.

Synthetic inductor current from known system parameters alleviates most of the challenges of obtaining current information on individual current measurements. This is due to the fact that the dynamic composition of the current in the inductor (i.e., how the current changes over time) can be calculated from the system parameters, which is less of a challenge to obtain high accuracy than obtaining the current value itself. The first order system parameters include the voltage across the inductor and the inductance value [di/dt=V/L]. A more precise calculation may include inductor and/or switching losses. Another more complex calculation may include nonlinearity or parameter drift over time. All such characteristics can be estimated or measured at low cost in circuit area and power consumption. More complex calculations improve the quality of synthesized information, but incur costs in computational circuit area and power consumption. Higher quality synthetic (or computational) information can reduce the cost of the measurement circuitry required to provide the vanishing steady-state inductor current component. In systems where synthesizers are designed with digital logic, total cost and power optimization can benefit through scaling based on Moore's Law, using primarily analog circuits to measure steady-state inductor current. This scheme of obtaining output current information can be very attractive for digital power controllers. However, even in controllers that include a current combiner as previously described, accurate inductor current measurement is still required for combiner current correction and other functions.

In summary, various embodiments of the regulators disclosed herein include power supply (or power converter or voltage regulator) control circuits designed to aid in optimal operation of the switching regulator/power supply, including the use of precise current measurements to improve Precise current synthesis. Figure 3 illustrates a block diagram of one embodiment of a system 300 including a power supply 301 designed in accordance with the principles described herein, as will be described in detail below. System 300 includes at least one example of a power supply/power regulator 301 that provides one or more supply voltages to system integrated circuits (or processing elements) 310, one or more peripheral devices 307, and a memory subsystem (or memory )305. Memory 305 may include, for example, program instructions executable by processing element 310 to perform various system functions, which may also include controlling and/or operating peripheral devices 307 .

In some embodiments, more than one power supply/converter 301 may be included. Furthermore, regulator 301 may include one or more power control integrated circuits, such as power control ICs 312 and 314. The power control ICs 312 and 314 may include various components, such as feedback control circuits, PWM modulation circuits, output stage control circuits, etc. Furthermore, in some embodiments, the control circuitry may not be included on a separate IC, but may simply be part of the power supply 301. In summary, various embodiments of the power supply 301 can be divided into two main components, a driver stage containing high-side and low-side FETs, and a control circuit including elements that perform control of the drive signals that drive the FETs in the output stage. As shown in Figure 3, the control circuit is implemented in the form of an IC, which can be coupled to a driver stage (such as the output control stage 136 shown in Figure 1), or can be directly coupled to the high-side FET and low-side FET, such as in Figure 1 FETs 138 and 140. In some embodiments, system 300 itself may be a system-on-a-chip (SOC), whereby system 300 is an IC with all components including voltage 301 and voltage control ICs 312 and/or 314 as part of the same IC. part.

Peripheral devices 307 may include any desired circuitry depending on the type of system. For example, in one embodiment, system 300 may be included in a mobile device (eg, a personal digital assistant (PDA), a smartphone, etc.) and peripheral devices 307 may include devices for various types of wireless communications, such as Wi-Fi. Fi, Bluetooth, cellular network, GPS, etc. Peripheral devices 307 may also include additional storage, including RAM storage, solid state storage, or disk storage. Peripheral devices 307 may include user interface devices, such as a display screen including a touch display screen or a multi-touch display screen, a keyboard or other input device, a microphone, a speaker, etc. In other embodiments, system 300 may be included in any type of computing system (eg, desktop personal computer, laptop computer, workstation, online system, etc.). Furthermore, system memory 305 may include any type of memory.

Figure 4 illustrates several embodiments of a computing system that may include all or part of system 300, more specifically power supply 301 and/or power control ICs 312 and/or 314. System 401 may represent a desktop computer, system 402 may represent a laptop computer, and system 403 may represent a tablet computer or smart phone with a wireless keyboard. System 401 may include one or more human-machine peripheral devices (HID), such as keyboards, mice, microphones, cameras, etc. Systems 402 and 403 may include HIDs similar to system 401. Other devices not shown, such as smart televisions or video game consoles, may also include power supply or voltage controllers such as those disclosed herein in various forms or embodiments. Note that the computer system shown in Figure 4 is provided as an example only. Other types of systems with power supplies/power regulators and power controller ICs are also possible and may be considered.

Additionally, and as previously stated, Applicants recognize that accurately sensing inductor current (eg, current in inductors 153, 155 in Figure 2) throughout the PWM switching cycle can be difficult and expensive. For example, traditional solutions tend to provide an accurate representation of the inductor current only during a small time window within the PWM cycle, leaving the remainder of the cycle noisy or inaccurate. More specifically, as shown in Figure 5, waveform 502 represents the PWM modulator (eg, 134 in Figure 1) output for a given phase (ie, one phase in the multiphase controller). Meanwhile, waveform 504 represents the corresponding inductor current in that phase. As shown in Figure 5, accurate current sensing data can only be obtained during intervals 508 of the current waveform 504, which correspond to the times when the PWM modulator output 502 is in the low state (i.e., the high-side FET 138 is off and Low side FET 140 conducts). However, during intervals 510 of the current waveform 504, when the inductor current increases in response to the high state of the PWM modulator output 502, the current sensing data can be very unreliable and inaccurate.

Applicants recognize that a digital system can be made more accurate by utilizing only samples taken during a precise portion of the signal from the current sensor (e.g., interval 508 in Figure 5), and that the The more samples the better. Observed in the context of a single phase, the optimal distribution of samples would be to burst all samples during a precise portion of the inductor current signal, and pause until the next precise window. However, an ADC that supports this scheme will waste power and area dedicated to that phase in proportion to the partial window sampled within the PWM cycle. But looking at the context of a multi-phase system, the authors envisage a more optimal use of this same ADC via time-sharing of its samples over multiple phases, the precise time windows of which are in time Proprietary.

For example, the authors recognized that in the steady state of a polyphase controller, the PWM period is fixed and the phase relationships between phases are evenly distributed, which makes it easy to optimally time share sampling so that it follows phase interleaving model. More specifically, as shown in Figure 6, waveform 602 represents the PWM modulator (eg, 134 in Figure 1) output for each of the four phases of a four-phase controller. In this example, the PWM periods are all the same, and the "high" state portion of PWM waveform 602 is evenly distributed between phases. Waveform 604 represents the inductor current in each phase produced in response to PWM waveform 602 . Because the "high" state portion of the PWM waveform 602 is very evenly distributed, the precise portion 606 of the current waveform 604 (eg, as described above in Figure 5) is also very evenly distributed. In this way, a simple TDM approach using a single shared ADC can be used to sequentially measure the current waveform 604 of each phase, one at a time.

Although the example of Figure 6 makes time sharing of samples fairly easy, in reality the PWM period and phase relationship can change significantly as the load on the voltage regulator changes. This is especially true if the modulation scheme uses dual-edge modulation, dynamically switching frequencies, or other techniques that make the PWM edges non-periodic. Optimal time sharing under dynamic loads requires that the time sharing follows the modulation of all PWM phases of the shared ADC.

Optimal time sharing may be further complicated in systems that employ predictions from the current information used in the modulator. Returning to Figure 5, and as mentioned previously, such a system can be derived from a known PWM signal (e.g., waveform 502 in Figure 5) as well as other parameters that affect the inductor current, such as input and output voltages, PWM propagation delays, and inductor values. ) to synthesize inductor current information (e.g., waveform 506 in Figure 5). Because of the predictive nature of such systems, they have the potential to deviate from the actual inductor current. This is especially true in the case of dynamic loading when system parameters are more dynamic. Bias may be included due to providing accurately measured inductor current to the synthesizer at a sufficient rate and at critical times when the synthesizer may error. Therefore, the optimal sharing of ADC samples of the actual inductor current between phases can be determined to some extent by the synthesizer architecture and system component characteristics.

According to some aspects, some embodiments, described in greater detail below, use information from a PWM modulator (eg, in controller 152 in FIG. 2) and weights based on the PWM waveform and past transitions to target each transition. , sets the priority for which current sense inputs should be sampled. As mentioned previously, the PWM modulator generates a PWM signal to be sent to an external output stage (such as 154 and 156 in Figure 2) or a FET. The PWM signal received by the output stage is then level shifted and applied to the power FETs (eg, 172-178 in Figure 2) used to drive the power inductors (eg, 153 and 155 in Figure 2). The resulting current sensed on the low voltage FET device is then driven onto pins of the output stage (e.g. 154 and 156 in Figure 2) which are connected back to the controller to be sensed (e.g. Control in Figure 2 device 152). The total time from PWM generation to the resulting analog sensing is often a few system clock cycles (e.g. around 80ns). As shown in Figure 5, and as mentioned previously, most output stages only produce useful data when the low-voltage FET is on because current is sensed flowing through the low-voltage FET. Therefore, the preferred portion of the PWM signal to measure is starting approximately 300ns after the PWM goes low until the PWM goes high. Furthermore, in a typical polyphase modulator, the phases are sequenced throughout the switching cycle to minimize ripple, which ensures that not all are the same in general and that there is valuable information.

By programming the device with weighted states based on the PWM modulator and collecting data based on past samples, methods according to embodiments of the present invention establish a queuing system that will feed useful signals from multiple phases into a shared ADC. Data sampling takes the maximum value. The queuing system determines which phase should be sampled next, ensures that all phases have recently received valid data, and selects the next sampled phase based on the state of the modulator (i.e., where in the analog waveform the ADC will sample). This queuing system can also be used to determine the optimal time for the ADC to take auto-zero samples to minimize ADC offset. Because the resulting samples are non-periodic, embodiments of the present invention also track the sampling frequency of each phase to account for the varying input impedance on each phase. Additionally, each phase can be programmed with a minimum sampling period, which can be set to ensure maximum sampling frequency for each phase.

7 is a timing diagram illustrating an example aspect of predictive sample queuing in accordance with an embodiment. As shown, the controller generates PWM waveforms 702 for each phase of the 4-phase converter. In this example, due to load requirements, waveforms 702 are not equally spaced and interleaved between phases as in the example of Figure 5. Waveforms 704 represent the corresponding inductor currents in the four phases produced in response to the PWM waveform 702, with each waveform 704 having a precise portion 706 as previously described. Also in this example, the load is being reduced, so the phases are falling progressively, starting with Ph3 falling, then Ph2 falling, then Ph1 falling, and now Ph0 is being operated.

The table below the waveform indicates which phase the inductor current samples are taken from during each sampling period. It can be seen that compared to the simple TDM technique (i.e., sampling in row 710), the inductor current samples are taken from the phase with the most accurate current information during a given sampling period (i.e., using embodiments of the present invention, row 710) 708). For example, in cycles 0 and 1, the current is sampled from Ph2 (instead of 0 and 1 in the TDM method); in cycle 2, the current is sampled from Ph0; in cycle 3, the current is sampled from Ph1, and so on. As further shown in the table, the present method reduces the number of imprecise samples 712 obtained using simple TDM methods. Setting priorities, ie how phases are allocated for sampling in a given sampling period, is described in more detail below.

8 is a block diagram illustrating an example implementation of a predictive sampling scheme in a converter according to an embodiment.

As shown in this example, controller 800 (eg, the example implementation of 152 in FIG. 2 ) includes a digital portion 802 and an analog portion 804 . Digital section 802 includes loop/modulator 806, current synthesizer 808, and sample queuing system 810.

Analog section 804 includes a current sensing analog to digital converter (Isen ADC) 812 and a multiplexer 814. Based on the signal from the queuing system 810, the Isen ADC 812 obtains analog samples from phases Ph1 to Ph4 via the multiplexer 814. The samples are digitized and provided to synthesizer 808 and queuing system 810. One aspect of an embodiment of the present invention requires only a single ADC 812 to sample the inductor current from all phases Ph1 to Ph4 under the control of the sample queuing system 810 .

The current samples from the ADC 812 can be used for current synthesizer correction, for example as described in US Patent 9,419,627, the contents of which are incorporated herein by reference in their entirety. Synthesizer 808 in turn provides corrected current synthesizer data to loop/modulator 806, as used, for example, in co-pending U.S. Patent Application No. 16/357,212 (the contents of which are incorporated by reference in their entirety). The combination of predicted data and measured data described in this article). Loop/modulator 806 uses the generated current data from synthesizer 808 and other information to generate appropriate PWM modulated signals to output stage 816 which uses the signals to drive current to power station 818 .

9 is a timing diagram illustrating aspects of an exemplary method for implementing sample queuing system 810, according to an embodiment.

As shown in Figure 9, waveform 902 represents the PWM modulator output for a given phase, and waveform 904 represents the corresponding inductor current for the given phase produced in response to waveform 902. As further shown, embodiments of the present invention recognize three primary states: a low state, in which the switch terminal of the inductor is actively pulled to a low voltage via a low-side switch or FET (eg, 140 in Figure 1); and a high state, in which Active pulling of the inductor's switch terminal to high voltage via a high-side switch or FET (e.g., 138 in Figure 1); and Mid/Hi-Z state (i.e., dio) where both switches or FETs are in a non-conducting state . In the final state, the inductor current will forward bias the body diode of one of the two FETs, the FET in question being determined/selected based on the polarity of the inductor current.

Figure 9 also illustrates transition states 906 between each main PWM state according to an embodiment. These transition states describe the time period during which the system is in the process of exiting an event. For each PWM event (rising edge, falling edge, mid-drive/Hi-Z state), a time period (or length of time) can be specified for each designated time slot. Specified time slots can be divided into two categories, namely "Settle" time slots and "Settled" time slots. Therefore, as shown in Figure 9, there may be different "Settle" time slots and "Settled" time slots for each PWM event.

As further shown in Figure 9, a corresponding weight 908 may be assigned (ie, configured) for each corresponding time slot 906. The corresponding weight 908 values are used by the queuing system 810 to determine how to prioritize ADC samples between phases for any given sampling period. In this example, there are three possible weight values, 0 means no current sampling accuracy, 1 means very little current sampling accuracy, and 3 means high current sampling accuracy. This facilitates sampling every precise portion of the corresponding current sensing waveform, while limiting or zeroing the current sampling in portions of the waveform where the actual current sensing waveform may be noisy or simply ineffective. For example, although samples may be obtained on the rising segment in the CFG _hiSettled time slot, low weight values indicate that the sampled current in that segment may be inaccurate. On the other hand, the samples obtained on the descending segment in the CFG _loSettled time slot can be very accurate, as shown by the relatively high weight values.

Therefore, in operation, in each sampling period, the queuing system 810 receives the modulator waveform 902 information for each phase and determines the time slot 906 in which that phase currently resides. Based on the time slot 906, the queuing system 810 further determines the weight value 908 to apply to each phase. In one example, the phase with the highest weight in a given sampling period will be selected to be sampled by ADC 812 via generating appropriate control signals to multiplexer 814 . In these and other embodiments, the queuing system 810 may include memory or storage that contains a configuration of designated "slots" of PWM waveforms and the weights assigned to them, and may access the memory or storage to Used to determine the phase with the highest weight for a given sampling period.

Referring back to Figure 7, it can be seen that compared to the simple TDM method (in which samples of each phase are obtained at a fixed sampling frequency), the effective sampling frequency of each phase is not fixed in embodiments of the present invention. This can cause the ADC input impedance of each phase to be different for each sample, and therefore the gain of each phase to be different for each sample. This way, in some embodiments, the actual sampling frequency of each phase is tracked and used to adjust the ADC gain as needed. Additionally and relatedly, the queuing system 810 may include a fixed maximum delay between samples of a given phase, and in addition to or instead of calculating weights, this may be used to decide which phase to sample for a given sampling period. In other words, if a given phase has not been sampled after the maximum delay since it was last sampled, it will be selected for sampling in the current sampling period, even if its weight is not the largest among all phases. In other embodiments, instead of or in addition to having a fixed maximum sampling delay, the period between samples of each phase may be a programmable parameter.

In this regard, FIG. 10 is a timing diagram illustrating an additional or alternative aspect of a prioritized sampling scheme that includes programmable minimum periods, according to an embodiment.

In this example, waveform 1002 represents the inductor current in the controller for each phase of a 4-phase converter. In this example, similar to the waveforms shown in Figure 7, due to load requirements, the waveforms 1002 and their respective precise portions 1004 are not equally spaced and interleaved between phases as in the example of Figure 5. Further similar to Figure 7, in this example the controller load is decreasing so the phases decrease progressively, starting with Ph3, then Ph2, then Ph1.

Table 1006 indicates which phase the inductor current is sampled from during each sampling period. Unlike the embodiment of Figure 7, in addition to the availability of accurate current samples as specified above in conjunction with the weights of Figure 9, the phase selected for sampling is also based on the minimum sampling period between samples. For example, as shown in Figure 9, when the "minimum period" parameter is 0, the queuing system 810 selects phase 2 for sampling in both periods 3 and 4. However, if the "minimum period" parameter is 1, then the queuing system 810 selects phase 2 for sampling in period 3, but does not select phase 2 in the immediately following period 4, but instead selects phase 3.

11 is a flowchart illustrating an exemplary prioritized current sampling method according to an embodiment.

In block 1102, the queuing system (eg, 810) identifies prioritization parameters for current sampling between phases, such as the configuration of time slots in the PWM waveform, and associated weights. As mentioned above, parameters may also include the maximum delay between samples, the minimum sampling period, etc. In block 1104, processing is then performed on a sample-by-sample basis for each sampling period of a single ADC (eg, ADC 812). For example, in block 1106, the queuing system 810 receives PWM waveform information for each phase at a given time (eg, from the loop/modulator 806). Using the PWM waveform information and priority parameters (eg, as described in connection with FIG. 9 ), the queuing system 810 determines the phase that currently has the highest weight in block 1108 . In some embodiments, the highest weight is the only one that needs to be decided. However, in block 1110, it is decided whether other standards should also be used. If so, then in block 1112, other priority parameters are used to decide whether a different phase should be selected for sampling other than the phase with the highest weight. As mentioned above, the other parameters may include the maximum delay between samples, the minimum sampling period, etc. Based on these other priority parameters, the phase with the highest weight is confirmed or replaced by a different phase. In either case, following block 1110, in block 1114, the actual sampling period of the selected phase is determined and used to adjust the ADC gain, if necessary. The ADC (eg, 812) is then directed to obtain inductor current samples from the selected phase (eg, via sending appropriate control signals to multiplexer 814). As mentioned previously, the inductor current samples (and identification of the sampled phases) can then be provided to other circuits, such as current synthesizers (eg, 808) and/or loop/modulators (eg, 806).

Although the embodiments of the present invention have been described in detail with reference to the preferred embodiments, it will be apparent to those skilled in the art that changes and modifications can be made in form and details without departing from the spirit and scope of the invention. The attached request is intended to cover such changes and modifications.

100: Buck regulator 132: Proportional-integral-derivative (PID) control filter 134: Pulse width modulator (PWM) 136:Output control circuit 138:Power transistor 140:Power transistor 142:Inductor 144:Capacitor 146: Error amplifier 152:Controller IC 153:Inductor 154:Output stage 155:Inductor 156:Output stage 160:Capacitor 162:Example load 172:Power FET 174:Power FET 176:Power FET 178:Power FET 280:Polyphase regulator 301:Power supply 305: Memory subsystem (or memory) 307: Peripheral equipment 310:System Integrated Circuits 312:Power control IC 314:Power control IC 401: System 402: System 403:System 502:PWM modulator output 504: Waveform 506: Waveform 508:Interval 510:interval 602: Waveform 604: Waveform 606:Precise part 702: Waveform 704: Waveform 706:Precise part 708: OK 710: OK 802:Digital part 804: Analogy part 806: Loop/Modulator 808:Current synthesizer 810: Sampling queuing system 812: Current Sensing Analog-to-Digital Converter (Isen ADC) 816:Output stage 818:Power station 902: Waveform 904: Waveform 1002:Waveform 1004:Exact part 1006:Table 1102: Square 1104:block 1106: Square 1108:block 1110: Square 1112: Square 1114:block 1116: Square

These and other aspects and features of the present invention will become apparent to those of ordinary skill in the art upon reading the following description of specific embodiments in conjunction with the accompanying drawings, in which:

Figure 1 is an example system block diagram of a controller according to an embodiment;

Figure 2 is a block diagram illustrating an example implementation of a controller such as that shown in Figure 1;

Figure 3 is a block diagram illustrating an example system having a power supply including a controller such as that shown in Figure 1;

Figure 4 illustrates an example computing system including a power supply such as that shown in Figure 3;

Figure 5 provides waveform diagrams illustrating various aspects of inductor current sampling in the controller;

6 provides waveform diagrams illustrating aspects of a shared inductor current sampling technique in accordance with embodiments;

7 provides waveform diagrams illustrating aspects of an exemplary prioritized inductor current sampling technique in accordance with an embodiment;

8 is a block diagram illustrating an example controller that may implement embodiments of the invention;

9 is a timing diagram illustrating an example of how to implement a prioritized inductor current sampling technique in accordance with an embodiment;

10 provides waveform diagrams illustrating aspects of another exemplary prioritized inductor current sampling technique in accordance with an embodiment; and

FIG. 11 is a flowchart illustrating an exemplary method according to the present embodiment.

Domestic storage information (please note in order of storage institution, date and number) without

Overseas storage information (please note in order of storage country, institution, date, and number) without

100: Buck regulator

132: Proportional-integral-derivative (PID) control filter

134: Pulse width modulator (PWM)

136:Output control circuit

138:Power transistor

140:Power transistor

142:Inductor

144:Capacitor

146: Error amplifier

Claims (15)

An apparatus for sampling inductor current in a polyphase controller, comprising: an analog-to-digital converter configured to sample any of a plurality of different analog signals corresponding to a plurality of phases of the polyphase controller; a multiplexer that selectively causes the analog-to-digital converter to sample one of the plurality of analog signals based on a control signal; and A queuing system that generates the control signal at each of a plurality of sampling periods based on pulse width modulation (PWM) waveform information associated with the plurality of sampling periods. The device of claim 1 further includes configuration information, and the queuing system uses the configuration information to generate the control signal to set a priority for the one of the plurality of analog signals for each sampling period. The device of claim 2, wherein the configuration information includes specifying a plurality of time slots in the PWM waveform and a corresponding plurality of weights for the plurality of time slots, and the queuing system uses the plurality of weights and the PWM waveform information To set a priority for one of the plurality of analog signals for each sampling period. The device of claim 3, wherein the plurality of weights identify certain of the plurality of time slots in the PWM waveform during which current sensing information for a relevant phase is accurate. The device of claim 1, wherein each of the plurality of analog signals includes an inductor current sensing signal. An apparatus for sampling inductor current in a polyphase controller, comprising: an analog-to-digital converter configured to sample any of a plurality of different analog signals corresponding to a plurality of phases of the polyphase controller; a multiplexer that selectively causes the analog-to-digital converter to sample one of the plurality of analog signals based on a control signal; and A queuing system based on pulse width modulation (PWM) waveform information associated with the plurality of phases of each sampling period and a minimum sampling period specified for the plurality of phases, in each of the plurality of sampling periods. The control signal is generated at one location. The device of claim 6 further includes configuration information, and the queuing system uses the configuration information to generate the control signal to set a priority for the one of the plurality of analog signals for each sampling period. The device of claim 7, wherein the configuration information includes designations of a plurality of time slots in the PWM waveform and corresponding plurality of weights for the plurality of time slots, and the queuing system uses the plurality of weights and the PWM waveform Information is used to set a priority for one of the plurality of analog signals for each sampling period. The device of claim 8, wherein the plurality of weights identify certain of the plurality of time slots in the PWM waveform during which current sensing information for a relevant phase is accurate. The device of claim 6, wherein each of the plurality of analog signals includes an inductor current sensing signal. A method for sampling inductor current in a polyphase controller includes the following steps: Configuring an analog-to-digital converter to sample any one of a plurality of different analog signals respectively corresponding to a plurality of phases of the polyphase controller; selectively causing the analog-to-digital converter to sample one of the plurality of analog signals based on a control signal; and The control signal is generated at each of a plurality of sampling periods based on pulse width modulation (PWM) waveform information associated with the plurality of sampling periods. As in the method of claim 11, the step of generating the control signal further includes the following step: setting a priority for the one of the plurality of analog signals for each sampling period based on the configuration information. The method of claim 12, wherein the configuration information includes designations of a plurality of time slots in the PWM waveform and a corresponding plurality of weights for the plurality of time slots, wherein the step of generating the control signal includes the following steps: The plurality of weights and the PWM waveform information are used to set a priority for the one of the plurality of analog signals for each sampling period. The method of claim 13, wherein the plurality of weights identify certain of the plurality of time slots in the PWM waveform during which current sensing information for a relevant phase is accurate. The method of claim 11, wherein each of the plurality of analog signals includes an inductor current sensing signal.