TWI790051B - Linear regulator having fast sinking capability - Google Patents

Abstract

A linear regulator having fast sinking capability includes a power switch coupled between a high voltage source and an output voltage; a dynamic output determination circuit for receiving a reference signal and generate a current setting signal according to the reference signal; and a current replication and gate control circuit for generating a gate control signal according to the current setting signal, to generate a gate voltage at a gate of the power switch, so as to control a conduction state of the power switch, wherein the dynamic output determination circuit is coupled to the output voltage so that the output voltage is a positive power source of the dynamic output determination circuit, and so that the dynamic output determination circuit provides a current path from the output voltage to ground, as a fast sinking path of the output voltage, wherein a current amount of the current path is not limited by a current source.

Description

Linear regulator circuit with fast pressure relief capability

The invention relates to a linear voltage stabilizing circuit with fast pressure relief capability, which can quickly release pressure when the output node needs to drop from high voltage to low voltage.

FIG. 1 shows a prior art linear regulator circuit for converting an input voltage Vin to an output voltage Vout. The voltage divider circuit composed of resistors R1 and R2 obtains the feedback voltage related to the output voltage Vout, and the error amplifier EA compares the feedback voltage with the reference signal Vref to generate the gate voltage VG to control the power switch M to convert the input voltage Vin is converted to output voltage Vout. The disadvantage of this prior art is: when the output voltage Vout needs to drop from a high voltage to a low voltage, because the path from the output node OUT to the ground only passes through the resistors R1 and R2, the charge of the output node OUT is released very slowly, that is, the output voltage Vout The reaction rate from high pressure to low pressure is slow.

In response to this problem, Yan Lu et al. wrote in "A fully-integrated low-dropout regulator with full-spectrum power supply rejection", IEEE Trans. Circuits Syst. I, Reg. Papers , vol. 62, no. 3, pp. 707 -716, Mar. 2015, a circuit as shown in Figure 2 is proposed, in which a current source I2 is provided as an additional charge discharge path from the output node OUT to ground to accelerate the output voltage Vout from high voltage to low voltage reaction speed. However, this prior art is still not completely ideal, because the current source I2 limits the upper limit of the current amount, and when the operating range (headroom) of the current source I2 is insufficient, the current source I2 cannot work normally, and the path at this time will have a higher Impedance slows down the charge release.

Similarly, J. Guo and K. N. Leung in "A 6- chip-area-efficient output-capacitorless LDO in 90-nm CMOS technology," IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1896 In –1905, Sep. 2010, a capacitor-less circuit as shown in Figure 3 was proposed, which also provides an additional charge discharge path from the output node OUT to the ground GND, but the upper limit of the current amount of this path is limited by the current source IBIAS, therefore has the same problems as the previous technique in Fig. 2.

In order to solve the above problems, the present invention provides a linear voltage stabilizing circuit with fast pressure release capability, which can quickly release the voltage when the output voltage needs to drop from high voltage to low voltage, and the current amount of the pressure release path is not as high as that of the prior art. limit.

From one point of view, the present invention provides a linear voltage regulator circuit with rapid pressure relief capability, comprising: a power switch, coupled to a high voltage source and an output voltage, and controlling the high voltage according to the conduction state of the power switch The relationship between the source and the output voltage, so as to control the level of the output voltage; a dynamic output determination circuit, used to receive a reference signal, and convert according to the reference signal to generate a current setting signal; and a current replication and gate A gate control circuit generates a gate control current according to the current setting signal, thereby generating a gate voltage at the gate of the power switch to control the conduction state of the power switch; wherein, the dynamic output decision circuit and the output voltage coupling, the output voltage is used as a positive voltage source of the dynamic output determining circuit, and the dynamic output determining circuit provides a current path from the output voltage to ground as a fast discharge path of the output voltage, wherein the current path Not limited by the upper current limit of the current source.

In a preferred embodiment, the dynamic output determination circuit includes: a voltage-to-current circuit for converting the reference signal into a current signal; and a current replication circuit coupled to the voltage-to-current circuit for The current signal is copied to generate the current setting signal, wherein there is a proportional relationship between the current signal and the current setting signal.

In a preferred embodiment, the voltage-to-current circuit includes a transistor, the current inflow end of which is coupled to the output voltage, and the control end of which is coupled to the reference signal, so as to determine the voltage of the transistor according to the reference signal. The conduction state determines the level of the current signal.

In a preferred embodiment, the current duplication circuit includes a current mirror circuit for duplicating and generating the current setting signal according to the current signal, wherein the current mirror circuit uses the output voltage as its positive voltage.

In a preferred embodiment, the current mirror circuit includes a pair of transistors with a common gate, and the current duplication circuit further includes a bypass capacitor arranged between the common node of the gates of the pair of transistors and the output voltage between.

In a preferred embodiment, the current replication and gate control circuit includes a first current mirror circuit, which replicates and generates the gate control current according to the current setting signal.

In a preferred embodiment, the current replication and gate control circuit further includes a transistor, which forms a second current mirror circuit with the power switch, whereby the current of the transistor is multiplied by the current of the power switch or proportional relationship.

In a preferred embodiment, the linear voltage regulator circuit with rapid pressure release capability further includes a dynamic bias adjustment circuit coupled to the current replication and gate control circuit, wherein the dynamic bias adjustment circuit is based on an external input The signal is biased to adjust the gate control current, thereby adjusting the gate voltage.

In a preferred embodiment, the dynamic bias adjustment circuit includes: a current replica circuit, which generates a bias signal in the form of a current according to the external input signal, the bias signal and the current path of the gate control current connected to bias adjust the gate control current.

In a preferred embodiment, the current replication circuit includes a current mirror circuit for generating the bias signal in the form of a current according to the external input signal.

In a preferred embodiment, the current mirror circuit includes a pair of transistors with a common gate, and the current duplication circuit further includes a bypass capacitor arranged between the common node of the gates of the pair of transistors and the output voltage between.

In a preferred embodiment, the dynamic bias adjustment circuit further includes a first switch, which is used to turn on or cut off the connection between the dynamic bias adjustment circuit and the current replication and gate control circuit, and/or There is a second switch on the path of the current setting signal, which is used to turn on or cut off the connection between the current setting signal and the current replication and gate control circuit.

In a preferred embodiment, the linear regulator circuit with fast pressure release capability further includes a bypass path directly bypassing from the dynamic output determining circuit to the dynamic bias adjustment circuit, so as to directly bypass the dynamic output determining circuit from the dynamic output determining circuit. The bias signal generated by the dynamic bias adjustment circuit is adjusted.

In a preferred embodiment, the linear regulator circuit with fast pressure release capability further includes a reference signal setting circuit coupled to the dynamic output determining circuit to provide a channel for setting the reference signal.

In a preferred embodiment, the reference signal setting circuit includes: a first setting circuit, the first setting circuit includes a first current mirror circuit composed of a pair of PMOS transistors, the high voltage source is used as a positive voltage source, One of the lower ends of the first current mirror circuit receives a first setting current, and the other generates a first voltage source; a second setting circuit is coupled with the first setting circuit, and the second setting circuit includes a pair of PMOS A second current mirror circuit composed of transistors uses the first voltage source as a positive voltage source, one of the lower ends of the second current mirror circuit receives a second set current, and the other lower end generates the reference signal; and an adjustment circuit , coupled with the second setting circuit, used to adjust the parameters of the second setting circuit, and then adjust the reference signal generated by the second setting circuit, wherein the adjustment circuit includes a third pair of NMOS transistors A current mirror circuit, the first upper end of the third current mirror circuit receives a third setting current, and the first voltage source is connected to the third current mirror circuit through an adjustment transistor and at least one diode connected in series The upper end of the second path is coupled, and the upper end of the third path of the third current mirror circuit is coupled with the reference signal, thereby, the gate voltage of the adjustment transistor can be obtained from the diode below one of the voltage, and/or set or adjust the reference signal by selecting the first, second, and third set currents.

In the following detailed description by means of specific embodiments, it will be easier to understand the purpose, technical content, characteristics and effects of the present invention.

The drawings in the present invention are all schematic, and are mainly intended to show the relationship between various circuit components, and the shapes and sizes are not drawn to scale.

Figure 4 shows an embodiment of the present invention. Please refer to Fig. 4, the linear voltage stabilizing circuit 40 of the present invention with rapid pressure relief capability is used to provide the output voltage Vdd to the load 100, the linear voltage stabilizing circuit 40 includes: a power switch 41, a dynamic output determining circuit 42, a current replica and gate control circuit 43. The power switch 41 is coupled between the high voltage source HV and the output voltage Vdd, and controls the relationship between the high voltage source HV and the output voltage Vdd, that is, the level of the output voltage Vdd according to the conduction state of the power switch 41 . The dynamic output determining circuit 42 receives the reference signal Vref, converts and generates the current setting signal Iset according to the reference signal Vref. The current replication and gate control circuit 43 generates a gate control current Ig according to the current setting signal Iset. The charge provided by the gate control current Ig is accumulated in the gate of the power switch 41 by using the parasitic capacitance of the power switch 41 itself. The gate voltage Vg is used to control the conduction state of the power switch 41 . In addition, the dynamic output determining circuit 42 is coupled to the output voltage Vdd. On the one hand, the output voltage Vdd is used as a positive voltage source of the dynamic output determining circuit 42. On the other hand, the dynamic output determining circuit 42 provides a current path from the output voltage Vdd to ground. , as a fast relief path for the output voltage Vdd. That is to say, the dynamic output determining circuit 42 converts and generates the current setting signal Iset according to the reference signal Vref on the one hand, so as to determine the gate control current Ig, and further determine the conduction state of the power switch 41, which also determines the output voltage Vdd; On the other hand, when the output voltage Vdd needs to be stepped down, the output voltage Vdd can be released through the dynamic output determination circuit 42 . The current replication and gate control circuit 43 can be used as its positive voltage source, such as but not limited to a high voltage source HV (other sufficiently high voltage sources can also be used).

In the above-mentioned circuit, firstly, it does not use the resistance voltage divider to generate the output voltage through feedback control as in the prior art in Fig. 1, therefore, it saves the energy consumed in the resistance voltage divider path; The current path from the voltage Vdd to the ground is used as a fast release path for the output voltage Vdd, and this current path is not limited by the current upper limit of the current source as in the prior art in Figures 2 and 3, so it is superior to the prior art. In addition, it is worth noting that because the output voltage Vdd generated by the circuit in this case is very stable, it is not necessary to set the output capacitor Cout at the output end as in the prior art in Figure 1, because the impedance of the ground seen from the output voltage Vdd It is lowered by the dynamic output decision circuit, therefore, the pole of the output voltage Vdd can be easily pushed to high frequency, so it is very stable in the application without output capacitor Cout. But if you want to set the output capacitor Cout, of course it is also possible.

FIG. 5 shows an embodiment of the dynamic output determination circuit 42 . Please refer to FIG. 5 , in this embodiment, the dynamic output determination circuit 42 includes a voltage-to-current circuit 421 and a current replication circuit 422 . The voltage-to-current circuit 421 converts the reference signal Vref into a current signal Iref; the current duplication circuit 422 is coupled to the voltage-to-current circuit 421, and generates a current setting signal Iset according to the current signal Iref, wherein the current signal Iref and the current setting signal Iset can be set to the desired proportional relationship.

FIG. 6 shows a more specific embodiment of the dynamic output determination circuit 42 . Please refer to FIG. 6 , in this embodiment, the voltage-to-current circuit 421 may be a transistor, the current input terminal thereof is coupled to the output voltage Vdd, and the control terminal thereof is coupled to the reference signal Vref. According to the reference signal Vref, the conduction state of the transistor is determined, that is, the level of the current signal Iref is determined. The current duplication circuit 422 can be a current mirror circuit, which duplicates and generates the current setting signal Iset according to the current signal Iref. In a preferred implementation, please refer to the figure, in addition to the current mirror circuit, a bypass capacitor Cbyp can also be provided between the output voltage Vdd and the gate common node N1 of the transistor pair of the current mirror circuit. The function of the bypass capacitor Cbyp is to couple the high frequency signal from the output voltage Vdd to the node N1.

It can be seen from Figure 6 that when the output voltage Vdd needs to be stepped down, the charge can be quickly discharged from the output voltage Vdd through the current mirror circuit, and there is no upper limit of the current, so the response speed is much faster than the previous technology. When there is an overshoot of the output voltage Vdd, the discharge capacity of the dynamic output determining circuit 42 can reach several times of the quiescent current in a steady state, and there is no upper limit as long as the components are tolerant.

Two embodiments of the current replication and gate control circuit 43 are shown in FIGS. 7A and 7B. Please refer to FIG. 7A. In this embodiment, the current replication and gate control circuit 43 includes a current mirror circuit, which replicates and generates the gate control current Ig according to the current setting signal Iset. Please refer to FIG. 7B. In this embodiment, in addition to using a current mirror circuit to replicate and generate the gate control current Ig according to the current setting signal Iset, the current replication and gate control circuit 43 further includes a transistor 411 and a power switch 41. Constitute another set of current mirror circuits, whereby the current of the transistor 411 and the current of the power switch 41 can have a multiple (or ratio) effect, increase the controllable parameters of the circuit, and make the operation of the power switch 41 more stable .

FIG. 8 shows another embodiment of the linear regulator circuit with rapid pressure release capability of the present invention. This embodiment is similar to the embodiment shown in FIG. 4 , but the difference lies in that the linear regulator circuit 40 with rapid pressure release capability in this embodiment further includes a dynamic bias adjustment circuit 44 . The dynamic bias adjustment circuit 44 and the current replication are coupled with the gate control circuit 43. The function of the dynamic bias adjustment circuit 44 is to bias and adjust the gate control current Ig (thus adjusting The gate voltage Vg), so that the response speed of the circuit can be accelerated by external control, or the internal setting of the original circuit can be adjusted. The above-mentioned external input signal, for example but not limited to, can be a bias signal Ibias (in this embodiment, it is a signal in the form of current, but of course it can also be a signal in the form of voltage, and then converted into a signal in the form of current inside the circuit).

A more specific embodiment of the dynamic bias adjustment circuit 44 is shown in FIG. 9 . Please refer to FIG. 9. In this embodiment, the dynamic bias adjustment circuit 44 includes a switch SW1 and a current replica circuit 441. The current replica circuit 441 generates a bias signal Ibias1 in the form of a current by replicating the bias signal Ibias. The bias signal Ibias1 It is connected with the current path of the gate control current Ig to adjust the gate control current Ig with bias. The function of the switch SW1 is to cut off the connection between the dynamic bias adjustment circuit 44 and the current replication and gate control circuit 43 when the bias adjustment is not needed.

In the case where the dynamic bias adjustment circuit 44 is set, in one of the implementations, as shown in the figure, a switch SW2 can also be set on the path of the current setting signal Iset, so that only the dynamic output can be selected to determine One of the circuit 42 and the dynamic bias adjustment circuit 44 is used to determine the gate control current Ig, or of course both can work together to determine the gate control current Ig. It should be noted that both the switches SW1 and SW2 can be omitted.

FIG. 10 shows a more specific embodiment of the current replication circuit 441 . Please refer to FIG. 10. In this embodiment, the current duplication circuit 441 includes a current mirror circuit, which generates a bias signal Ibias1 in the form of a current by duplicating the bias signal Ibias; in the current duplication circuit 441, Vs can be any suitable voltage source. In a preferred embodiment, please refer to the figure, in addition to the current mirror circuit, a bypass capacitor Cvd can also be set between the output voltage Vdd and the gate common node N2 of the transistor pair of the current mirror circuit, bypassing The function of the pass capacitor Cvd is to couple the high frequency signal from the output voltage Vdd to the node N2.

FIG. 11 shows another embodiment of the linear regulator circuit with rapid pressure release capability of the present invention. This embodiment is similar to the embodiment in FIG. 8 , but the difference lies in that in this embodiment, a bypass path P1 directly bypassing from the dynamic output determining circuit 42 to the dynamic bias adjustment circuit 44 is set. The function of the bypass path P1 is to directly adjust the bias signal Ibias1 generated by the dynamic bias adjustment circuit 44 from the dynamic output determination circuit 42 . For a detailed circuit embodiment, for example, please refer to FIG. 12, the node N1 of the dynamic output determination circuit 42 is directly bypassed to the gate of the transistor Q of the dynamic bias adjustment circuit 44, and therefore, flows through the transistor Q The current will have a proportional relationship with the current signal Iref, so that the bias signal Ibias1 generated by the dynamic bias adjustment circuit 44 can be directly adjusted from the dynamic output determination circuit 42 . In addition, another function of the bypass path P1 is to adjust the pole and zero of the circuit.

Figures 13-14 show another two embodiments of the linear voltage regulator circuit with rapid pressure release capability of the present invention. These two embodiments are similar to the embodiments in Fig. 4 and Fig. 8 respectively, but the difference is that a reference signal setting circuit 45 is added. The reference signal setting circuit 45 is coupled to the dynamic output determining circuit 42 to provide a channel for setting the reference signal Vref from the outside.

FIG. 15 shows an embodiment of the reference signal setting circuit 45 . In this embodiment, the reference signal setting circuit 45 includes a first setting circuit 451 , a second setting circuit 452 , and an adjustment circuit 453 . The first setting circuit 451 generates a voltage source V1 according to a suitable voltage source (such as but not limited to a high voltage source HV, other voltage sources can also be used); the second setting circuit 452 is coupled to the first setting circuit 451, and generates The reference signal Vref; the adjusting circuit 453 is coupled to the second setting circuit 452 for adjusting the parameters of the second setting circuit 452 , and then adjusting the reference signal Vref generated by the second setting circuit 452 .

FIG. 16 shows a more specific embodiment of the reference signal setting circuit 45 . Please refer to FIG. 16. In this embodiment, the first setting circuit 451 includes a current mirror circuit composed of a pair of PMOS transistors. The high voltage source HV is used as a positive voltage source. One of the lower ends of the current mirror circuit receives the setting current I11. The lower end of the other path is coupled to a Zener diode Z, and the upper end of the Zener diode Z generates a voltage source V1. The second setting circuit 452 includes a current mirror circuit composed of a pair of PMOS transistors. The voltage source V1 is used as a positive voltage source. One of the lower ends of the current mirror circuit receives the setting current I12, and the other lower end generates the reference signal Vref.

The adjustment circuit 453 is coupled to the second setting circuit 452. The adjustment circuit 453 includes a current mirror circuit composed of multiple pairs of NMOS transistors. The upper end of the first circuit of the current mirror circuit receives the setting current I13, and the voltage source V1 is connected via the transistors connected in series. Pref and several diodes D1-D4 (the four shown in this embodiment are just for example, the number of diodes can be changed) are coupled to the upper end of the second path, and the upper end of the third path is coupled to the reference signal Vref. The voltage below the diode from which the gate voltage Vgr of the TV transistor Pref is obtained can determine the conduction state of the transistor Pref, thereby adjusting the reference signal Vref. In addition, in the reference signal setting circuit 45 , the setting currents I11 , I12 , and I13 can all be used to adjust the reference signal Vref.

In the circuit of the above embodiment, the transistor Pref and the diodes D1 - D4 in the adjustment circuit 453 can be used to compensate the impedance of the first setting circuit 451 and the temperature coefficient of the voltage-to-current circuit 421 . On the other hand, when the high voltage source HV is much larger than the voltage source V1, the transistor Pref will be turned on; when the high voltage source HV is close to the voltage source V1, the loop of the adjustment circuit 453 will turn off (non-conductive) the transistor Pref, at this time the reference signal Vref will be pulled up to the voltage source V1. The above function is to make the output of the linear voltage stabilizing circuit as close as possible to the level of the high voltage source HV when the linear voltage stabilizing circuit operates under the lower level high voltage source HV.

The present invention has been described above with reference to preferred embodiments, but the above description is only for making those skilled in the art easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Within the same spirit of the present invention, various equivalent changes can be conceived by those skilled in the art. The content shown in each embodiment can be combined with each other. In addition, between the two components or circuits that are directly connected as shown in the circuit diagram of the embodiment, components or circuits that do not affect the main function of the overall circuit can be inserted between them, such as switches, buffers, resistors, etc.; therefore, the term "coupled" in the present invention "Include direct connection and indirect connection. The scope of the present invention shall cover the above and all other equivalent variations.

40: Linear voltage regulator circuit (linear voltage regulator circuit with fast pressure relief capability) 41: Power switch 42: Dynamic output decision circuit 421: Voltage to current circuit 422: Current replication circuit 43: Current replication and gate control circuit 44: Dynamic bias adjustment circuit 441: Current replication circuit 45: Reference signal setting circuit 451: The first setting circuit 452: The second setting circuit 453: Adjustment circuit 100: load Cbyp, Cvd: bypass capacitance Cout: output capacitance D1-D4: Diodes EA: error amplifier GND: ground HV: High voltage source I11, I12, I13: set current I2, IBIAS: current source Ibias, Ibias1: bias signal Ig: gate control current Iref: current signal Iset: current setting signal M: power switch N1, N2: gate common node OUT: output node P1: bypass path Pref, Q: Transistor R1, R2: Resistors SW1, SW2: switch V1, Vs: voltage source Vdd, Vout: output voltage Vg, VG, Vgr: gate voltage Vin: input voltage Vref, VREF: reference signal Z: Zener diode

Figures 1-3 show prior art linear regulator circuits. FIG. 4 shows an embodiment of the linear voltage regulator circuit with rapid pressure release capability of the present invention. Figure 5 shows an embodiment of the dynamic output determination circuit. Fig. 6 shows a more specific embodiment of the dynamic output determination circuit. Figures 7A and 7B show two embodiments of current replication and gate control circuits. FIG. 8 shows another embodiment of the linear regulator circuit with rapid pressure release capability of the present invention. Fig. 9 shows a more specific embodiment of the dynamic bias adjustment circuit. Figure 10 shows a more specific embodiment of the current replication circuit. FIG. 11 shows another embodiment of the linear regulator circuit with rapid pressure release capability of the present invention. FIG. 12 shows a specific embodiment of the present invention, in which a bypass path P1 directly bypassing from the dynamic output determining circuit to the dynamic bias adjusting circuit is provided. Figures 13-14 show another two embodiments of the linear regulator circuit with rapid pressure release capability of the present invention. FIG. 15 shows an embodiment of the reference signal setting circuit. FIG. 16 shows a more specific embodiment of the reference signal setting circuit. please

40: Linear voltage regulator circuit (linear voltage regulator circuit with fast pressure relief capability)

41: Power switch

42: Dynamic output decision circuit

43: Current replication and gate control circuit

100: load

HV: High voltage source

Ig: gate control current

Iset: current setting signal

Vdd: output voltage

Vref: reference signal

Claims (15)

A linear voltage stabilizing circuit with rapid pressure relief capability, comprising: a power switch coupled between a high voltage source and an output voltage, and controlling the voltage between the high voltage source and the output voltage according to the conduction state of the power switch Relationship, so as to control the level of the output voltage; a dynamic output determination circuit, used to receive a reference signal, and convert and generate a current setting signal according to the reference signal; and a current replication and gate control circuit, according to the current setting signal to generate a gate control current, thereby generating a gate voltage at the gate of the power switch to control the conduction state of the power switch; wherein, the dynamic output determining circuit is coupled to the output voltage, and the output voltage is used as The dynamic output determines the source of the positive voltage for the circuit, and the dynamic output determines the circuit provides a current path from the output voltage to ground as a fast relief path for the output voltage, wherein the current path is not limited by the current of the current source upper limit. The linear voltage stabilizing circuit with rapid pressure relief capability as described in Claim 1, wherein the dynamic output determination circuit includes: a voltage-to-current circuit for converting the reference signal into a current signal; and a current replica circuit, Coupled with the voltage-to-current circuit, the current setting signal is duplicated and generated according to the current signal, wherein the current signal and the current setting signal have a proportional relationship. The linear regulator circuit with rapid pressure release capability as described in claim 2, wherein the voltage-to-current circuit includes a transistor, the current inflow end of which is coupled to the output voltage, and its control The terminal is coupled to the reference signal, so as to determine the conduction state of the transistor according to the reference signal, thereby determining the level of the current signal. The linear voltage regulator circuit with rapid pressure release capability as described in claim 2, wherein the current replica circuit includes a current mirror circuit, which is used to replicate and generate the current setting signal according to the current signal, wherein the current mirror circuit uses the current mirror circuit The output voltage is its positive voltage. The linear voltage stabilizing circuit with rapid pressure release capability as described in claim item 4, wherein the current mirror circuit includes a pair of transistors with a common gate, and the current replica circuit also includes a bypass capacitor, which is arranged on the pair of common gates Between the gate common node of the transistors of the pole and this output voltage. The linear voltage stabilizing circuit with rapid pressure release capability as described in Claim 1, wherein the current replication and gate control circuit includes a first current mirror circuit, which replicates and generates the gate control current according to the current setting signal. The linear regulator circuit with rapid pressure release capability as described in claim 6, wherein the current replication and gate control circuit further includes a transistor, which forms a second current mirror circuit with the power switch, thereby enabling the electric current The current of the crystal is multiplied or proportional to the current of the power switch. The linear voltage stabilizing circuit with rapid pressure release capability as described in claim 1 further includes a dynamic bias adjustment circuit coupled to the current replication and gate control circuit, wherein the dynamic bias adjustment circuit is based on an external input The bias signal adjusts the gate control current, thereby adjusting the gate voltage. The linear regulator circuit with fast pressure release capability as described in claim 8, wherein the dynamic bias adjustment circuit includes: a current replica circuit, which generates a bias signal in the form of a current according to the external input signal, and the bias signal The setting signal is connected to the current path of the gate control current to adjust the gate control current by bias. The linear voltage stabilizing circuit with rapid pressure release capability as claimed in item 9, wherein the current duplication circuit includes a current mirror circuit for generating the bias signal in the form of a current according to the external input signal. The linear voltage stabilizing circuit with rapid pressure release capability as described in claim item 10, wherein the current mirror circuit includes a pair of transistors with a common gate, and the current duplication circuit also includes a bypass capacitor, which is arranged on the pair of common gates Between the gate common node of the transistors of the pole and this output voltage. The linear voltage regulator circuit with rapid pressure release capability as described in Claim 9, wherein the dynamic bias adjustment circuit further includes a first switch, which is used to turn on or cut off the dynamic bias adjustment circuit and the current replication and gate and/or a second switch on the path of the current setting signal for turning on or cutting off the current setting signal and the connection between the current replica and the gate control circuit. The linear regulator circuit with rapid pressure relief capability as described in claim 8 further includes a bypass path directly bypassing from the dynamic output determining circuit to the dynamic bias adjustment circuit, so as to directly adjust from the dynamic output determining circuit The bias signal generated by the dynamic bias adjustment circuit. The linear voltage stabilizing circuit with rapid pressure relief capability as described in Claim 1 further includes a reference signal setting circuit coupled to the dynamic output determining circuit to provide a channel for setting the reference signal. The linear regulator circuit with rapid pressure release capability as described in claim 14, wherein the reference signal setting circuit includes: a first setting circuit, the first setting circuit includes a first current mirror composed of a pair of PMOS transistors The circuit uses the high voltage source as a positive voltage source, one of the lower ends of the first current mirror circuit receives a first setting current, and the other generates a first voltage source; a second setting circuit is coupled to the first setting circuit , the second setting circuit includes a second current mirror circuit composed of a pair of PMOS transistors, using the first voltage source as a positive voltage source, the One of the lower ends of the second current mirror circuit receives a second setting current, and the other lower end generates the reference signal; and an adjustment circuit, coupled with the second setting circuit, is used to adjust the parameters of the second setting circuit, and then adjusting the reference signal generated by the second setting circuit, wherein the adjusting circuit includes a third current mirror circuit composed of multiple pairs of NMOS transistors, the first upper end of the third current mirror circuit receives a third setting current, The first voltage source is coupled to the upper end of the second path of the third current mirror circuit through a series adjustment transistor and at least one diode, and the third upper end of the third current mirror circuit is connected to the reference signal coupling whereby the gate voltage of the adjustment transistor can be set by taking the voltage below one of the diodes and/or by selecting the first, second, third set current Or adjust the reference signal.

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