TWI780882B - Light emitting diode display device and method for driving the same - Google Patents

Abstract

A light emitting diode （LED） display device and method for driving the same are provided. The LED display device includes a plurality of pixel circuits disposed as display rows, a clock controller and a signal generator. The clock controller is configured to provide a first control signal and a second control signal according to display data. The signal generator is configured to receive the first control signal and the second control signal, and is configured to generate a modulating signal to one of the display rows according to the first control signal and the second control signal. Within a frame period, the modulating signal has a plurality of pulses for driving the emitting devices of the display rows many times.

Description

Light-emitting diode display device and driving method thereof

The present invention relates to a display device and its driving method, in particular to a light emitting diode display device and its driving method.

Different driving methods can be applied to various display devices, wherein the driving methods include, for example, pulse-amplitude modulation (PAM) and pulse-width modulation (PWM). The PWM driving method can drive active light-emitting diodes by adjusting the pulse width of the driving signal. However, when displaying low-gray-scale images, the pulse width of the corresponding driving signal is narrow due to the short light-emitting time required, thereby resulting in a low duty cycle. Therefore, the display device has the problems of low display uniformity and screen flicker when displaying low-grayscale images.

The invention provides a light-emitting diode display device, which can reduce the duty ratio of a driving signal, so as to reduce screen flicker and improve display uniformity.

The LED display device of the present invention includes a plurality of pixel circuits, a timing controller and a signal generator. A plurality of pixel circuits form a display column. The timing controller is used for providing the first control signal and the second control signal according to the display data. The signal generator is used for receiving the first control signal and the second control signal, and is used for generating modulation signals to the display bar according to the first control signal and the second control signal. The modulation signal has multiple pulses in the image frame period to drive multiple light emitting elements in the display row.

The invention further provides a driving method of the light emitting diode display device. This driving method includes the following operations: providing the first control signal and the second control signal according to the display data; generating and providing the modulation signal to the display bar according to the first control signal and the second control signal, wherein the modulation signal is shown in Fig. There are a plurality of pulse waves in the image frame period; and in the image frame period, a plurality of light-emitting elements in the display column are driven multiple times.

Based on the above, the light-emitting diode display device of the present invention can use the modulation signal generated by the control signal to drive the display row, wherein the modulation signal has multiple pulses in the image frame period. Therefore, in one image frame period, multiple light-emitting elements in the display column can be driven multiple times to reduce screen flicker and improve display uniformity.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

100: Light-emitting diode display device

110: Timing controller

120: Signal generator

130: Pixel circuit

131: Display columns

132: Display line

140: scan driver

150:Data drive

310: timing controller

311: the first control signal circuit

312: The second control signal circuit

3121: pulse generator

3122, 3123: gate control circuit

320: signal generator

321: Ramp wave circuit

322, 323: voltage level displacement circuit

3211: logic circuit

3212: integrating circuit

500: pixel circuit

510: switch

520: modulation circuit

530: drive circuit

S310~S350: Steps

S610~S630: steps

A1, A2, A3: pulse wave

C1, C2: capacitance

CK: clock signal

CP: comparator circuit

D1: Diode

DI: Jitter Information

dt: time difference

dV: voltage difference

EM: enable signal

FT, FT1, FT2, FTn: image frame period

LED: light emitting diode

OP: operational amplifier

P1: Timing

R1: resistance

SW1, SW2: switch

T1, T2, T3: enabling time

Vdata, Vdata1, Vdata2: data signal

VDD: Voltage

Vg, Vg1, Vg2: drive signal

VH, VL: control signal

Vscan: scan signal

VSS: Voltage

Vsweep, Vsweep1, Vsweep1: modulation signal

Vt: control signal

FIG. 1 is a schematic diagram of a light emitting diode display device according to an embodiment of the present invention.

FIG. 2 is a timing diagram of the driving signal generation method of the LED display device according to the embodiment of FIG. 1 of the present invention.

FIG. 3 is a schematic diagram of an implementation of a timing controller and a signal generator in a light-emitting diode display device according to an embodiment of the present invention.

FIG. 4 is a timing diagram of multiple signals according to the embodiment of FIG. 3 of the present invention.

FIG. 5 is a schematic diagram of a pixel circuit according to an embodiment of the invention.

FIG. 6 is a flowchart of a driving method of a light emitting diode display device according to an embodiment of the present invention.

FIG. 1 is a schematic diagram of a light emitting diode display device according to an embodiment of the present invention, please refer to FIG. 1 . The light-emitting diode display device 100 includes a timing controller 110, a signal generator 120, a plurality of pixel circuits 130, a scan driver 140 and a data driver 150, wherein the pixel circuits 130 are arranged in an array to form a plurality of display rows 131 and A plurality of display rows 132 .

In this embodiment, the timing controller 110 is coupled to the signal generator 120 , the scan driver 140 and the data driver 150 . The timing controller 110 can provide control signals VL and VH to the signal generator 120 according to the display data, and can provide other control signals (not shown) to the scan driver 140 and the data driver 150 to control the signal generator 120 and the scan driver 140 respectively. and a data driver 150 . The signal generator 120 is coupled to each display row 131 . The signal generator 120 can receive the control signals VL, VH, and can generate a plurality of modulation signals Vsweep according to the control signals VL, VH. The modulation signal Vsweep is sent to the corresponding display columns 131 to modulate the driving signal for driving the pixel circuit 130 .

The modulation signal Vsweep has a plurality of pulses in the image frame period, so that the driving signal generated by the modulation signal Vsweep can drive the plurality of light emitting elements in the corresponding display row 131 multiple times in the image frame period.

The scan driver 140 is coupled to each display row 131 , and can provide a plurality of scan signals Vscan to each corresponding display row 131 to select the display row 131 to be driven. The data driver 150 is coupled to each display row 132 , and can provide a plurality of data signals Vdata to each corresponding display row 132 to modulate in coordination with the modulation signal Vsweep corresponding to each display row 131 to generate a driving signal.

FIG. 2 is a timing diagram of the driving signal generation method of the light emitting diode display device 100 in the embodiment of FIG. 1 . Wherein, in the example (A), in a frame period FT, the pixel circuit 130 can compare the modulation signal Vsweep1 and the data signal Vdata1 to generate the driving signal Vg1. Wherein, the modulation signal Vsweep1 can be a ramp signal, and the data signal Vdata1 is a DC signal. When the voltage of the modulating signal Vsweep1 is greater than the data signal Vdata1, the pixel circuit 130 can make the driving signal Vg1 an enabled state (with a higher voltage value). When the voltage of the modulating signal Vsweep1 is not greater than the data signal Vdata1, the pixel circuit 130 can make the driving signal Vg1 in a disabled state (with a lower voltage value). Therefore, the driving signal Vg1 modulated according to the modulation signal Vsweep1 and the data signal Vdata1 can be a square wave signal.

In the example (B), the generation mechanism of the drive signal Vg2 is the same as that of the example (A) , the generation mechanism of the driving signal Vg1 is similar, and will not be repeated here. It should be noted that the frequency of the modulation signal Vsweep2 is higher than the frequency of the modulation signal Vsweep1. That is to say, in a single image frame period FT, the pulse number of the modulation signal Vsweep2 is more than that of the modulation signal Vsweep1.

In the examples (A) and (B), the modulation signals Vsweep1, Vsweep2 and the driving signals Vg1, Vg2 in one image frame period FT respectively have a plurality of pulses, wherein the number of pulses is related to the corresponding display column 131 The grayscale value of the displayed data. Since the grayscale value of the display row 131 used in the example (A) and the example (B) is different, the corresponding modulation signals Vsweep1, Vsweep2 and driving signals Vg1, Vg2 in the examples (A) and (B) have different numbers. pulse wave.

In the image frame period FT, the modulation signal Vsweep1 and the driving signal Vg1 respectively have corresponding four pulses, wherein each pulse occupies 1/4 of the image frame period FT (1/4 FT).

In addition, in the image frame period FT, the amplitude of one pulse A1 of the modulation signal Vsweep1 is different from the amplitudes of other pulses (indicated by dashed lines). Since the modulation signal Vsweep1 is a ramp wave in this embodiment, the maximum amplitude value of the pulse wave of the modulation signal Vsweep1 can also be called a peak value. In this embodiment, the peak value of the pulse wave A1 of the modulation signal Vsweep1 is higher than the peak values of other pulse waves. Under this configuration, the enabling time T1 of the pulse corresponding to the pulse A1 in the driving signal Vg1 is longer than that of other pulses.

In this way, by configuring the modulation signal Vsweep1 to have multiple pulses in one image frame period FT, the drive signal Vg1 can be configured in one image frame period FT The pixel circuit 130 is enabled multiple times to emit light multiple times. Therefore, the duty cycle of the driving signal can be reduced to reduce screen flickering. In addition, by adjusting the pulse wave of the modulation signal Vsweep1 to have different peak values, the driving signal Vg1 can enable the pixel circuit 130 at different working times to have a variable display effect. Accordingly, the color depth can be increased, and the display uniformity can be greatly improved when displaying low grayscale images.

Compared with the example (A), in the example (B), in the image frame period FT, the modulation signal Vsweep2 and the driving signal Vg2 respectively have corresponding eight pulses, wherein each pulse occupies 1/8 Image frame period FT(1/8 FT).

In addition, in the image frame period FT, the amplitudes of the pulse waves A2 and A3 of the modulation signal Vsweep2 are different from those of other pulse waves (indicated by dotted lines), and the amplitude of the pulse wave A2 can be the same as the amplitude of the pulse wave A3 or not the same. In this embodiment, the peak values of the pulse waves A2 and A3 of the modulation signal Vsweep2 are both higher than the peak values of other pulse waves. Under this configuration, the enabling times T2 and T3 of the pulses corresponding to the pulses A2 and A3 in the driving signal Vg2 are longer than the enabling times of other pulses.

FIG. 3 is a schematic diagram of an implementation of a timing controller and a signal generator in a light emitting diode display device according to an embodiment of the present invention. FIG. 4 is a timing diagram of multiple signals according to the embodiment of FIG. 3 of the present invention, wherein the frame periods FT1 , FT2 and FTn are consecutive frame periods.

Please refer to FIG. 3 and FIG. 4 , the timing controller 310 includes a first control signal circuit 311 and a second control signal circuit 312 . The first control signal circuit 311 is coupled to the second control signal circuit 312 . The first control signal circuit 311 can generate dithering information DI according to the received display data. The second control signal circuit 312 can The clock signal CK is generated, and the clock signal CK can be processed to generate the control signals VL and VH according to the jitter information DI.

The first control signal circuit 311 can be a digital circuit or a processor with computing capability. The first control signal circuit 311 can perform the following steps. First, the first control signal circuit 311 accumulates the grayscale values of the display data of the display bar 311 to generate an accumulated grayscale value (step S310 ). Next, the first control signal circuit 311 compares the accumulated gray scale value with the preset information to generate a matching result (step S320). The default information can be a look-up table, indicating that different accumulated gray scale values correspond to the parameters of the required modulation signal, wherein the parameters include: for example, the modulation signal Vsweep in Fig. The frequency and amplitude distribution of each pulse wave. Therefore, the information indicated by the matching result includes, for example, the frequency and amplitude distribution of the pulse wave required to modulate the signal Vsweep in the image frame period FT in FIG. 4 . Then, the first control signal circuit 311 determines the number of pulses according to the matching result (step S330). The number of pulse waves can be the number of pulse waves corresponding to the image frame period, for example, the image frame periods FT1 and FTn in FIG. 4 are 4 and 6 respectively.

Then, the first control signal circuit 311 can perform dither calculation on the display data of the display bar 311 (step S340 to step S350 ). The first control signal circuit 311 generates a scrambler sequence according to the number of pulses (step S340). The scrambling sequence indicates coded information of pulses of the signal, wherein the coded information includes, for example, a first number of pulses with a first amplitude, a second number of pulses with a second amplitude, and the timing of the aforementioned pulses. For example, in FIG. 4, the scrambling sequence indicates the number of pulses of the modulation signal Vsweep in each frame period FT1, FT2 and FTn Timing configuration. Next, the first control signal circuit 311 generates dithering information DI according to the scrambling sequence (step S350). The jitter information DI indicates the peak distribution of the pulse wave of the signal. For example, in FIG. 4 , the dithering information DI indicates the peak value and timing of the pulse wave of the modulation signal Vsweep in each frame period FT1 , FT2 and FTn.

In other embodiments, the first control signal circuit 311 can determine whether to perform dithering calculation according to the display data of the display bar 311 and the configuration of the light emitting elements (step S340 to step S350 ). For example, as shown in the image frame period FT1 in FIG. 4, if the accumulated grayscale value of the display data is 10 bits (bit), and the number of pulse waves is indicated as 4, each of the modulation signal Vsweep The pulse wave is represented as at least 2 bits. At this time, if the least significant bit (LSB) of the accumulated gray scale value has valid data, then according to the scrambling sequence and the dithering information DI, the least significant bit is assigned to the pulse wave of the modulation signal Vsweep at the time sequence P1, Make the peak value of this pulse wave higher than the peak value of other pulse waves. Therefore, the pulse wave of the modulation signal Vsweep at the timing P1 has more bits than others, so as to realize the gain of the color depth.

Returning to FIG. 3 , the second control signal circuit 312 includes a pulse generator 3121 and gate control circuits 3122 , 3123 . The pulse generator 3121 is coupled to the timing controller 310 and the gate control circuits 3122 and 3123 . The pulse generator 3121 can generate the clock signal CK according to the number of pulses. Therefore, as shown in FIG. 4 , the clock signal CK is a continuous pulse signal, and the clock signal CK has the number of pulses associated with the corresponding matching results in the frame periods FT1 , FT2 and FTn.

The gate control circuits 3122 and 3123 can be AND gates, and are coupled to the pulse generator 3121 . The gate control circuit 3122 can receive the clock signal CK and the jitter data News DI. The gate control circuit 3122 can pass the clock signal CK during the first enabling sequence and not pass the clock signal CK during the second enabling sequence according to the jitter information DI, so as to generate the control signal VH. For example, as shown in FIG. 4 , the first enabling timing period may be timing P1 , and the second enabling timing period may be other timings excluding timing P1 in the image frame period FT1 . The gate control circuit 3123 can receive the clock signal CK and the jitter information DI. The gate control circuit 3123 can pass the clock signal CK during the second enabling sequence period according to the jitter information DI, and not pass the clock signal CK during the first enabling sequence period, so as to generate the control signal VL. As shown in FIG. 4 , the first enabling timing period (timing P1 ) and the second enabling timing period do not overlap each other, so that the enabling periods of the control signals VH and VL are staggered from each other. Therefore, the pulses of the control signals VH, VL have different timing configurations.

In other embodiments, the gate control circuits 3122 and 3123 may also be other types of logic gates. The AND gate in this embodiment is just an example and is not intended to limit the scope of the present invention.

Returning to FIG. 3 , the signal generator 320 includes a ramp circuit 321 and voltage level shift circuits 322 , 323 . The voltage level shift circuit 322 is coupled between the gate control circuit 3122 and the ramp circuit 321 , and the voltage level shift circuit 323 is coupled between the gate control circuit 3123 and the ramp circuit 321 . The ramp circuit 321 is further coupled to the display column 131 .

The voltage level shift circuit 322 can receive the control signal VH, and can pull up the amplitude/peak value of the pulse wave of the control signal VH to a first voltage value. The voltage level shift circuit 323 can receive the control signal VL, and can reduce the amplitude/peak value of the pulse wave of the control signal VL to a second voltage value. In other words, the control signals VH and VL with different timings are adjusted to the peak values of the corresponding pulse waves by the voltage level shift circuits 322 and 323 respectively. And the first voltage value of the adjusted peak value is different from the second voltage value.

The ramp circuit 321 can receive the adjusted control signals VH, VL, and generate a modulation signal Vsweep according to the adjusted control signals VH, VL. In this embodiment, the ramp circuit 321 includes a logic circuit 3211 and an integrating circuit 3212 . The logic circuit 3211 is coupled to the integration circuit 3212 . The logic circuit 3211 is shown as an OR gate in FIG. 3 , and can superimpose the control signals VH and VL to generate the control signal Vt. The integrating circuit 3212 includes an operational amplifier OP, a resistor R1, a capacitor C1 and a diode D1, and can convert the waveform of the control signal Vt from a square wave to a ramp wave, and output a modulation signal Vsweep.

For example, as shown in FIG. 4 , in the image frame period FT1 , according to the number of pulses, the clock signal CK has corresponding 4 pulses. According to the jitter information DI, the timing configurations of the pulses of the control signals VH and VL are different and their enabling periods do not overlap each other. In addition, since the adjusted peak values of the control signals VH and VL have different voltage values, the multiple pulses of the control signal Vt have different voltage values. For example, in the image frame period FT1, the peak value of the pulse wave of the control signal Vt at the time sequence P1 is higher than the peak values of other pulse waves, and the difference is represented by a voltage difference dV. Therefore, the peak value of the pulse wave at the time sequence P1 of the modulated signal Vsweep generated by modulating the control signal Vt is higher than the peak values of other pulse waves.

FIG. 5 is a schematic diagram of a pixel circuit according to an embodiment of the present invention, please refer to FIG. 1 and FIG. 5 . The pixel circuit 500 can be another embodiment of the pixel circuit 130 in FIG. 1 . The pixel circuit 500 includes a switch 510 , a modulating circuit 520 and a driving circuit 530 . The switch 510 is coupled to the scan driver 140, the data driver 150 and Modulation circuit 520. The switch 510 can input the data signal Vdata to the modulation circuit 520 according to the scan signal Vscan from the scan driver 140 . The modulation circuit 520 includes a capacitor C2 and a comparator circuit CP, and is coupled to the signal generator 120 and the driving circuit 530 . The modulation circuit 520 can compare the modulation signal Vsweep from the signal generator 120 with the input data signal Vdata to generate the driving signal Vg. The driving circuit 530 includes a plurality of switches SW1, SW2 and LEDs, and can drive the LEDs to emit light according to the driving signal Vg and the enabling signal EM.

Referring back to FIG. 4 and FIG. 5 , in this embodiment, the modulating circuit 520 can modulate the data signal Vdata through the modulating signal Vsweep, so as to generate the driving signal Vg. For example, in the image frame period FT1, since the data signal Vdata is a constant voltage signal and the peak value of the pulse wave of the modulation signal Vsweep at the time sequence P1 is higher than others, the pulse wave of the driving signal Vg at the time sequence P1 The enabling period of the other is longer than that of the others, and the difference is represented by the time difference dt. Under this configuration, in one image frame period FT1, since the driving signal Vg has multiple pulses, the light-emitting diode LED can emit light multiple times to reduce flickering on the screen. In addition, in the image frame period FT1, since one of the pulses (or multiple pulses) of the driving signal Vg has a longer enabling period, the light-emitting diode LED can emit light for a longer time and increase color depth.

FIG. 6 is a flowchart of a driving method of a light emitting diode display device according to an embodiment of the present invention, please refer to FIG. 6 . The driving method may include the following steps. Firstly, a first control signal and a second control signal are provided according to the display data (step S610). The display data can be the gray scale value of the display data of the display bar 311 in FIG. 1, and the first control signal and the second control signal can be respectively the Control signals VH, VL. Next, according to the first control signal and the second control signal, a modulation signal is generated and provided to the display bar (step S620). The modulation signal has multiple pulses in one image frame period. The modulation signal can be the modulation signal Vsweep in FIG. 1 , FIG. 3 to FIG. 5 , or can be the modulation signal Vsweep1 or Vsweep2 in FIG. 2 . One picture frame period can be one of the picture frame periods FT1 to FTn in FIG. 4 or can be the picture frame period FT in FIG. 2 . Next, according to the driving signal modulated by the modulation signal, the plurality of light emitting elements in the display row are driven multiple times in the image frame period (step S630 ). The light emitting element can be the light emitting diode shown in FIG. 5 .

The implementation details of the above steps have been described in detail in the foregoing embodiments and multiple implementation manners, and will not be repeated here.

To sum up, the light-emitting diode display device and the driving method thereof of the embodiments of the present invention can generate modulation signals through the timing controller and the signal generator. The modulation signal has multiple pulses in one image frame period, so that the driving signal generated according to the modulation signal also has multiple pulses in the corresponding image frame period. In this way, in the image frame period, the light-emitting element can be driven multiple times to reduce screen flicker and improve display uniformity. In some embodiments, the modulated signal is generated according to the dithered signal, so in one image frame period, the modulated signal may have zero to multiple pulse peaks different from other pulse peaks, And the driving signal can be further made to have a corresponding pulse width. Accordingly, in the image frame period, more variable information can be displayed and the color depth can be increased.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Within the spirit and scope, some changes and modifications can be made, so the protection scope of the present invention should be defined by the scope of the appended patent application.

100: Light-emitting diode display device

110: Timing controller

120: Signal generator

130: Pixel circuit

131: Display columns

132: Display line

140: scan driver

150:Data drive

Vdata: data signal

Vscan: scan signal

Vsweep: modulation signal

VH, VL: control signal

Claims (10)

A light emitting diode display device, comprising: a plurality of pixel circuits forming at least one display row; a timing controller for providing a first control signal and a second control signal according to at least one display data; and a A signal generator, used to receive the first control signal and the second control signal, and to generate at least one modulation signal to the at least one display row according to the first control signal and the second control signal, wherein the at least A modulation signal has a plurality of pulses in an image frame period to drive multiple light emitting elements in the at least one display row, wherein in the image frame period: the at least one modulation signal The number of these pulse waves is related to the gray scale value of the at least one display data of the at least one display row, and the amplitude of at least one first pulse wave among the pulse waves of the at least one modulation signal is related to the pulse wave The amplitudes of the other at least one second pulse wave are different. The light-emitting diode display device as claimed in item 1, wherein the timing controller includes: a first control signal circuit for generating at least one jitter information according to the at least one display data of the at least one display row; and a second control signal circuit for generating a clock signal and processing the clock signal to generate the first control signal and the second control signal according to the at least one jitter information, The enabled periods of the first control signal and the second control signal do not overlap with each other. The light-emitting diode display device as described in claim 2, wherein the first control signal circuit is used to: accumulate the gray scale value of the at least one display data of the at least one display row to generate an accumulated gray scale value; Generate a matching result for the accumulated grayscale value and preset information; determine a pulse number according to the matching result; generate a scrambling sequence according to the pulse number; and generate the at least one scrambling sequence according to the scrambling sequence The dithering information is used to determine the peak distribution of the pulses of the at least one modulation signal. The light-emitting diode display device as described in claim 3, wherein the second control signal circuit includes: a pulse generator for generating the clock signal according to the number of pulses; a first gate control circuit, used to receive the clock signal and the at least one jitter information, and to generate the first control signal through the clock signal during a first enabling sequence according to the at least one jitter information; and a second gating A circuit for receiving the clock signal and the at least one jitter information, and for generating the second control signal through the clock signal during a second enabling sequence according to the at least one jitter information, wherein the first The enabling sequence period does not overlap with the second enabling sequence period. The light-emitting diode display device as described in Claim 1, wherein the signal generator includes: a first voltage level shift circuit for receiving the first control signal and adjusting the pulse wave of the first control signal the peak value of the second control signal to a first voltage value; and a second voltage level shift circuit for receiving the second control signal and adjusting the peak value of the pulse wave of the second control signal to a second voltage value, wherein the The first voltage value is different from the second voltage value; and a ramp circuit is used for receiving the adjusted first control signal and the second control signal, and according to the adjusted first control signal and the second The control signal is used to generate the at least one modulation signal. A driving method of a light emitting diode display device, comprising: providing a first control signal and a second control signal according to at least one display data; generating and providing at least one control signal according to the first control signal and the second control signal Modulate the signal to at least one display row, wherein the at least one modulation signal has a plurality of pulses in an image frame period; in the image frame period, drive a plurality of light emitting lights in the at least one display row multiple times component; correlate the number of the pulses of the at least one modulation signal with the grayscale value of the at least one display data of the at least one display row; and make at least one of the pulses of the at least one modulation signal The amplitude of a first pulse wave is different from that of at least one other second pulse wave among the pulse waves. The driving method as described in claim 6, further comprising: generating at least one jitter information according to the at least one display data of the at least one display row; generating a clock signal; and processing the clock signal according to the at least one jitter information to generate the first control signal and the second control signal, wherein the enabled periods of the first control signal and the second control signal do not overlap with each other. The driving method as described in claim 7, wherein the step of generating the at least one dithering information includes: accumulating the gray scale value of the at least one display data of the at least one display row to generate an accumulated gray scale value; comparing the accumulated gray scale value According to the matching result, a pulse number is determined; according to the pulse number, a scrambling sequence is generated; and according to the scrambling sequence, at least one jitter information is generated to determine The peak distribution of the pulse waves of the at least one modulation signal. The driving method as described in claim 8, wherein the step of processing the clock signal and generating the first control signal and the second control signal includes: according to the at least one jitter information, passing the a clock signal to generate the first control signal; and According to the at least one jitter information, the clock signal is passed during a second enable timing period to generate the second control signal, wherein the first enable timing period and the second enable timing period do not overlap each other. The driving method as described in claim 6, wherein the step of generating the at least one modulation signal to the at least one display column includes: respectively adjusting the peak value of the pulse wave of the first control signal and the pulse wave of the second control signal peak value; and converting the adjusted first control signal and the second control signal into the at least one modulated signal, wherein the adjusted peak value of the pulse wave of the first control signal and the adjusted second control signal The peak value of the pulse wave is different.

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