TWI775145B - Multi-chip package and manufacture method thereof - Google Patents

Abstract

A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.

Description

Multichip package and method of making the same

The present invention relates to a semiconductor package and a manufacturing method thereof, and more particularly, to a multi-chip package and a manufacturing method thereof.

In order to make the semiconductor package have both light and thin volume and high performance, the current packaging technology has tried to integrate a plurality of semiconductor chips into a single semiconductor package to form a multi-chip package or to stack a plurality of semiconductor packages with a three-dimensional stacking technology to form a multi-chip package. Form a package on package (PoP) or a system in package (System in Package). However, the speed of signal communication among the plurality of semiconductor chips in the existing multi-chip package is limited, so the overall performance of the semiconductor package still needs to be further improved.

The object of the present invention is to provide a multi-chip package with good performance.

The invention provides a multi-chip package including an interposer, a plurality of semiconductor chips, an encapsulation body and a reconfigured circuit structure. The interposer includes a wiring structure and an interposer via electrically connected to the wiring structure. The plurality of semiconductor chips are located on the first surface of the interposer and are electrically connected to each other through the interposer. The encapsulant is on the first surface of the interposer and encapsulates at least a portion of the plurality of semiconductor wafers. The reconfiguration line structure is located on a second surface of the interposer, the second surface of the interposer being opposite the first surface of the interposer. The plurality of semiconductor chips are electrically connected to the reconfiguration line structure at least through the interposer.

The present invention provides a multi-chip package including an interposer, a plurality of semiconductor chips and a reconfigured circuit structure. The interposer includes a wiring structure, an opening exposing at least a portion of the wiring structure, and an interposer via located in the opening and electrically connected to the wiring structure. The plurality of semiconductor chips are located on the first surface of the interposer and are electrically connected to each other through the interposer. The reconfiguration circuit structure is located on a second surface of the interposer and is electrically connected to the interposer via, and the second surface of the interposer is opposite to the first surface of the interposer. The plurality of semiconductor chips are electrically connected to the reconfiguration line structure at least through the interposer.

The present invention provides a method of manufacturing a multi-chip package, comprising the following steps. A plurality of semiconductor wafers are provided on the first surface of the interposer such that the first conductors of the interposer and the second conductors of the plurality of semiconductor wafers are bonded to each other. An opening is formed from a second surface of the interposer opposite the first surface to expose at least a portion of the wiring structure of the interposer. An interposer via is formed in the opening of the interposer, the interposer via being connected to the wiring structure of the interposer. A reconfiguration line structure is formed on the second surface of the interposer, and the reconfiguration line structure is electrically connected to the interposer via.

Based on the above, the multi-chip package of the present invention can improve the overall performance of the multi-chip package.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

The following examples are described in detail with the accompanying drawings, but the provided examples are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only, and are not drawn in full scale, and different layers or regions may be enlarged or reduced to be shown in a single drawing. Furthermore, although "first", "second", etc. are used herein to describe various elements, regions and/or components, these elements, regions and/or components should not be limited by these terms. Rather, these terms are only used to distinguish one element, region or component from another element, region or component. Thus, a first element, region or component discussed below could be termed a second element, region or component without departing from the teachings of the embodiments. The same or similar reference numerals denote the same or similar elements, and the repeated descriptions will not be repeated in the following paragraphs.

Herein, spatially relative terms such as "upper" and "lower" are defined with reference to the accompanying drawings. Thus, it should be understood that the term "upper surface" may be used interchangeably with the term "lower surface" and that when an element such as a layer or film is described as being disposed on another element, the element may be placed directly on the other element , or an intervening element may exist between the two elements. On the other hand, when one element is described as being disposed directly on another element, there are no intervening elements between the two elements. Similarly, when an element is described as being connected or engaged with another element, the element can be directly connected or engaged with the other element or intervening elements may be present between the two elements. On the other hand, when an element is described as being directly connected or engaged with another element, there are no intervening elements between the two elements.

FIG. 1 is a schematic cross-sectional view illustrating a multi-chip package according to an embodiment of the present invention. FIG. 2 is a schematic plan view along line I-I' of the multi-die package of FIG. 1 .

1 , a multi-die package 100 according to an embodiment of the present invention includes an interposer 150 , a semiconductor die 120 on a first surface 150A of the interposer 150 , and a first surface 150A of the interposer 150 opposite to the first surface 150A. Reconfigured line structures 110 on two surfaces 150B.

The interposer 150 may be used to connect the side-by-side semiconductor die 120 to each other and to the reconfiguration wiring structure 110 . The interposer 150 may include a wiring structure 150W in the body of the interposer 150 , an opening 150H exposing the wiring structure 150W, and an interposer via 153 in the opening 150H and connected to the wiring structure 150W, and on the first surface 150A of the interposer 150 A connection conductor 150P connected to the wiring structure 150W may be included. The wiring structure 150W can be used to transmit signals, especially high-bandwidth signals, between the side-by-side semiconductor chips 120 . The interposer 153 can electrically connect the wiring structure 150W to the reconfiguration wiring structure 110 .

In current System in Packages, reconfigured wiring structures are used to transmit signals between side-by-side semiconductor chips. However, with the increase of high-performance computing applications, the demand for high-bandwidth signal transmission is also increasing. The reconfiguration circuit structure is limited by the line width and line spacing and the exposure and development capability of the organic dielectric layer, and the number of layers used for the connection is not large, so a connection structure with a higher circuit density is still required to meet the requirements of, for example, high bandwidth memory (High Bandwidth Memory). , HBM) bandwidth requirements. The multi-chip package of the present invention transmits signals between the semiconductor chips 120 by using the wiring structure 150W with higher wiring density (ie, smaller line width and line spacing and more layers) than the reconfigured wiring structure. for faster signal transmission.

For example, in the multi-chip package according to the present invention, the number of layers of the wiring structure 150W may be multiple layers, such as 4 layers or more, and the line width, line spacing and via size may be less than or equal to 10 microns. Since the multi-chip package of the present invention may have wiring structures 150W with a line width of less than or equal to 10 μm to connect the semiconductor chips 120 , high-bandwidth signal transmission can be performed between the semiconductor chips 120 .

In addition, the multi-die package 100 according to the present invention may form the interposer via 153 on the backside of the interposer 150 to electrically connect the wiring structure 150W to the reconfiguration wiring structure 110 . The interposer via 153 in the multi-chip package 100 of the present invention does not need to penetrate the interposer, that is, no via structure such as through silicon via or through glass via may be formed in the interposer 150 . Therefore, the interposer 150 of the multi-chip package according to the present invention can save the process of forming the via structure, thereby reducing the cost and improving the yield. However, the present invention is not limited thereto, and a through hole structure may also be formed in the interposer 150 as needed.

The material of the main body of the interposer 150 may be, for example, inorganic semiconductor materials such as silicon (Si), germanium (Ge), and gallium arsenide (GaAs), or glass. The wiring structure 150W may be formed in the body of the interposer 150 . The wiring structure 150W can be used to transmit signals, especially high-bandwidth signals, between the semiconductor chips 120 . The material of the wiring structure 150W may include, for example, copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten ( W) or its alloys and other conductive materials or other metals with excellent electrical properties or their alloys. As described above, the wiring structure 150W has a high wiring density. In some embodiments, the number of layers of the wiring structure 150W may be multiple layers, for example, 4 layers or more, and the line width, line spacing and via size may be less than or equal to 10 microns. For example, the line width, line spacing, and via size of the wiring structure 150W may each be about 1 micrometer or less, about 2 micrometers or less, about 3 micrometers or less, about 4 micrometers or less than 4 micrometers , about 5 microns or less, about 6 microns or less, about 7 microns or less, about 8 microns or less than 8 microns or about 9 microns or less.

Referring to FIG. 2 , the interposer 150 may have a plurality of openings 150H. The plurality of openings 150H may penetrate at least a portion of the interposer 150 from the second surface of the interposer 150 but not penetrate the interposer 150 . In other words, the plurality of openings 150H do not directly contact the first surface 150A of the interposer 150 . The plurality of openings 150H may have different depths, so that the plurality of openings 150H may respectively expose wiring structures of different layers. Referring to the enlarged view in FIG. ₁ , the width WB of one end of the opening 150H closer to the second surface 150B may be greater than the width _WA of the other end closer to the first surface 150A. That is, the angle α between the tapered sidewalls of the opening 150H and the second surface 150B may be greater than 90°. In other words, the width of the opening 150H increases as the distance from the semiconductor wafer 120 increases. An intermediate via 153 is disposed on the sidewall of the opening 150H. The material of the interposer 153 may include copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W ) or its alloys and other conductive materials. The interposer via 153 may be used to electrically connect the wiring structure 150W of the interposer 150 and the reconfiguration wiring layer 116 of the reconfiguration wiring structure 110 to each other. As shown in FIG. 1 , the intervening via 153 may be conformally formed on the surface of the opening 150H, that is, formed in the form of a thin layer on the wall surface of the opening 150H. In other embodiments, the intervening via 153 may also fill the entire opening 150H.

An interposer connection conductor 150P is formed on the first surface 150A of the interposer 150 . Interposer connection conductors 150P may be used to connect interposer 150 to other devices. The material of the interposer connection conductor 150P may include, for example, copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), Conductive materials such as tungsten (W) or its alloys, or other metals with excellent electrical properties or their alloys. The shape of the interposer connection conductor 150P may include various shapes such as a pillar shape or a stud bump. The interposer connection conductors 150P may have different sizes. For example, the interposer connection conductor 150P may include a first interposer connection conductor 150P1 with a larger size and a second interposer connection conductor 150P2 with a smaller size. That is, the width DA of the first interposer connection conductor _150P1 is greater than the width DB of the second interposer connection conductor _150P2 . In other embodiments, the interposer connection conductors 150P may have the same size.

The semiconductor chip 120 may be any suitable integrated circuit (IC) chip, such as a memory chip, a logic chip, a digital chip, an analog chip, a sensor chip, an AI chip, a radio frequency chip (wireless and radio frequency chip) or voltage regulator chip, etc. The sensor chip may be an image sensor chip, at least including a charge coupled device (CCD) or a CMOS image sensor. Although two semiconductor dies 120 are included in the multi-die package 100 of FIG. 1 , the present invention is not limited thereto. For example, the multi-die package of the present invention may include three or more than three semiconductor die 120 . In some embodiments, the lateral distance between the individual semiconductor wafers 120 may be maintained constant (ie, the semiconductor wafers 120 are arranged equidistantly on the interposer 150 ). In other embodiments, the lateral distance between the individual semiconductor wafers 120 may vary (ie, the semiconductor wafers 120 are arranged non-equidistantly on the interposer 150). The individual semiconductor wafers 120 may be separated from each other by an encapsulant 180 described below.

The semiconductor wafer 120 has wafer connection conductors 120P on the active surface. The material of the die attach conductor 120P may include, for example, copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W) or its alloys or other conductive materials, or other metals with excellent electrical properties or their alloys. The shape of the die connecting conductor 120P may include various shapes such as a column shape or a stud bump. The die attach conductors 120P may have different sizes. For example, the die attach conductors 120P may include a first die attach conductor 120P1 having a larger size and a second die attach conductor 120P2 having a smaller size. That is, the width D ₁ of the first die attach conductor 120P1 is greater than the width D ₂ of the second die attach conductor 120P2. The die connection conductors 120P and at least a part of the interposer connection conductors 150P are joined to each other. In some embodiments, the die attach conductors 120P and the interposer attach conductors 150P, which are correspondingly bonded to each other, may have corresponding sizes. For example, the larger first die attach conductor 120P1 may be bonded to the larger first interposer attach conductor 150P1 and the smaller second die attach conductor 120P2 may be bonded to the smaller second interposer attach conductor 150P2. In this case, the larger first die attach conductor 120P1 and the first interposer attach conductor 150P1 may be used to carry large currents (eg, ground), while the smaller second die attach conductor 120P2 and the second interposer attach conductor 150P2 can be used to transmit high bandwidth signals. The bonding surfaces of the die attach conductors 120P and the interposer connection conductors 150P may be solderless bonding surfaces. Since the interposer 150 and the semiconductor chip 120 are connected to each other through the die connecting conductors 120P and the interposer connecting conductors 150P instead of the reconfigured wiring structure, the transmission paths of power and/or signals between the interposer 150 and the semiconductor chip 120 can be shortened , and improve the transmission speed and quality of power and/or signals. In some embodiments, bumps may be further included between the die attach conductors 120P and the interposer attach conductors 150P (as shown in FIG. 4B ).

In addition, the side-by-side semiconductor wafers 120 may be connected to each other via the wiring structures 150W in the interposer 150 . As described above, the high-density wiring structure 150W of the inter-chip interconnection may have a line width of less than or equal to 10 μm, and the wiring structure 150W may transmit high-bandwidth signals between the semiconductor chips 120 . In addition, depending on the signal or current to be transmitted, a signal requiring a faster transmission speed or a larger bandwidth can be transmitted through the second chip connecting conductor 120P2 and the second interposer connecting conductor 150P2, while power or ground can be transmitted through the second chip connecting conductor 120P2 and the second interposer connecting conductor 150P2. A die attach conductor 120P1 communicates with the first interposer connection conductor 150P1. That is, in the multi-chip package 100 of the present invention, the signal transmission between the semiconductor chips 120 may be transmitted through different paths depending on the nature of the signal.

The multi-die package 100 according to the present invention may include an underfill 170 between the semiconductor die 120 and the interposer 150 . The primer 170 can fill the space between the semiconductor die 120 and the interposer 150 and encapsulate the interposer connecting conductor 150P and the die connecting conductor 120P. The primer 170 has inclined sidewalls, and the upper width of the primer 170 is smaller than the lower width of the primer 170 . In some embodiments, the width of the primer 170 is tapered, and the width of the primer 170 gradually decreases from one end closer to the interposer 150 toward the other end closer to the semiconductor wafer 120 . The material of the primer 170 is not particularly limited, and may be, for example, an insulating material such as epoxy resin. In other embodiments, the multi-die package 100 according to the present invention may also replace the primer 170 with a protective layer 175 between the semiconductor die 120 and the interposer 150 (see FIG. 5B ).

The multi-die package 100 according to the present invention may include an encapsulant 180 on the interposer 150 to encapsulate the semiconductor die 120 and the interposer 150 . The encapsulant 180 may be disposed between the semiconductor wafers 120 to separate the semiconductor wafers 120 from each other. The material of the encapsulant 180 may include molding compound, molding underfill, resin or epoxy molding compound (EMC), and the like. Optionally, the encapsulation body 180 may be doped with inorganic fillers. The sidewalls of the encapsulation body 180 , the sidewalls of the interposer 150 , and the sidewalls of the reconfiguration wiring structure 110 may be aligned with each other.

The reconfiguration wiring structure 110 is located on the second surface 150B of the interposer 150 and can be used to reroute the input and output terminals of the semiconductor wafer 120 . For example, the reconfigured wiring structure 110 may be used to fan-out the input and output terminals of the semiconductor chip 120 to connect the semiconductor chip 120 and a printed circuit board (PCB) (not shown). The reconfiguration wiring structure 110 includes a plurality of dielectric layers 114 and a plurality of reconfiguration wiring layers 116 embedded in the dielectric layers 114 . The material of the dielectric layer 114 may include polyimide, epoxy, acrylic resin, phenolic resin, Bismaleimide-trazine resin (BT resin) or any other suitable polymer Dielectric materials and silicon oxide layers, silicon nitride layers, silicon oxynitride layers or other suitable silicon dielectric materials. In some embodiments, the material of the dielectric layer 114 may include a photosensitive insulating resin. The material of the reconfiguration wiring layer 116 may include copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W) or its alloys and other conductive materials.

The reconfiguration wiring structure 110 may further include a reconfiguration via 118, and the reconfiguration via 118 may be used to connect the reconfiguration wiring layers 116 at different layers. The material of the reconfiguration via 118 may include copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten ( W) or its alloys and other conductive materials. The upper width W ₁ of the reconfiguration via 118 may be smaller than the lower width W ₂ of the reconfiguration via 118 . That is, the angle β between the sloped sidewalls of the reconfiguration vias 118 and the lower surface of the dielectric layer 114 may be greater than 90°.

Although the reconfiguration wiring structure 110 in FIG. 1 is shown as including three layers of dielectric layers 114 and three layers of reconfiguration wiring layers 116 , the present invention is not limited thereto. The multi-die package 100 according to the present invention may include more or less dielectric layers 114 and reconfiguration wiring layers 116 than shown in the figures.

The multi-die package 100 according to the present invention may further include conductive terminals 190 . Conductive terminals 190 are partially embedded in the lowermost dielectric layer 114 to connect to the lowermost reconfiguration wiring layer 116 . The conductive terminals 190 may be used to connect the multi-die package 100 to external devices such as printed circuit boards. The conductive terminals 190 may be, for example, solder balls, but the present invention is not limited thereto.

In the multi-chip package 100 according to the present invention, the side-by-side semiconductor chips 120 can be connected to each other through the interposer 150 having the high-density and high-layer-count wiring structure 150W to achieve high-efficiency signal transfer. Meanwhile, the multi-chip package 100 according to the present invention can realize a fan-out package by reconfiguring the wiring structure 110 to rewire the semiconductor chip 120 .

3A to 3H are schematic cross-sectional views illustrating steps of a manufacturing process for manufacturing a multi-chip package according to an embodiment of the present invention. 4A and 4B are schematic cross-sectional views illustrating a method for bonding wafers according to an embodiment of the present invention. 5A and 5B are schematic cross-sectional views illustrating a method for bonding wafers according to another embodiment of the present invention.

3A, a semiconductor substrate 15 having a wiring structure 150W is provided. The semiconductor substrate 15 can be, for example, a silicon substrate. Although only the process of forming one multi-chip package using the semiconductor substrate 15 is shown in the figures, in some embodiments, a semiconductor substrate 15 having a large size may be used to form multiple multi-chip packages simultaneously. For example, a silicon wafer or a panel-level silicon substrate can be used as the semiconductor substrate 15 . The semiconductor substrate 15 has an interposer connection conductor 150P on the first surface 150A, and the interposer connection conductor 150P is electrically connected to the wiring structure 150W. The interposer connection conductor 150P includes a first interposer connection conductor 150P1 and a second interposer connection conductor 150P2 having different sizes. That is, the width DA of the first interposer connection conductor _150P1 may be greater than the width DB of the second interposer connection conductor _150P2 . Optionally, the width DA of the first interposer connection conductor _150P1 and the width DB of the second interposer connection conductor _150P2 may be the same.

3B, a plurality of semiconductor wafers 120 are provided on the semiconductor substrate 15 such that the wafer connection conductors 120P and the interposer connection conductors 150P are aligned and bonded to each other. The die attach conductor 120P includes a first die attach conductor 120P1 and a second die attach conductor 120P2 having different sizes. That is, the width D ₁ of the first die attach conductor 120P1 may be greater than the width D ₂ of the second die attach conductor 120P2 . Size In some embodiments, the larger size first die attach conductor 120P1 and the first interposer attach conductor 150P1 are bonded to each other, and the smaller size second die attach conductor 120P2 and the second interposer connection conductor 150P2 are bonded to each other. The bonding method of the die attach conductors 120P and the interposer connection conductors 150P may be, for example, direct bonding by heating and/or pressure. After the die attach conductors 120P and the interposer attach conductors 150P are bonded, a primer 170 may be applied on the inorganic semiconductor substrate 15 to encapsulate the die attach conductors 120P and the interposer attach conductors 150P.

In some embodiments, the die attach conductors 120P and the interposer attach conductors 150P may be bonded to each other through bumps. Referring to FIG. 4A , first bumps 155 may be formed on interposer attach conductors 150P and second bumps 165 may be formed on die attach conductors 120P. Then, the first bumps 155 and the second bumps 165 are bonded together using heat and/or pressure. The materials of the first bump 155 and the second bump 165 can be, for example, solder alloys (eg Cu/Sn, Cu/Ni/Sn, Cu/Ni/SnBi), copper, gold, silver, indium, palladium, titanium, manganese , cobalt, or its alloys (such as Ni/Au, Cu/Ni/Au, Cu/Ni/In) and other bonding metals. Materials of the first bump 155 and the second bump 165 may be different from each other. For example, the material of the first bump 155 may be surface-treated pure copper, Ni/Au alloy, Cu/Ni/Au alloy, or Cu/Ni/In alloy, and the material of the second bump 165 may be Cu/ Sn, Cu/Ni/Sn or Cu/Ni/SnBi alloy, etc. In some embodiments, the materials of the first bumps 155 and the second bumps 165 do not contain solder components. In some embodiments, the material of the first bump 155 and the second bump 165 may be a low temperature bonding metal with a melting point lower than 200°C. For example, the low temperature bonding metal may include twin-crystalline copper, twin-crystalline silver or other nano-twin materials, indium-tin alloys, tin-bismuth alloys, porous gold, or combinations thereof. Compared to conventional solder balls or solders that require reflow temperatures greater than or equal to 250°C, the use of low temperature bond metals can be used at relatively low heating temperatures (for example, at temperatures below 200°C or below 150°C) The connection structure achieves stable bonding and meets the reliability requirements of electrical connection requirements. In some embodiments, only one of the first bump 155 and the second bump 165 may be formed. For example, the first bumps 155 may be formed only on the interposer attach conductors 150P and bonded to the die attach conductors 120P.

4B , after the first bumps 155 and the second bumps 165 are bonded, an underfill 170 may be applied on the semiconductor substrate 15 to encapsulate the die attach conductors 120P, the interposer connection conductors 150P, the first bumps 155 and the The second bump 165 . The underfill 170 can fill the space between the semiconductor chip 120 and the semiconductor substrate 15 and encapsulate the interposer connecting conductor 150P, the die connecting conductor 120P, the first bump 155 and the second bump 165 .

Referring to FIGS. 5A and 5B , in some embodiments, a protective layer 175 may be formed on the semiconductor wafer 120 . The material of the protective layer 175 can be, for example, organic materials such as resin, non-conductive adhesive film, and dielectric materials. The surface of the die attach conductor 120P and the surface of the protective layer 175 between the semiconductor die 120 may be coplanar. When the die connecting conductor 120P and the interposer connecting conductor 150P are bonded to each other, since the die connecting conductor 120P is encapsulated by the protective layer 175 and only the surface is exposed for connection, it can be prevented from being damaged by external force impact. Rate.

Referring back to FIG. 3C , an encapsulant 180 is formed on the semiconductor substrate 15 . The method of forming the encapsulant 180 includes the following steps. An encapsulation material layer covering the semiconductor substrate 15 and the semiconductor wafer 120 is formed on the semiconductor substrate 15 through a suitable process (eg, a molding process or a deposition process), and thereafter, a surface grinding and polishing process (grinding) or a surface planarization process ( surface planarization) exposes the upper surface of the semiconductor wafer 120 .

3C and 3D together, the structure obtained in FIG. 3C is turned upside down, and a thinning process such as a grinding process or an etching process is performed on the backside of the semiconductor substrate 15 to reduce the thickness of the semiconductor substrate 15 . The purpose of reducing the thickness of the semiconductor substrate 15 is to miniaturize and thin the final multi-chip package. In addition, the reduced thickness of the semiconductor substrate 15 also facilitates the formation of the following openings 150H. This step can be omitted if desired. The thinned semiconductor substrate 15 is hereinafter referred to as an interposer 150 .

Referring to FIG. 3E , a plurality of openings 150H exposing at least a portion of the wiring structure 150W in the interposer 150 are formed in the interposer 150 by, for example, an etching process. Referring to the enlarged view in FIG. 3E , the width WB of the opening 150H formed in the interposer 150 near the second surface 150B may be greater than the width _WA near the first surface _150A . That is, the angle α between the tapered sidewalls of the opening 150H and the second surface 150B may be greater than 90°. In other words, the width of the opening 150H increases as the distance from the semiconductor wafer 120 increases.

Referring to FIG. 3F , a reconfiguration wiring layer 116 and an interposer via 153 are formed on the second surface 150B of the interposer 150 and the surfaces of the openings 150H, respectively. The reconfiguration wiring layer 116 and the interposer via 153 can be integrally formed. For example, the process of forming the reconfiguration wiring layer 116 and the interposer via 153 includes the following steps. First, a seed layer is sputtered or deposited on the second surface 150B of the interposer 150 and the surface of the opening 150H, where the material of the seed layer can be, for example, a conductive material such as titanium/copper. Next, a patterned photoresist layer is formed on the seed layer to expose the seed layer. A conductive material is formed on the seed layer exposed by the patterned photoresist layer through an electroplating process, and the conductive material may include copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W) or alloys thereof. Next, the photoresist layer and part of the seed layer not covered by the conductive material are removed to form the reconfiguration wiring layer 116 and the interposer 153 .

Referring to FIG. 3G , a dielectric layer 114 may be formed on the redistribution wiring layer 116 and on the interposer via 153 , thereby forming a redistribution circuit structure 110 . The method of forming the dielectric layer 114 may include spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and the like. The dielectric layer 114 may fill the space in the opening 150H that is not occupied by the interposer via 153 .

The reconfiguration wiring structure 110 may include a multi-layer or a single-layer reconfiguration wiring layer 116 . When the reconfiguration wiring structure 110 includes multiple layers of reconfiguration wiring layers 116, the process of forming the upper layer reconfiguration wiring layer 116 includes the following steps. First, via holes are formed in the dielectric layer 114 to expose the underlying reconfiguration wiring layer 116 . The method of forming the via holes in the dielectric layer 114 may use different processes depending on the material of the dielectric layer 114 . When the dielectric layer 114 is a photosensitive insulating layer including a photosensitive insulating resin, the dielectric layer 114 can be patterned by a lithography process to form via holes. When the dielectric layer 114 is a non-photosensitive insulating layer, the dielectric layer 114 can be patterned by a lithography/etching process, a laser drilling process or a mechanical drilling process to form via holes. Next, in the same manner as described above for forming the reconfiguration wiring layer 116 , the upper layer reconfiguration wiring layer 116 and the reconfiguration vias 118 filling the via holes are formed to connect to the reconfiguration wiring layer 116 exposed through the via holes. Although in the drawings, the reconfiguration line structure 110 is shown as including three layers of dielectric layers 114 and three layers of reconfiguration wiring layers 116 , the invention is not limited to this, and the reconfiguration line structure 110 may include more Multiple or fewer dielectric layers 114 and reconfiguration wiring layers 116 .

Referring to FIG. 3H , a plurality of conductive terminals 190 may be formed on the reconfigured wiring structure 110 to complete the multi-chip package 100 of the present invention. A plurality of multi-chip packages 100 of the present invention can be simultaneously formed using a large-sized semiconductor substrate 15 , and then the individual multi-chip packages 100 are separated by processes such as dicing. Therefore, the sidewalls of the interposer 150 and the sidewalls of the encapsulation body 180 in the multi-die package 100 of the present invention can be aligned with the sidewalls of the reconfiguration circuit structure 110 .

In summary, the present invention provides a multi-chip package and a method for manufacturing the same. The multi-chip package of the present invention can shorten the transmission paths of power and/or signals in the multi-chip package to improve the overall performance of the multi-chip package, and at the same time, the multi-chip package of the present invention also has a re-wiring structure and has a fan-out type Package design freedom.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

15: Semiconductor substrate 100: Multi-die package 110: Reconfigured wiring structure 114: Dielectric layer 116: Reconfigured wiring layer 118: Reconfigured via 120: Semiconductor die 120P: Die attach conductor 120P1: First die attach conductor 120P2: Second die attach conductor 150: Interposer 150A: First surface 150B: Second surface 150H: Opening 150P: Interposer attach conductor 150P1: First interposer attach conductor 150P2: Second interposer attach conductor 150W: Wiring structure 153: Intermediate via 155: First bump 165: Second bump 170: Underfill 175: Protective layer 180: Encapsulation body 190: Conductive terminal I-I': Section line D ₁ : Width D ₂ : Width D _A : Width D _B : Width W ₁ : Width W ₂ : Width W _A : Width W _B : Width α: Angle β: Angle

FIG. 1 is a schematic cross-sectional view illustrating a multi-chip package according to an embodiment of the present invention. FIG. 2 is a schematic plan view along line I-I' of the multi-die package of FIG. 1 . 3A to 3H are schematic cross-sectional views illustrating steps of a manufacturing process for manufacturing a multi-chip package according to an embodiment of the present invention. 4A and 4B are schematic cross-sectional views illustrating a method for bonding wafers according to an embodiment of the present invention. 5A and 5B are schematic cross-sectional views illustrating a method for bonding wafers according to another embodiment of the present invention.

100: Multi-die package

110: Reconfigure the circuit structure

114: Dielectric layer

116: Reconfigure the wiring layer

118: reconfiguration path

120: Semiconductor wafer

120P: Chip connection conductor

120P1: First chip connection conductor

120P2: Second chip connection conductor

150:Intermediary Layer

150A: First surface

150B: Second Surface

150H: Opening

150P: Interposer connection conductor

150P1: First interposer connection conductor

150P2: Second interposer connection conductor

150W: wiring structure

153: Mediation pathway

170: Primer

180: Encapsulation

190: Conductive terminal

I-I': Section Line

D ₁ : width

D ₂ : width

D _A : width

D _B : width

W ₁ : width

W ₂ : width

W _A : width

W _B : width

α: included angle

β: included angle

Claims (19)

A multi-die package comprising: an interposer including a wiring structure and intervening vias electrically connected to the wiring structure; a plurality of semiconductor dies on a first surface of the interposer and connected to each other via the interposer electrical connections; an encapsulant on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a reconfiguration circuit structure on the second surface of the interposer, the second surface of the interposer is opposite the first surface of the interposer, wherein the plurality of semiconductor chips are electrically connected to the reconfiguration line structure at least through the interposer, and wherein An interposer connecting conductor is disposed on the first surface of the interposer, and a die connecting conductor is disposed on a surface of each of the plurality of semiconductor wafers adjacent to the interposer, and the interposer connecting conductor is connected to the interposer. The die attach conductors are joined to each other. The multi-die package of claim 1, wherein the bonding surface between the interposer connecting conductor and the die connecting conductor is a solderless bonding surface. The multi-die package of claim 1, wherein the interposer connection conductor and the die connection conductor are joined by a bonding metal having a melting point below 200°C. The multi-die package of claim 1, further comprising a first bump located between the interposer connecting conductor and the die connecting conductor. The multi-die package of claim 4, further comprising a second bump located between the first bump and the die attach conductor. The multi-chip package of claim 1, further comprising: a protective layer disposed between the interposer and the plurality of semiconductor chips and encapsulating the interposer connection conductors and the die connection conductors. The multi-die package of claim 1, wherein the interposer connection conductor comprises a first interposer connection conductor and a second interposer connection conductor, the first interposer connection conductor having a larger size than the second interposer connection conductor The size of the layer connection conductors. The multi-die package of claim 7, wherein the die attach conductors comprise first die attach conductors and second die attach conductors, the first die attach conductors being larger in size than the second die attach conductors . The multi-die package of claim 8, wherein the first interposer attach conductor and the first die attach conductor are bonded to each other, and the second interposer attach conductor and the second die attach conductor are attached to each other engage. The multi-die package of claim 1, wherein the interposer includes an opening exposing at least a portion of the wiring structure, the interposer via being disposed in the opening. The multi-die package of claim 10, wherein a width of the opening increases with distance from the plurality of semiconductor dies. The multi-chip package of claim 10, wherein the reconfiguration wiring structure includes a dielectric layer and a reconfiguration wiring layer, and the reconfiguration wiring layer is electrically connected to the intermediate via. The multi-die package of claim 12, wherein a portion of the dielectric layer fills a portion of the opening. The multi-die package of claim 1, wherein sidewalls of the encapsulation body, sidewalls of the interposer, and sidewalls of the reconfiguration line structure are aligned with each other. The multi-die package of claim 1, wherein the interposer comprises through silicon vias. The multi-chip package of claim 1, wherein the material of the body of the interposer comprises silicon, germanium, gallium arsenide (GaAs) or glass. The multi-chip package as claimed in claim 1, further comprising: a primer, disposed between the interposer and the plurality of semiconductor chips, wherein the width of the primer varies with the width of the plurality of semiconductor chips increases as the distance increases. A multi-die package includes: an interposer including a wiring structure, an opening exposing at least a portion of the wiring structure, and an interposer via located in the opening and electrically connected to the wiring structure; a plurality of semiconductor chips, on a first surface of the interposer and electrically connected to each other through the interposer; and a reconfigured circuit structure on a second surface of the interposer and electrically connected with the interposer, the The second surface of the interposer is opposite the first surface of the interposer, wherein the plurality of semiconductor chips are electrically connected to the interposer at least via the interposer The reconfigured line structure, and wherein interposer connection conductors are configured on the first surface of the interposer, and die connection conductors are configured on a surface of each of the plurality of semiconductor wafers immediately adjacent to the interposer , the interposer connecting conductor and the die connecting conductor are bonded to each other. A method of fabricating a multi-die package comprising: providing a plurality of semiconductor dice on a first surface of an interposer such that interposer connection conductors of the interposer and die attach conductors of the plurality of semiconductor dice are bonded to each other; from A second surface of the interposer opposite to the first surface forms an opening to expose at least part of a wiring structure of the interposer; an interposer via is formed in the opening of the interposer, the interposer a via is connected to the wiring structure of the interposer; and a reconfiguration line structure is formed on the second surface of the interposer, the reconfiguration line structure is electrically connected to the interposer via.

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