TWI775121B - High electron mobility transistor - Google Patents

Abstract

A high electron mobility transistor includes a channel layer, a barrier layer, a first compound semiconductor layer, and a second compound semiconductor layer. The channel layer is disposed on the substrate, and the barrier layer is disposed on the channel layer. The first compound semiconductor layer is disposed on the barrier layer. The second compound semiconductor layer is disposed between the barrier layer and the first compound semiconductor layer, where the first compound semiconductor layer and the second compound semiconductor layer include a concentration distribution of metal dopant, and the concentration distribution of metal dopant includes a first peak in the first compound semiconductor layer and a second peak in the second compound semiconductor layer.

Description

High Electron Mobility Transistor

The present disclosure relates to the field of semiconductor devices, and in particular, to a high electron mobility transistor.

In semiconductor technology, group III-V semiconductor compounds can be used to form various integrated circuit devices, such as high power field effect transistors, high frequency transistors or high electron mobility transistors (HEMTs). HEMT is a transistor with two dimensional electron gas (2-DEG), and its 2-DEG will be adjacent to the junction between two materials with different energy gaps (ie, heterojunction) . Since HEMT does not use the doped region as the carrier channel of the transistor, but uses 2-DEG as the carrier channel of the transistor, compared with the conventional MOSFET, HEMT has various attractive Human characteristics such as high electron mobility and the ability to transmit signals at high frequencies.

In order for the HEMT to be switched between an on-state and an off-state, a positive or negative voltage is usually applied to the gate of the HEMT. However, for the conventional HEMT, the threshold voltage (Vt) usually varies with the value of the gate voltage due to the gate-lag effect. For example, the threshold voltage deviation (ΔVt) corresponding to the on-state and the off-state is usually different, which is not conducive to the fast switching of the HEMT, thus affecting the performance of the semiconductor device.

In view of this, it is necessary to propose an improved high electron mobility transistor to improve the shortcomings of the conventional high electron mobility transistor.

According to an embodiment of the present disclosure, a high electron mobility transistor is provided, including a channel layer, a barrier layer, a first compound semiconductor layer, and a second compound semiconductor layer. Wherein, the channel layer is arranged on the substrate, and the barrier layer is arranged on the channel layer. The first compound semiconductor layer is disposed on the barrier layer. The second compound semiconductor layer is disposed between the barrier layer and the first compound semiconductor layer, wherein the first compound semiconductor layer and the second compound semiconductor layer include a concentration distribution of a metal dopant, and the concentration distribution in the first compound semiconductor layer has The first wave peak, and the concentration distribution in the second compound semiconductor layer has a second wave peak.

According to the embodiments of the present disclosure, since the second compound semiconductor layer is disposed between the first compound semiconductor layer and the barrier layer, by forming a concentration peak of the metal dopant in the second compound semiconductor layer, the second compound semiconductor layer can be increased The energy barrier between the highest valence band of the semiconductor layer and the highest valence band (maximum Ev) of the barrier layer. Therefore, holes from the first compound semiconductor layer are not easily injected into the barrier layer, thus avoiding trapped charges in the barrier layer, thereby reducing the threshold voltage deviation of the high electron mobility transistor degree, and avoid the gate delay effect.

100-1: High Electron Mobility Transistor

100-2: High Electron Mobility Transistor

100-3: High Electron Mobility Transistor

100-4: High Electron Mobility Transistor

100-5: High Electron Mobility Transistor

102: Substrate

104: Nitride layer

106: first nitride layer

108: Second nitride layer

110: Superlattice layer

112: first superlattice layer

114: Second superlattice layer

116: High resistance layer

118: Three or five family channel layer

120: Three-five barrier layer

122: the second compound semiconductor layer

124: the first compound semiconductor layer

126: Crystalline silicon compound semiconductor layer

128: P-type III-V compound semiconductor layer

130: Two-dimensional electron gas region

132: Two-dimensional hole-gas region

134: P-type III-V barrier layer

210: Curves

212: Curves

220: Curves

222: Curves

△V ₁ : Deviation of the first threshold voltage

△V ₂ : Deviation of the second threshold voltage

V _g1 : the first gate voltage

V _g2 : the second gate voltage

D: drain

G: gate

P1: crest

P2: Crest

S: source

In order to make the following easier to understand, reference is made to both the drawings and their detailed description while reading the present disclosure. The specific embodiments of the present disclosure will be explained in detail through the specific embodiments herein and the corresponding drawings will be referred to, and the working principles of the specific embodiments of the present disclosure will be described. Furthermore, for clarity, the various features in the drawings may not be drawn to scale, so some of the may be intentionally enlarged or reduced in size.

FIG. 1 is a schematic cross-sectional view of a semiconductor stack of a high-voltage semiconductor device according to an embodiment of the present disclosure, wherein the semiconductor stack at least includes a second compound semiconductor layer.

FIG. 2 is a graph showing the relationship between dopant concentration and depth in the semiconductor stack of the present disclosure.

FIG. 3 is a graph showing the relationship between the threshold voltage deviation value and the gate voltage of Embodiments 1 and 2 and Comparative Example 1 of the present disclosure.

FIG. 4 is a schematic cross-sectional view of a semiconductor stack of a high-voltage semiconductor device according to an embodiment of the disclosure, wherein the semiconductor stack at least includes a silicon capping layer.

5 is a schematic cross-sectional view of a semiconductor stack of a high-voltage semiconductor device according to an embodiment of the present disclosure, wherein the semiconductor stack at least includes a second compound semiconductor layer and a P-type IIIV compound semiconductor layer.

6 is a schematic cross-sectional view of a semiconductor stack of a high-voltage semiconductor device according to an embodiment of the present disclosure, wherein the semiconductor stack at least includes a second compound semiconductor layer and a P-type IIIV barrier layer.

7 is a schematic cross-sectional view of a semiconductor stack of a high-voltage semiconductor device according to an embodiment of the present disclosure, wherein the semiconductor stack at least includes a second compound semiconductor layer, a P-type III-V barrier layer, and a P-type III barrier layer. Group V compound semiconductor layer.

The present disclosure provides several different embodiments for implementing different features of the present disclosure. For simplicity of illustration, the present disclosure also describes examples of specific components and arrangements. These examples are provided for illustrative purposes only and are not intended to be limiting in any way. For example, the following description of "the first feature is formed on or over the second feature" may mean "the first feature is in direct contact with the second feature" or "the first feature is in direct contact with the second feature". There are other features between features", resulting in the first feature There is no direct contact with the second feature.

In addition, for the space-related narrative words mentioned in this disclosure, for example: "below", "low", "below", "above", "above", "below", "top" ”, “bottom” and similar words, for ease of description, are used to describe the relative relationship of one element or feature to another (or more) elements or features in the drawings. In addition to the pendulum shown in the drawings, these space-related terms are also used to describe the possible pendulum orientations of the semiconductor device during use and operation. With the different swing directions of the semiconductor device (rotated by 90 degrees or other orientations), the space-related descriptions used to describe the swing directions should also be interpreted in a similar manner.

Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that such elements, components, regions, layers, and/or blocks should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and/or block from another element, component, region, layer, and/or block, and do not by themselves imply or represent that element The presence of any preceding ordinal numbers does not imply the order in which an element is arranged relative to another element, or the order of the method of manufacture. Thus, a first element, component, region, layer or block discussed below could be termed a second element, component, region, layer or block without departing from the scope of the specific embodiments of the present disclosure Of.

The terms "about" or "substantially" referred to in this disclosure generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range, or Within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, the meaning of "about" or "substantially" can still be implied without the specific description of "about" or "substantially".

In the present disclosure, "group III-V semiconductor" refers to a compound semiconductor including at least one group III element and at least one group V element. Among them, the group III element can be boron (B), aluminum (Al), gallium (Ga) or indium (In), and the group V element can be nitrogen (N), phosphorus (P), arsenic (As) or antimony ( Sb). further In further terms, "group III and V semiconductors" may include: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), nitrogen Indium Aluminum Gallium (InAlGaN), Indium Gallium Nitride (InGaN), Aluminum Nitride (AlN), Gallium Indium Phosphide (GaInP), Aluminum Gallium Arsenide (AlGaAs), Aluminum Indium Arsenide (InAlAs), Gallium Arsenide Indium (InGaAs), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), analogs thereof, or compounds of the foregoing combination, but not limited to this. In addition, depending on the requirements, dopants may also be included in the III-V semiconductor, which is a III-V semiconductor with a specific conductivity type, such as an N-type or P-type III-V semiconductor.

Although the invention of the present disclosure is described below with reference to specific embodiments, the inventive principles of the present disclosure can also be applied to other embodiments. Furthermore, in order not to obscure the spirit of the present invention, certain details will be omitted, which are within the knowledge of those having ordinary skill in the art.

The present disclosure relates to a high voltage semiconductor device or a high electron mobility transistor (HEMT), such as a power switching transistor that can be used as a voltage converter or a telecommunication high power application, but the present invention is not limited thereto. Compared with silicon power transistors, III-V HEMTs have the characteristics of low on-state resistance (R _ON ) and low switching losses due to their wider energy bandgap.

FIG. 1 is a schematic cross-sectional view of a semiconductor stack of a high-voltage semiconductor device according to an embodiment of the present disclosure, wherein the semiconductor stack at least includes a P-type III-V intermediate layer. As shown in FIG. 1 , the high electron mobility transistor 100 - 1 includes a substrate 102 , a semiconductor stack (for example, at least a group 35 channel layer 118 , a group 35 barrier layer 120 , a second compound semiconductor layer 122 , The first compound semiconductor layer 124), the source electrode S, the drain electrode D, and the gate electrode G. Other layers such as the nitride layer 104 , the superlattice layer 110 , and the high resistance layer 116 may optionally be disposed between the substrate 102 and the semiconductor stack.

According to an embodiment of the present disclosure, the substrate 102 may be a ceramic substrate such as silicon carbide (SiC), aluminum oxide (Al ₂ O ₃ ), sapphire, or aluminum nitride. In one embodiment, a bonding layer may be disposed on the surface of the substrate 102 , wherein the bonding layer material includes silicon, for example. According to an embodiment of the present disclosure, the substrate 102 further includes a core layer and a single or multiple layers of insulating material and/or other suitable material layers covering the core layer. The core layer may be aluminum nitride or aluminum oxide. The material layers may be oxides, nitrides, oxynitrides, or other suitable insulating materials.

The nitride layer 104 can be selectively disposed on the substrate 102 , which has less lattice defects, and thus can improve the epitaxial quality of the semiconductor stacked layer disposed on the nitride layer 104 . The nitride layer 104 may include a nitride stack layer, such as a first nitride layer 106 and a second nitride layer 108 . According to an embodiment of the present disclosure, the first nitride layer 106 may be, for example, a low temperature aluminum nitride layer (LT-AlN), and the low temperature aluminum nitride layer may be deposited by metal-organic chemical vapor deposition (MOCVD), Formed at an ambient temperature of 800°C-1100°C; the second nitride layer 108 can be, for example, a high temperature aluminum nitride layer (HT-AlN), which can be deposited by organometallic chemical vapor deposition at 1100°C. It is formed under the ambient temperature of ℃-1400℃, but it is not limited to this.

A superlattice layer (SL) 110 may be selectively disposed on the substrate 102 , such as on the nitride layer 104 . The superlattice layer 110 can be used to reduce the degree of lattice mismatch between the substrate 102 and the semiconductor layer disposed on the superlattice layer 110, and to reduce the stress caused by the lattice mismatch. According to an embodiment of the present disclosure, the superlattice layer 110 may be a superlattice stacked layer, for example, including a first superlattice layer 112 and a second superlattice layer 114 . According to different requirements, the first superlattice layer 112 or the second superlattice layer 114 can each be a periodically alternating layer structure composed of at least two kinds of III-V compound semiconductors, such as AlN thin layers/GaN thin layers alternating The stacked structure, or each is a III-V compound semiconductor with a graded composition ratio, such as aluminum gallium nitride (Al _x Ga _1-x N, 0.15≦x≦0.9) whose aluminum composition ratio decreases from bottom to top, But not limited to this.

The high resistance layer 116 may be selectively disposed on the substrate 102 , such as on the superlattice layer 110 . Compared with other layers, the high-resistance layer 116 has higher resistivity, so that leakage current can be avoided between the semiconductor layer disposed on the high-resistance layer 116 and the substrate 102 . According to an embodiment of the present disclosure, the high resistance layer 116 may be a doped III-V semiconductor layer, such as carbon-doped gallium nitride (c-GaN), but not limited to Set here.

A channel layer (ie, the III-V channel layer described below) 118 may be disposed on the substrate 102 , for example, on the high-resistance layer 116 . The III-V group channel layer 118 may include one or more III-V group semiconductor layers, and the composition of the III-V group semiconductor layer may be GaN, AlGaN, InGaN or InAlGaN, but is not limited thereto. According to an embodiment of the present disclosure, the III-V channel layer 118 is an undoped III-V semiconductor, such as undoped GaN (undoped-GaN, u-GaN). According to other embodiments of the present disclosure, the III-V channel layer 118 may also be one or more doped III-V semiconductor layers, such as P-type III-V semiconductor layers. For the P-type III-V semiconductor layer, the dopant may be Cd, Fe, Mg or Zn, but is not limited thereto.

A barrier layer (ie, a Group 35 barrier layer described below) 120 may be disposed on the Group 35 channel layer 118 . The III-V barrier layer 120 may include one or more III-V semiconductor layers, and its composition may be different from that of the III-V body layer 104 . For example, the IIIV barrier layer 120 may include AlN, _{AlyGa (1-y)} N (0<y<1), or a combination thereof. According to an embodiment, the III-V barrier layer 120 may be an N-type III-V group semiconductor, such as an essentially N-type AlGaN layer, but is not limited thereto.

Since there is a discontinuous energy gap between the group III-V channel layer 118 and the group III-V barrier layer 120, by stacking the group III-V channel layer 118 and the group III-V barrier layer 120 on each other, electrons will The piezoelectric effect is concentrated in the III-V channel layer 118 and is adjacent to the heterojunction between the III-V channel layer 118 and the III-V barrier layer 120 . The collected electrons can form a thin layer with high carrier mobility, ie, a two-dimensional electron gas (2-DEG) region 130 .

The first compound semiconductor layer 124 may be disposed on the III-V barrier layer 120 to deplete the two-dimensional electron gas (2-DEG) region 130 to achieve a normally-off state of the semiconductor device. The first compound semiconductor layer 124 may be a P-type III-V semiconductor, such as a P-type GaN layer, but is not limited thereto. In addition, the energy gap of the first compound semiconductor layer 124 may be smaller than that of the IIIV barrier layer 120 , so that there may be discontinuous energy gaps between the first compound semiconductor layer 124 and the IIIV barrier layer 120 .

The second compound semiconductor layer 122 (eg, a P-type III-V intermediate layer) may be disposed between the III-V barrier layer 120 and the first compound semiconductor layer 124 , and the thickness of the second compound semiconductor layer 122 may be thinner than Thickness of the group III-V barrier layer 120 and the first compound semiconductor layer 124 . For example, the thickness of the second compound semiconductor layer 122 may be 20 nm, and the thicknesses of the IIIV barrier layer 120 and the first compound semiconductor layer 124 may be 50 nm and 35 nm, respectively, but not limited thereto. According to an embodiment of the present disclosure, the second compound semiconductor layer 122 is a P-type III-V semiconductor, such as a P-type GaN layer, and the dopant can be a metal dopant selected from Mg, Cd or Zn. According to an embodiment of the present disclosure, the dopant peak concentration range of the second compound semiconductor layer 122 is 9E18 (cm ⁻³ ) to 2E19 (cm ⁻³ ), and is lower than the dopant peak concentration range of the first compound semiconductor layer 124 (eg 1E19 (cm ^-3 ) to 1E20 (cm ^-3 )).

Since there is a discontinuous energy gap between the second compound semiconductor layer 122 and the III-V group barrier layer 120 , by stacking the second compound semiconductor layer 122 and the III-V group barrier layer 120 on each other, holes will be reduced due to pressure. The electrical effect is concentrated in the second compound semiconductor layer 122 and is adjacent to the heterojunction between the second compound semiconductor layer 122 and the IIIV barrier layer 120 . The aggregated holes can form a thin layer with high carrier mobility, ie, two-dimensional hole gas (2-DHG) region 132 .

The source electrode S and the drain electrode D may be electrically connected to the IIIV channel layer 118 , respectively, and the gate electrode G may be electrically connected to the first compound semiconductor layer 124 . The source electrode S and the drain electrode D may form ohmic contact with the IIIV channel layer 118, and the gate electrode G may form Schottky contact with the first compound semiconductor layer 124, but not limited thereto.

In order to analyze the concentration distribution in the semiconductor stack, secondary ion mass spectroscopy (SIMS) can be used to analyze the relationship between the concentration of metal components and the depth of the semiconductor stack as shown in Figure 1. The results are shown in Figure 2. FIG. 2 is a graph showing the relationship between dopant concentration and depth in a semiconductor stacked layer according to an embodiment of the present disclosure. As shown in FIG. 2, the curve 210 and the curve 212 are the concentration distributions of Mg and Al corresponding to different depths in the semiconductor stacked layer of an embodiment of the present disclosure, and the curve 220 and the curve 222 are respectively the semiconductor stacked layer of Comparative Example 1 ( Mg, Al in the second compound semiconductor layer 122) without the second compound semiconductor layer corresponds to the concentration distribution of different depths. Among them, the depth of 0-70 nm in Fig. 2 roughly corresponds to the first compound semiconductor layer 124 in Fig. 1, the depth of 70-85 nm roughly corresponds to the second compound semiconductor layer 122 in Fig. 1, and the depth of 85-120 nm roughly corresponds to the The group 35 barrier layer 120 with a depth of 120-140 nm roughly corresponds to the group 35 channel layer 118 in FIG. 1 . As far as the curve 210 is concerned, there is a concentration peak P2 in the depth range of 70-85 nm (that is, corresponding to the second compound semiconductor layer), and the full width half maximum (FWHM) of the concentration peak P2 is approximately 5 nm to 15 nm, and The highest concentration (or peak concentration) is approximately up to 1.5E19 cm ^-3 ; and in the depth range of 0-70 nm (that is, corresponding to the first compound semiconductor layer), there is a concentration peak P1, and the highest concentration in this interval is approximately 5E19 cm ^-3 (corresponding to a depth of 2-5 nm interval), and the lowest concentration is approximately 7E18 cm ^-3 (corresponding to a depth of 70 nm). In contrast, the Mg concentration of the curve 220 does not have any concentration peak in the depth range of 40-100 nm. It should be noted that the concentration distribution of the metal dopant shown in FIG. 2 is preferably measured by a secondary ion mass spectrometer or a detection device with a higher resolution. If the measurement is performed by a detection device with poor resolution, the concentration peak of the second compound semiconductor layer may not be measured.

In order to determine the influence of the second compound semiconductor layer on the gate delay effect in high electron mobility transistors, the threshold voltage deviation under different gate stress voltages can be further analyzed. The measurement results are shown in Section 3 picture. FIG. 3 is a graph showing the relationship between the threshold voltage deviation value and the gate voltage of Embodiments 1 and 2 and Comparative Examples 1 and 2 of the present disclosure. Please refer to Figure 1, Figure 3, and Figure 4 at the same time. The structure of Embodiment 1 in Figure 3 is similar to the structure shown in Figure 1; the structure of Embodiment 2 in Figure 3 is similar to the structure shown in Figure 4. The main difference is that the semiconductor stack does not include the second compound semiconductor layer 122, but includes a crystalline silicon compound semiconductor layer 126 disposed on the first compound semiconductor layer 124; the structure of Comparative Example 1 in FIG. 3 is in the semiconductor stack Any second compound semiconductor layer 122 is not included.

As shown in FIG. 3 , when the gate voltages are the first gate voltage V _g1 and the second gate voltage V _g1 respectively, for example, when they correspond to -6V and 6V, respectively, the high electron mobility transistor can correspond to OFF state and ON state. For Embodiment 1, when the gate voltages are the first gate voltage V _g1 and the second gate voltage V _g1 respectively, the corresponding threshold voltage deviation values are approximately equal, and the first threshold voltage deviation value ΔV The difference between ₁ and the second threshold voltage deviation value ΔV ₂ indicates that the high electron mobility transistor of Example 1 does not have a significant gate delay effect. For the second embodiment, when the gate voltage is the second gate voltage V _g2 , the corresponding threshold voltage deviation value is slightly lower than the first threshold voltage deviation value ΔV ₁ , rather than at the first threshold voltage deviation value The value between the value ΔV ₁ and the second threshold voltage deviation value ΔV ₂ indicates that the high electron mobility transistor of Example 2 has a gate delay effect in the on-state. In contrast, for Comparative Example 1, when the gate voltage is the first gate voltage V _g1 , the corresponding threshold voltage deviation value is much larger than the first threshold voltage deviation value ΔV ₁ . Therefore, the gate delay effect of Comparative Example 1 is more significant than that of Examples 1 and 2.

Those with ordinary knowledge in the technical field should easily understand that the high electron mobility transistor of the present invention may also have other aspects under the premise of meeting the requirements of actual products, which is not limited to the above. Further embodiments or variations of high electron mobility transistors are described further below. In order to simplify the description, the following description mainly focuses on the differences of the embodiments, and does not repeat the same points. Additionally, various embodiments in the present disclosure may use repeated reference symbols and/or textual notation. These repeated reference signs and notations are used for brevity and clarity of description, rather than to indicate associations between different embodiments and/or configurations.

4 is a schematic cross-sectional view of a semiconductor stack of a high-voltage semiconductor device according to an embodiment of the present disclosure, wherein the semiconductor stack at least includes a silicon compound semiconductor layer. As shown in FIG. 4, the structure 100-2 shown in FIG. 4 is similar to the structure 100-1 shown in FIG. 1, and the main difference lies in the group III-V barrier layer 120 and the first compound semiconductor layer 124 in FIG. 4 The second compound semiconductor layer 122 is not included, but the compound semiconductor layer is disposed on the first compound semiconductor layer 124 . According to an embodiment of the present disclosure, the compound semiconductor layer may be the crystalline silicon compound semiconductor layer 126 . Since the energy gap between the crystalline silicon compound semiconductor layer 126 and the first compound semiconductor layer 124 is discontinuous, holes can be more easily transferred from the gate to the first compound semiconductor layer 124 .

5 is a schematic cross-sectional view of a semiconductor stack of a high-voltage semiconductor device according to an embodiment of the present disclosure, wherein the semiconductor stack at least includes a second compound semiconductor layer and a P-type IIIV compound semiconductor layer. As shown in FIG. 5, the structure 100-3 shown in FIG. 5 is similar to the structure 100-1 shown in FIG. 1, and the main difference lies in the group III-V barrier layer 120 and the first compound semiconductor layer 124 in FIG. 5 In addition to the second compound semiconductor layer 122 , the space also includes a semiconductor capping layer disposed on the first compound semiconductor layer 124 , such as a P-type III-V group compound semiconductor layer 128 . According to an embodiment of the present disclosure, the P-type IIIV compound semiconductor layer 128 may be P ⁺ -type GaN with a high dopant concentration, which may be used to facilitate the injection of holes. Wherein, the P-type IIIV compound semiconductor layer 128 and the first compound semiconductor layer 124 may include the same metal dopant, such as Mg, and the doping concentration of the P-type IIIV compound semiconductor layer 128 is higher than that of the first compound semiconductor layer 124 doping concentration.

6 is a schematic cross-sectional view of a semiconductor stack of a high-voltage semiconductor device according to an embodiment of the present disclosure, wherein the semiconductor stack at least includes a second compound semiconductor layer and a P-type IIIV barrier layer. As shown in FIG. 6, the structure 100-4 shown in FIG. 6 is similar to the structure 100-1 shown in FIG. 1, and the main difference lies in the III-V barrier layer 120 and the first compound semiconductor layer in FIG. 6 In addition to the second compound semiconductor layer 122 , the space 124 also includes a P-type III-V group barrier layer 134 disposed between the III-V group barrier layer 120 and the second compound semiconductor layer 122 . According to an embodiment of the present disclosure, the P-type III-V barrier layer 134 may be P ^- type AlGaN with a low dopant concentration, which may be used to increase the threshold voltage (Vth) and reduce electron penetration by the III-V group barrier layer 120 degree of capture. Wherein, the P-type III-V group barrier layer 134 and the second compound semiconductor layer 122 may include the same metal dopant, such as Mg, and the doping concentration of the P-type III-V group barrier layer 134 is lower than that of the second compound semiconductor layer Doping concentration of layer 122 .

7 is a schematic cross-sectional view of a semiconductor stack of a high-voltage semiconductor device according to an embodiment of the present disclosure, wherein the semiconductor stack at least includes a second compound semiconductor layer, a P-type III-V barrier layer, and a P-type III barrier layer. Group V compound semiconductor layer. As shown in FIG. 7, the structure 100-5 shown in FIG. 7 is similar to the structure 100-1 shown in FIG. 1, and the main difference lies in the group III-V barrier layer 120 and the first compound semiconductor layer 124 in FIG. 7 In addition to the second compound semiconductor layer 122, the The P-type III-V compound semiconductor layer 128 on the material semiconductor layer 124 includes a P-type III-V barrier layer 134 disposed between the III-V barrier layer 120 and the second compound semiconductor layer 122 .

According to the above-mentioned embodiment, since the second compound semiconductor layer is disposed between the first compound semiconductor layer and the Group III-V barrier layer, by forming the concentration peak of the metal dopant in the second compound semiconductor layer, the first compound semiconductor layer can be increased. The energy barrier between the highest valence band of the two compound semiconductor layer and the highest valence band of the barrier layer. Therefore, the holes from the first compound semiconductor layer are not easily injected into the barrier layer, thereby avoiding the generation of trapped charges in the III-V barrier layer, thereby reducing the high electron mobility transistor's performance. Threshold voltage deviation. Therefore, the gate delay effect can be avoided, and the fast switching of the high electron mobility transistor is facilitated.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100-1: High Electron Mobility Transistor

102: Substrate

104: Nitride layer

106: first nitride layer

108: Second nitride layer

110: Superlattice layer

112: first superlattice layer

114: Second superlattice layer

116: High resistance layer

118: channel layer

120: Barrier layer

122: the second compound semiconductor layer

124: the first compound semiconductor layer

130: Two-dimensional electron gas region

132: Two-dimensional hole-gas region

D: drain

G: gate

S: source

Claims (13)

A high electron mobility transistor, comprising: a channel layer disposed on a substrate; a barrier layer disposed on the channel layer; a first compound semiconductor layer disposed on the barrier layer; and a first Two compound semiconductor layers are disposed between the barrier layer and the first compound semiconductor layer, wherein the first compound semiconductor layer includes a first concentration distribution of a metal dopant, and the second compound semiconductor layer includes the metal dopant A second concentration distribution of the substance, the first concentration distribution has a first peak in the first compound semiconductor layer, and the second concentration distribution has a second peak in the second compound semiconductor layer, wherein the first compound The highest concentration of the metal dopant in the first peak in the semiconductor layer is greater than the highest concentration of the metal dopant in the second peak in the second compound semiconductor layer. The high electron mobility transistor of claim 1, wherein the metal dopant is magnesium, cadmium, carbon or zinc. The high electron mobility transistor according to claim 1, wherein the concentration range of the first peak is 1E19 (cm ^-3 ) to 1E20 (cm ^-3 ), and the concentration range of the second peak is 9E18 (cm ^-3 ) to 2E19 (cm ^-3 ). The high electron mobility transistor of claim 1, wherein the second peak has a full width at half maximum (FWHM) of 5 nm to 15 nm. The high electron mobility transistor according to claim 1, wherein the channel layer is an undoped IIIV channel layer. The high electron mobility transistor of claim 1, wherein a two-dimensional electron gas (2-DEG) region is formed in the channel layer, and the two-dimensional electron gas region is adjacent to the channel layer and the barrier layer. junction. The high electron mobility transistor of claim 1, wherein the thickness of the second compound semiconductor layer is smaller than the thicknesses of the barrier layer and the first compound semiconductor layer, respectively. The high electron mobility transistor of claim 1, wherein a two-dimensional hole gas (2-DHG) region is formed in the second compound semiconductor layer, and the two-dimensional hole gas region is adjacent to the barrier layer and the junction of the second compound semiconductor layer. The high electron mobility transistor according to claim 1, further comprising a semiconductor cap layer disposed on the second compound semiconductor layer. The high electron mobility transistor of claim 9, wherein the semiconductor cap layer is a P-type cap layer, wherein the P-type cap layer and the first compound semiconductor layer include the metal dopant, and the P-type cap layer The doping concentration of the layer is higher than the doping concentration of the first compound semiconductor layer. The high electron mobility transistor of claim 1, further comprising a P-type barrier layer disposed between the barrier layer and the second compound semiconductor layer, and the P-type barrier layer includes the metal doped quality. The high electron mobility transistor of claim 11, wherein the gold of the P-type barrier layer The doping concentration of the metal dopant is lower than the doping concentration of the metal dopant of the second compound semiconductor layer. The high electron mobility transistor of claim 1, further comprising: a gate electrode electrically connected to the first compound semiconductor layer; and at least two source/drain electrodes electrically connected to the channel layer respectively.

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