TWI770425B - Method of manufacturing semiconductor device and system for manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_2nd level (first M_2nd pattern) or a first conductive pattern in the M_1st level (first M_1st pattern); determining that the candidate pattern satisfies one or more criteria; and changing a size of the candidate pattern thereby revising the layout diagram. A system for manufacturing a semiconductor device is disclosed herein.

Description

Method for manufacturing semiconductor element and for manufacturing semiconductor system of body components

This disclosure relates to a manufacturing method and system, and more particularly, to a method for manufacturing a semiconductor device and a system for manufacturing a semiconductor device.

An integrated circuit ("IC") includes one or more semiconductor elements. One way of representing semiconductor elements is through a plan view called a layout. Layout diagrams are generated in the context of design rules. A set of design rules constrains the placement of corresponding patterns in the layout, eg, geographic/spatial constraints, connection constraints, or the like. Oftentimes the set of design rules includes a subset of design rules related to spacing and other interactions between patterns in adjacent or adjacent cells, where the patterns represent conductors in layers of metallization.

Typically, a set of design rules is specific to the process technology node by which the semiconductor device will be fabricated based on the layout. The set of design rules compensates for the variability of the corresponding process technology node. This compensation increases the likelihood that the actual semiconductor elements generated from the layout will be acceptable counterparts to the virtual elements on which the layout is based.

Embodiments of the present disclosure relate to a method of fabricating a semiconductor device, including the following steps. For a layout stored on a non-transitory computer-readable medium, a semiconductor device is based on the layout including a first metallization level and a first metallization level overlying the first metallization level Two metallization levels and a first interconnection level between the first metallization level and the second metallization level, the layout corresponds to a first metallization layer in the semiconductor device overlying the first metallization level A second metallization layer of the metallization layers and a first interconnection layer between the first metallization layer and the second metallization layer to generate the layout diagram, including the following steps. selecting a candidate pattern in the layout, the candidate pattern being a first conductive pattern in the second metallization level or a first conductive pattern in the first metallization level; determining that the candidate pattern satisfies one or more and reducing the size of at least one of the candidate patterns, thereby revising the layout.

Embodiments of the present disclosure relate to a system for fabricating a semiconductor device, comprising at least one processor; and at least one memory including computer code for one or more programs; wherein the at least one memory, The computer code and the at least one processor are used to cause the system to perform the following steps. For a layout stored on a non-transitory computer-readable medium, the semiconductor device is based on the layout including a first metallization level and a first metallization level overlying the first metallization level Two metallization levels and a first interconnection level between the first metallization level and the second metallization level, the layout corresponds to a first metallization layer in the semiconductor device and overlying the first metallization level A second metallization layer of the metallization layer and a first interconnection layer between the first metallization layer and the second metallization layer, resulting in the cloth The layout diagram includes the following steps. selecting a candidate pattern in the layout, the candidate pattern being a first conductive pattern in the second metallization level or a first conductive pattern in the first metallization level; determining that the candidate pattern satisfies one or more and changing a size of the candidate pattern, thereby revising the layout; wherein the layout further includes a transistor level, the transistor level corresponding to a transistor layer in the semiconductor device; and in the first There is no metallization level between a metallization level and the transistor layer.

Embodiments of the present disclosure relate to a method of fabricating a semiconductor device, including the following steps. For a layout stored on a non-transitory computer-readable medium, the semiconductor device is based on the layout including a first metallization level and a first metallization level overlying the first metallization level Two metallization levels and a first interconnection level between the first metallization level and the second metallization level, the layout corresponds to a first metallization layer in the semiconductor device and overlying the first metallization level A second metallization layer of the metallization layer and a first interconnection layer between the first metallization layer and the second metallization layer, generating the layout diagram, includes the following steps. selecting a candidate pattern in the layout, the candidate pattern being a first conductive pattern in the first metallization level; determining that the candidate pattern satisfies one or more criteria; and increasing a size of the candidate pattern, thereby Revise the layout.

100: Semiconductor Components

101: Circuit Macros

102: Columns

104: Unit area

200A: Layout Diagram

200B: Layout Diagram

200C: Layout Diagram

200D: Layout Diagram

200E: Layout Diagram

200F: Layout Diagram

202: Column

203N: Subcolumn

203P: Subcolumn

204(1)(A): Unit

204(1)(B): Unit

204(2)(C): Unit

204(2)(D): Unit

204(3)(E): Unit

204(3)(F): Unit

208N: Active area pattern

208P: Main area pattern

210(1): MD pattern

210(2): MD Pattern

210(3): MD pattern

210(4): MD Pattern

210(5): MD Pattern

210(6): MD Pattern

210(7): MD Pattern

210(8): MD Pattern

210(9): MD Pattern

210(10): MD Pattern

210(11): MD Pattern

210(12): MD Pattern

210(13): MD Pattern

210(14): MD Pattern

210(15): MD Pattern

210(16): MD Pattern

210(17): MD Pattern

210(18): MD Pattern

210(19): MD Pattern

210(20): MD Pattern

212(1): Gate pattern

212(2): Gate pattern

212(3): Gate pattern

212(4): Gate pattern

212(5): Gate pattern

212(6): Gate pattern

214(1): Gate pattern

214(2): Gate pattern

214(3): Gate pattern

214(4): Gate pattern

214(5): Gate pattern

214(6): Gate pattern

214(7): Gate pattern

214(8): Gate pattern

214(9): Gate pattern

214(10): Gate pattern

214(11): Gate pattern

214(12): Gate pattern

216(1): VGD pattern

216(2): VGD pattern

216(3): VGD pattern

216(4): VGD pattern

216(5): VGD pattern

216(6): VGD pattern

216(7): VGD pattern

216(8): VGD pattern

216(9): VGD pattern

216(10): VGD pattern

216(11): VGD pattern

216(12): VGD pattern

216(13): VGD pattern

216(14): VGD pattern

216(15): VGD pattern

216(16): VGD pattern

216(17): VGD pattern

216(18): VGD pattern

216(19): VGD pattern

216(20): VGD pattern

216(21): VGD pattern

216(22): VGD pattern

216(23): VGD pattern

218(1): M0 pattern

218(2): M0 pattern

218(3): M0 pattern

218(4): M0 pattern

218(5): M0 pattern

218(6): M0 pattern

218(7): M0 pattern

218(8): M0 pattern

218(9): M0 pattern

218(10): M0 pattern

218(11): M0 pattern

218(12): M0 pattern

218(12)': Dotted shape

218(13): M0 pattern

218(14): M0 pattern

218(14)': Dotted shape

218(15): M0 pattern

218(16): M0 pattern

218(17): M0 pattern

218(18): M0 pattern

218(19): M0 pattern

218(20): M0 pattern

218(20)': M0 pattern

218(21): M0 pattern

220(1): VIA0 pattern

220(1)': Dotted shape

220(2): VIA0 pattern

220(3): VIA0 pattern

220(3)': Dotted shape

220(4): VIA0 pattern

220(4)': Dotted shape

220(5): VIA0 pattern

222(1): M1 pattern

222(2): M1 pattern

222(3): M1 pattern

222(4): M1 pattern

230: Side Border

232: Gap

300A: Layout Diagram

300B: Layout Diagram

300C: Layout Diagram

300D: Layout Diagram

300E: Layout Diagram

300F: Layout Diagram

300G: Layout Diagram

300H: Layout drawing

304(1)(A): Unit

304(1)(B): Unit

304(2)(C): Unit

304(2)(D): Unit

312(1): Gate pattern

312(2): Gate pattern

314(1): Gate pattern

314(2): Gate pattern

316(1): VGD pattern

318(1): VGD pattern

318(1)(A): M0 pattern

318(2): M0 pattern

318(2)(C): M0 pattern

318(2)(D): M0 pattern

318(3)(E): M0 pattern

318(3)(F): M0 pattern

318(4)(G): M0 pattern

318(4)(H): M0 pattern

320(1): VIA0 pattern

336(1):OH/width

336(2):OH/width

336(3):OH/width

336(4):OH/width

338(1): Part III

338(1)': Dotted shape

338(2): Part V

338(2)': Dotted shape

338(3)': Dotted shape

338(4)': Dotted shape

400A: Cross-sectional view

400B: Cross-sectional view

400C: Cross-sectional view

400D: Cross-sectional view

410(2): MD structure

410(3): MD structure

412(1): Gate structure

412(2): Gate structure

416(2): VGD structure

416(3): VGD structure

418(2): Conductive M0 segment

418(4): Conductive M0 segment

418(5): VGD structure

420(1): VIA0 pattern

420(1)': Dotted shape

420(2): VIA0 structure

422(1): Conductive M1 segment

422(1)': Dotted shape

422(2): M1 segment

422(2)': Dotted shape

422(3): M1 segment

450:ILD

452: Transistor layer

454: M0 floor

456: V0 layer

458: M1 floor

460: Interlayer Dielectric Layer (ILD)

462:ILD

464:ILD

466:ILD

468:ILD

500: Method

502: Blocks

504: Blocks

602: Blocks

604: Square

606: Blocks

610: Square

612: Square

620: Square

622: Square

630: Square

632: Square

640: Square

642: Square

650: Square

652: Square

660: Square

662: Square

670: Square

672: Square

674: Square

676: Square

678: Square

680: Square

682: Square

700: Electronic Design Automation (EDA) Systems

702: Hardware Processor

704: Non-transitory computer-readable storage medium

706: Computer code

707: Library

708: Busbar

710: I/O interface

712: Web Interface

714: Internet

742: User Interface (UI)

800: Integrated Circuit (IC) Manufacturing Systems

820: Design Studio

822: IC Design Layout

830: Mask Room

832: Data preparation

844: Mask Making

845: Mask

850: IC Manufacturer/Manufacturer ("Fab")

852: Wafer Fabrication

853: Semiconductor Wafers

860: IC Components

Aspects of embodiments of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that according to industry standards Quasi-practical, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

Figure 1 is a block diagram according to some embodiments.

Figures 2A-2F are corresponding layout views 200A-200F according to some embodiments.

3A-3H are corresponding layout diagrams 300A- 300H according to some embodiments.

Figures 4A-4D are corresponding cross-sectional views 400A-400D according to some embodiments.

Figure 5 is a flow diagram of a method according to some embodiments.

6A-6E are corresponding flowcharts of corresponding methods according to some embodiments.

7 is a block diagram of an electronic design automation (EDA) system in accordance with some embodiments.

8 is a block diagram of an integrated circuit (IC) fabrication system and an IC fabrication flow associated therewith, in accordance with some embodiments.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like are described below to simplify embodiments of the present disclosure. Of course, these are only examples and are not intended to be limiting. Other components, values, operations, materials, arrangements or the like are contemplated. For example, in the following description a first feature is formed over or over a second feature Embodiments may be included in which the first feature and the second feature are formed in direct contact, and may also be included in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact Example. Additionally, embodiments of the present disclosure may repeat reference numerals and/or letters in various instances. This repetition is for the purpose of simplicity and clarity, and does not in itself represent a relationship between the various embodiments and/or configurations discussed.

Additionally, for simplicity of description, spatially relative terms such as "below," "below," "lower," "above," "upper," and similar terms may be used herein, to describe the relationship of one element or feature to another (other) element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

For some embodiments, generating the layout includes: selecting a candidate pattern in the layout, eg, an M1 pattern or an M0 pattern; determining whether the candidate pattern satisfies one or more criteria; and changing the size of the candidate pattern to thereby revise the layout Figure, thereby improving M0 routing resources. In some embodiments, the context in which the layout diagram is generated is the first design rule (design rule 1), design rule 2, design rule 3, or design rule 4. In some embodiments where the context is design rule 3, the size of the candidate pattern is changed by reducing the size of the candidate pattern. In some embodiments where the context is Design Rule 1 or Design Rule 2, the size of the candidate pattern is changed by removing the candidate pattern from the layout Small. In some embodiments where the context is design rule 4, the size of the candidate pattern is changed by increasing the size of the candidate pattern.

FIG. 1 is a block diagram of a semiconductor device 100 according to some embodiments.

In FIG. 1, a semiconductor element 100 includes, among other things, a circuit macro (hereinafter, a macro) 101 . In some embodiments, macro 101 is a logical macro. In some embodiments, macro 101 is an SRAM macro. In some embodiments, macros 101 are macros other than logic macros or SRAM macros. The macro 101 includes, among other things, one or more cell areas 104 arranged in a presentation 102 . In some embodiments, each cell region 104 is implemented based on a layout map generated by one or more of the design rules disclosed herein, and thus each cell region 104 has improved M0 routing resources.

2A-2B are corresponding layout diagrams 200A-200B according to some embodiments.

Layout 200A represents an initial layout, and layout 200B represents a corresponding layout produced by one or more of the methods disclosed herein, according to some embodiments.

Figures 2A to 2B assume an orthogonal XYZ coordinate system, wherein the X-axis, Y-axis and Z-axis represent corresponding first, second and third directions. In some embodiments, the first, second and third directions correspond to a different orthogonal coordinate system than the XYZ coordinate system.

In Figure 2A, floor plan 200A includes cell 204(1)(A). Cell 204(1)(A) represents a semiconductor based on layout 200A Cell area in a bulk element. Cells 204(1)(A) are arranged in rows 202 that extend generally in a first direction (extend horizontally). Although not shown for simplicity of illustration, in some embodiments, column 202 includes additional instances of cells, eg, cell 204(1)(A) and/or other cells. Column 202 includes sub-columns 203N and 203P.

The layout diagram 200A further includes: active area patterns 208P and 208N; MD patterns 210(1), 210(2), 210(3), 210(4), 210(5), 210(6), 210(7), 210(8), 210(9), 210(10) and 210(11): gate patterns 212(1), 212(2), 212(3), 212(4), 212(5), 214( 1), 214(2), 214(3) and 214(4); VGD patterns 216(1), 216(2), 216(3), 216(4), 216(5), 216(6), 216(7), 216(8), 216(9), 216(10), 216(11) and 216(12); M0 patterns 218(1), 218(2), 218(3), 218(4 ), 218(5), 218(6), 218(7), 218(8) and 218(9): VIA0 pattern (also referred to as V0 pattern, as shown in Figures 2A to 2F, Figures 3A to 3H and 4A to 4D) 220(1), 220(2), 220(3), 220(4), and 220(5); and M1 patterns 222(1), 222( 2), 222(3) and 222(4). In some embodiments, cell 204(1)(A) includes: active area patterns 208P and 208N; MD patterns 210(1)-210(11); gate patterns 212(1)-214(4); VGD patterns 216(1) to 216(12); M0 patterns 218(2) to 218(8); portions of M0 patterns 218(1) and 218(9); VIA0 patterns 220(1) to 220(5); and M1 Patterns 222(1) to 222(4).

In the example of FIG. 2A, it is assumed that the M0 patterns 218(1) and 218(9) are power grid (PG) patterns, and these power grid (PG) patterns Represents the corresponding conductors in the grid of the semiconductor element fabricated based on the layout 200A: and the M0 patterns 218(2) to 218(8) are wiring patterns that represent non-PG conductors of the semiconductor element fabricated based on the layout 200A. In some embodiments, PG pattern 218(1) is designated to provide a first system reference voltage, and PG pattern 218(9) is designated to provide a second system reference voltage. In Figure 2A, PG pattern 218(1) is designated to provide VDD, and PG pattern 218(9) is designated to provide VSS. In some embodiments, PG pattern 218(1) is designated to provide VSS and PG pattern 218(9) is designated to provide VDD. In some embodiments, PG patterns 218(1) and 218(9) are designated to provide corresponding voltages other than VDD and VSS, respectively, or VSS and VDD, respectively.

Active area patterns 208P and 208N, MD patterns 210(1) to 210(11), gate patterns 212(1) to 212(5) and 214(1) to 214(4), and VGD patterns 216(1) to 216 (2) Included in the transistor level of the layout diagram 200A, which corresponds to the transistor layer of the semiconductor device based on the layout diagram 200A. The M0 patterns 218(1) to 218(9) are included in the metallization level M0 in the layout diagram 200A, which corresponds to the metallization layer M0 of the semiconductor device based on the layout diagram 200A. The VIA0 patterns 220(1) to 210(5) are included in the interconnection level V0 in the layout diagram 200A, which corresponds to the interconnection level V0 of the semiconductor element based on the layout diagram 200A. The M1 patterns 222(1) to 222(4) are included in the M1 metallization level, which corresponds to the metallization layer M1 of the semiconductor device based on the layout diagram 200A.

MD patterns 210(1) to 210(11) and gate patterns 212(1) to 212(5) and 214(1) to 214(4) are located over corresponding portions of active area patterns 208P and 208N. In some embodiments, active area patterns 208P and 208N are located over substrate patterns (not shown). VGD patterns 216(1)-216(12) are located over corresponding portions of MD patterns 210(1)-210(7) and 210(11) and gate patterns 212(1)-212(5). M0 patterns 218(1)-218(9) overlie corresponding VGD patterns 216(1)-216(12). VIA0 patterns 220(1)-220(5) are located over corresponding M0 patterns 218(2)-218(5) and 218(7). The M1 patterns 222(1) to 222(4) are located over the corresponding VIA0 patterns 220(1) to 220(5).

The floor plan 200A assumes a corresponding semiconductor technology process node that includes various design rules for generating the floor plan. The layout diagram 200A further assumes that the design rules follow a numbering convention, with the first level of metallization (M_1st) and the corresponding first level of interconnect structure (V_1st) referred to as M0 and V0, respectively. The levels M0 and V0 of the layout diagram 200A correspondingly represent the metallization layer M0 and the interconnect structure layer V0 in the semiconductor device based on the layout diagram 200A. In some embodiments, the numbering convention assumes that the M_1st level and the V_1st level are referred to as M1 and V1, respectively.

Active area patterns 208P and 208N and M0 patterns 218(1)-218(9) have corresponding long axes extending generally along the X-axis (extending horizontally). MD patterns 210(1) to 210(11), gate patterns 212(1) to 212(5) and 214(1) to 214(4), and M1 patterns 222(1) to 222(4) have substantially upper edges The Y axis extends (extends vertically) to the corresponding long axis.

In FIG. 2A, active region patterns 208P and 208N represent corresponding PMOS and NMOS fins in a semiconductor device based on layout diagram 200A. Accordingly, active region patterns 208P and 208N are designated for corresponding PMOS finFET and NMOS finFET configurations and are referred to as corresponding fin patterns 208P and 208N. In some embodiments, fin patterns 208P and 208N are designated for PMOS and NMOS configurations, respectively. Although not shown for simplicity of illustration, in some embodiments, each of sub-columns 203N and 203P includes two or more fin patterns designated for PMOS finFET and NMOS finFET configurations, respectively . In some embodiments, active area patterns 208P and 208N are designated for a planar transistor configuration, and thus represent corresponding active areas in the cell area based on cell 204(1)(A). In some embodiments, active area patterns 208P and 208N are designated for nanowire configurations. In some embodiments, active area patterns 208P and 208N are designated for nanochip configurations. In some embodiments, active area patterns 208P and 208N are designated for a Gate-All-Around (GAA) configuration. In some embodiments in which the active regions are referred to as oxide-dimensioned (OD) regions, the active region patterns 208P and 208N are referred to as corresponding OD patterns 208P and 208N.

In layout 200A, MD patterns 210(1) to 210(11) represent corresponding MD conductive structures in the transistor layers of the semiconductor device based on layout 200A. Gate patterns 212(1) to 212(5) and 214(1) to 214(4) represent corresponding gate structures in the transistor layers of the semiconductor device based on layout diagram 200A. VGD patterns 216(1) through 216(12) represent cloth-based Figure 200A shows the corresponding VG or VD structure in the transistor layer of the semiconductor device. The VG structure (see Figure 4B) electrically couples the gate structure to the corresponding M0 conductive segment. The VD structure (see Figure 4A) electrically couples the drain/source structure to the corresponding M0 conductive segment. The M0 patterns 218(1) to 218(9) represent corresponding conductive segments in the metallization layer M0 of the semiconductor device based on the layout diagram 200A. VIA0 patterns 220( 1 ) to 220( 5 ) represent corresponding interconnect structures (eg, vias) in the interconnect layer V0 of the semiconductor device based on the layout diagram 200A. The M1 patterns 222(1) to 222(4) represent corresponding conductive segments in the metallization layer M1 of the semiconductor device based on the layout diagram 200A.

In Figure 2A, gate patterns 212(1) to 212(5) are included in cell 204(1)(A). With respect to the X-axis, gate patterns 214(1)-212(4) are included in cell 204(1)(A). With respect to the Y-axis, gate patterns 214(1) and 214(3) are generally collinear, and gate patterns 214(2) and 214(4) are generally collinear. In some embodiments (not shown), gate patterns 214(1) and 214(3) are merged and covered by a cut pattern that (actually) results in a corresponding gate pattern 214(1) and 214 (3) Two discrete gate patterns. In some embodiments (not shown), gate patterns 214(2) and 214(4) are merged and covered by a cut pattern that (in effect) results in gate patterns 214(2) and 214 corresponding to (4) Two discrete gate patterns.

With respect to layout diagram 200A, in some embodiments, gate patterns 212(1)-212(5) are active gate patterns. In some embodiments, gate patterns 214(1)-214(4) are designated as active or dummy gate patterns, respectively. In some embodiments, depending on the corresponding active area pattern 208P and 208N is substantially continuous or substantially discontinuous relative to the X-axis at the lateral boundaries of cell 204(1)(A), gate patterns 212(1)-212(5) and 214(1)-214(4 ) are correspondingly designated as active or dummy gate patterns. In some embodiments, where the active region pattern is substantially continuous at the side boundaries of cell 204(1)(A), this configuration is referred to as a continuous oxide diffusion (CNOD) configuration. In some embodiments where there is a CNOD configuration, the area of the active area pattern covering the side boundaries of the cell is designated for doping, which results in a corresponding fill area in the semiconductor element. In some embodiments, where the active region pattern is substantially discontinuous at the side boundaries of cell 204(1)(A), this configuration is referred to as continuous poly over diffusion edge (CPODE) ) configuration. In some embodiments where there is a CPODE configuration, an insulator pattern (not shown) is placed over the region representing the disconnection of the active region pattern at the side boundaries of the cell. In some embodiments, the active gate pattern is designated to receive signals regarding the function of the circuit represented by cell 204(1)(A). In some embodiments, with respect to the X-axis, the dummy gate pattern represents a dummy gate structure that helps provide the cell region corresponding to cell 204(1)(A) with adjacent (eg, contiguous) cells Isolation between regions (not shown). In some embodiments, the dummy gate structure is used to float, so the dummy gate pattern is correspondingly designated as floating, eg, in the case of a CPODE configuration. In some embodiments, with respect to the X-axis, the dummy gate structure is used to receive a voltage that inhibits conduction in the underlying portion of the corresponding fin, eg, inhibits the inversion layer in the underlying portion of the corresponding fin, so dummy The gate pattern is correspondingly designated to receive the conduction suppression voltage.

The gate patterns 212(1) to 212(5) and 214(1) to 214(4) are separated by a distance (uniform distance) with respect to the X-axis. In some embodiments, the uniform distance represents a contacted poly pitch (CPP) corresponding to a semiconductor technology process generation, eg, gate patterns 214(1) and 212(1) are separated by a CPP. Thus, cell 204(1) has a width of 6 CPPs relative to the X-axis.

Cell 204(1)(A) represents a circuit. In some embodiments, unit 204(1)(A) represents a circuit that provides functionality. In some embodiments, cell 204(1)(A) represents a circuit that provides logic functionality, and is thus referred to as a logic cell. In some embodiments, cell 204(1)(A) represents a logical function AND, eg, a four-input AND (AND4). In some embodiments, at least one of cells 204(1)-204(2) represents a circuit that provides functionality other than logic functionality.

In the example of FIG. 2A, cell 204(1)(A) has input labels A1, A2, A3, and A4, and output label Z, which labels indicate that in the semiconductor element corresponding to cell 204(1)(A) The corresponding input signals A1, A2, A3 and A4 and the output signal Z of the unit area. Input label A1 is graphically coupled to the gate via a graphical path including gate pattern 212(1), VGD pattern 216(2), M0 pattern 218(4), VIA0 pattern 220(1), and M1 pattern 222(1). Pole pattern 212(1). Input label A2 is graphically coupled to the gate via a graphical path including gate pattern 212(2), VGD pattern 216(9), M0 pattern 218(6), VIA0 pattern 220(4), and M1 pattern 222(2). Pole pattern 212(2). Input label A3 is diagrammatically via a diagrammatic path including gate pattern 212(3), VGD pattern 216(4), and M0 pattern 218(5). is coupled to the gate pattern 212(3). Input label A4 is diagrammatically coupled to gate pattern 212(4) via a diagrammatic path including gate pattern 212(4), VGD pattern 216(10), and M0 pattern 218(7). Output marker Z is graphically coupled to the MD pattern via a graphical path including MD pattern 210(6), VGD pattern 216(7), M0 pattern 218(3), VIA0 pattern 220(3), and M1 pattern 222(4). 210(6).

Recall that layout diagram 200A represents an initial layout diagram, and also recall that layout diagram 200B represents a corresponding layout diagram produced by one or more of the methods disclosed herein, in accordance with some embodiments. More specifically, cell 204(1)(B) of floorplan 200B represents that a method including a first design rule (Design Rule 1) (discussed below) has been applied to floorplan 200A in accordance with some embodiments. An example of a cell region corresponding to cell 204(1)(B) is cell region 104 of FIG. 1 .

The floor plan 200B is similar to the floor plan 200A. Figure 2B follows a similar numbering convention to that of Figure 2A. For the sake of brevity, the discussion will focus more on the differences between Figure 2B and Figure 2A than on the similarities.

In Figure 2B, compared to Figure 2A, some of the patterns have been removed. In particular, VIA0 patterns 220(1), 220(4), and 220(3) of FIG. 2A have been removed in FIG. 2B, such as by the corresponding dotted line shapes 220(1)', 220(4) ' and 220(3)'. Also, the M1 patterns 222(1), 222(2), and 222(4) of FIG. 2A have been removed in FIG. 2B, such as by the corresponding dotted line shapes 222(1)', 222(2)' and 222(4)'.

In some embodiments, Design Rule 1 is as follows: If a unique VIA0 pattern is covered by a given M1 pattern, then this given M1 pattern is removed. More specifically, a given M1 pattern is part of a graphical path that includes the given M1 pattern, a unique VIA0 pattern, and a corresponding underlying M0 pattern.

In some embodiments, Design Rule 1 is as follows: For the first M1 pattern designated as the pinhole pattern, if the first VIA0 pattern is the only VIA0 pattern covered by the first M1 pattern, then remove the first M1 pattern And instead designate the corresponding underlying first M0 pattern as the nail hole pattern.

In some embodiments, designation as a pin hole pattern should be understood as follows: For a first conductive pattern in a first metallization level M_1st having a corresponding overlying first interconnect level V_1st, the first conductive pattern is designated as The pinhole pattern indicates that there are at least first and second allowable overlying locations for the corresponding first via pattern in level V_1st at which one of the second metallization levels exists. At least corresponding second and third conductive patterns may be positioned to cover the first via pattern. For example, for the first M0 pattern and the corresponding overlying first VIA0 pattern, if the first VIA0 pattern has multiple locations (where the corresponding M1 pattern can be positioned to cover the first VIA0 pattern) , the first M0 pattern is designated as the pinhole pattern. For example, for the first M1 pattern and the corresponding overlying first VIA1 pattern (also referred to as the V1 pattern), if the first VIA1 pattern has multiple locations at which the corresponding M2 pattern can be positioned to cover the first VIA1 pattern), the first M1 pattern is designated as the pinhole pattern. In some embodiments, the relationship of a given M0/M1 pattern relative to an overlying pattern is analyzed to decide whether to designate a given M0/M1 as a pinhole pattern. In some embodiments, referred to The state given as a pinhole pattern is a property associated with a given M0/M1 pattern such that examining the properties of a given M1 pattern reveals whether the given M1 pattern is a pinhole pattern.

In Figure 2A, M1 patterns 222(1), 222(2), and 222(4) and M0 patterns 218(5) and 218(7) are designated as pinhole patterns. Thus, regarding the M1 pattern 222(1), the corresponding via pattern VIA1(1) (not shown in the figure) has a plurality of allowable overlying positions, and at these positions, the corresponding M2 pattern (not shown in the figure) can be is positioned to cover the via pattern VIA1(1). Regarding the M1 pattern 222(2), the corresponding via pattern VIA1(2) (not shown) has a number of allowable overlying positions at which the corresponding M2 pattern (not shown) can be positioned A pattern VIA1(2) covering the via is formed. Regarding the M1 pattern 222(4), there are a number of allowable overlying positions corresponding to the via pattern VIA1(3) (not shown), which may be positioned to cover the via pattern VIA1(3).

In layout diagram 200A, among the M1 patterns designated as pinhole patterns, each of M1 patterns 222(1), 222(2), and 222(4) covers only one VIA0 pattern (ie, the corresponding VIA0 patterns 220(1), 220(4) and 220(3)). Thus, Design Rule 1 applies to each of M1 patterns 222(1), 222(2), and 222(4).

The result of applying Design Rule 1 to Figure 2A is shown in Figure 2B. Cell 204(1)(B) of floorplan 200B is the result of applying the method including Design Rule 1 to floorplan 200A, and more specifically to M1 patterns 222(1), 222(2), and 222( 4). The results of applying Design Rule 1 to Figure 2A include: VIA0 pattern 220(1) has been removed from Figure 2B, 220(4) and 220(3) and M1 patterns 222(1), 222(2) and 222(4), as indicated by the corresponding dashed shapes 220(1)', 220(4)', 220(3)' , 222(1)', 222(2)' and 222(4)'; and M0 patterns 218(4), 218(6), 218(5), 218(7) and 218(3) have been designated As a nail hole pattern.

In Figure 2B, designation of M0 pattern 218(4) as the pinhole pattern indicates that there are multiple permissible overlying locations corresponding to via pattern 220(1)" (not shown), at which locations, A corresponding M1 pattern (eg, 220(1)") (not shown) may be positioned to cover the via pattern 220(1)". In Figure 2B, the M0 pattern 218(6) is designated as the pinhole pattern Indicates that the corresponding via pattern 220(4)" (not shown) has a number of allowable overlying positions at which the corresponding M1 pattern (eg, 222(2)") (not shown) ) may be positioned to cover the via pattern 220(4)". In Figure 2B, the designation of the M0 pattern 218(5) as the pinhole pattern indicates that the corresponding via pattern VIA(4) (not shown) has a number of allowable overlying positions at which the corresponding The M1 pattern (not shown) may be positioned to cover the via pattern VIA(4). In Figure 2B, the designation of the M0 pattern 218(7) as the pinhole pattern indicates that the corresponding via pattern VIA(5) (not shown) has a number of allowable overlying positions at which the corresponding The M1 pattern (not shown) may be positioned to cover the via pattern VIA(5). In Figure 2B, the designation of the M0 pattern 218(3) as the pinhole pattern indicates that the corresponding via pattern 220(3)" (not shown) has a number of allowable overlying locations, at which locations, A corresponding M1 pattern (eg, 222(4)") (not shown) may be positioned to cover the via pattern 220(4)".

3%)至(

4%)。 With M1 patterns 222(1), 222(2), and 222(4) and VIA0 patterns 220(1), 220(4), and 220(3) removed, layout 200B is compared to layout 200A. Not congested. Layout 200B has Improved M1 routing resources. In some embodiments, because floorplan 200B has fewer M1 patterns than floorplan 200A, floorplan 200B is considered to have improved routing resources relative to floorplan 200A. In some embodiments, reduced congestion in level M1 results in reduced congestion in level M2. In some embodiments, congestion is reduced in level M2 (

3%) to (

4%).

Figures 2C to 2D are corresponding layout views 200C to 200D according to some embodiments.

Layout 200C represents an initial layout, and layout 200D represents a corresponding layout produced by one or more of the methods disclosed herein, according to some embodiments. More specifically, cell 204(2)(D) of floorplan 200D represents that a method including a second design rule (Design Rule 2) (discussed below) has been applied to floorplan 200C in accordance with some embodiments. An example of a cell region corresponding to cell 204(2)(D) is cell region 104 of FIG. 1 .

The layout diagrams 200C to 200D are similar to the layout diagrams 200A to 200B of the corresponding FIGS. 2A to 2B . Figures 2C-2D follow a similar numbering convention to that of Figures 2A-2B. Although corresponding, some parts are different. To help identify corresponding but still different parts, the numbering convention uses bracket numbers. For example, the pattern in Figure 2C 218(10) and pattern 218(1) in Figure 2B are both M0 patterns, where the similarities are reflected in the common root 218(_), and where the differences are reflected in the brackets _(10) and _(1) . For the sake of brevity, the discussion will focus more on the differences between Figures 2C-2D and Figures 2A-2B than on the similarities.

In Figure 2C, floorplan 200C includes cell 204(2)(C). The layout diagram 200C further includes: MD patterns 210(10), 210(11), 210(12), 210(13), 210(14) and 210(15); gate patterns 212(6), 214(5) , 214(6), 214(7), and 214(8); VGD patterns 216(3), 216(14), 216(15), and 216(16); and M0 patterns 218(10), 218(11) , 218(12), 218(13), 218(14) and 218(15). For simplicity of description, (except for other patterns), the fin pattern and the M1 pattern are omitted from FIGS. 2C to 2D. In some embodiments, cell 204(2)(C) includes: MD patterns 210(10)-210(15); gate patterns 212(6) and 214(5)-214(8); VGD patterns 216( 13) to 216(16): M0 pattern 218(11) to 218(14): and portions 218(10) and 218(15) of the M0 pattern.

In some embodiments, cells 204(2)(C) and 204(2)(D) corresponding to Figures 2C and 2D are inversion cells representing corresponding inversion circuits.

In Figure 2D, compared to Figure 2C, some patterns have been removed. In particular, the M0 patterns 218(12) and 218(14) of Fig. 2C have been removed in Fig. 2D, as shown by the corresponding dashed shapes 218(12)' and 218(14)' in Fig. 2D indicated.

In some embodiments, design rule 2 is as follows: if a given M0 pattern does not cover one or more VGD contact patterns and if a given M0 pattern does not cover one or more V0 contact patterns, remove a given M0 pattern. More specifically, a given M0 pattern is not part of a diagrammatic path that includes a given M0 pattern and one or more VGD patterns, nor is a given M0 pattern part of a diagrammatic path that includes a given M0 pattern and one or more VIA0 patterns. part.

In Figure 2C, M0 pattern 218(12) is not covered by one or more VGD contact patterns, and M0 pattern 218(12) is not covered by one or more V0 contact patterns. Therefore, Design Rule 2 applies to the M0 pattern 218(12). Similarly, in Figure 2C, M0 pattern 218(14) is not covered by one or more VGD contact patterns, and M0 pattern 218(14) is not covered by one or more V0 contact patterns. Therefore, Design Rule 2 applies to the M0 pattern 218(14).

The result of applying Design Rule 2 to Figure 2C is shown in Figure 2D. Cell 204(2)(D) of floorplan 200D is the result of applying the method including Design Rule 2 to floorplan 200C, and more specifically to M0 patterns 218(12) and 218(14). The results of applying Design Rule 2 to Figure 2C include: the M0 pattern 218(12) has been removed from Figure 2D, as indicated by the corresponding dashed shape 218(12)' in Figure 2D; The figure removes the M0 pattern 218(14), as indicated by the corresponding dashed shape 218(14)' in the 2D figure.

With M0 patterns 218(12) and 218(4) removed, layout 200D is less congested than layout 200C. With M0 patterns 218(12) and 218(4) removed, floorplan 200D has improved M0 routing resources compared to floorplan 200C. In some embodiments, because the layout 200D has fewer M0 patterns than floorplan 200C, so floorplan 200D is considered to have improved M0 routing resources relative to floorplan 200C.

Figures 2E-2F are corresponding layout views 200E-200F according to some embodiments.

Floorplan 200E represents an initial floorplan, and floorplan 200F represents a corresponding floorplan generated by one or more of the methods disclosed herein, in accordance with some embodiments. More specifically, cell 204(3)(F) of floorplan 200F represents that a method including a third design rule (Design Rule 3) (discussed below) has been applied to floorplan 200E in accordance with some embodiments. An example of a cell region corresponding to cell 204(3)(F) is cell region 104 of FIG. 1 .

The layout diagrams 200E to 200F are similar to the layout diagrams 200A to 200D of the corresponding Figures 2A to 2D. Figures 2E-2F follow a similar numbering convention to that of Figures 2A-2D. Although corresponding, some parts are different. To help identify corresponding but still different parts, the numbering convention uses bracket numbers. For example, pattern 218(16) in Fig. 2E and pattern 218(10) in Fig. 2D are both M0 patterns, where the similarities are reflected in the common root 218(_), and where the differences are reflected in parentheses _(16) and _(10). For the sake of brevity, the discussion will focus more on the differences between Figures 2E-2F and Figures 2A-2D than on the similarities.

In Figure 2E, floorplan 200E includes cell 204(3)(E). The layout diagram 200E further includes: MD patterns 210(17), 210(18), 210(19), 210(20) and 210(21); gate patterns 212(7), 212(8), 214(9) , 214(10), 214(11) and 214(12); VGD patterns 216(17), 216(18), 216(19), 216(20), 216(21), 216(22) and 216(23); and M0 patterns 218(16), 218(17), 218(18), 218(19), 218(20) and 218(21). For simplicity of description, (except for other patterns), the fin pattern, the VIA0 pattern, and the M1 pattern are omitted from FIGS. 2C to 2D. In some embodiments, cell 204(3)(E) includes: MD patterns 210(17)-210(21); gate patterns 212(7)-212(8) and 214(9)-214(12) : VGD patterns 216(17) to 216(23); M0 patterns 218(17) to 218(20): and portions of M0 patterns 218(16) and 218(21).

Element 204(3)(E) represents a circuit. In some embodiments, unit 204(3)(E) represents a circuit that provides functionality. In some embodiments, cell 204(3)(E) represents a circuit that provides logic functionality, and is thus referred to as a logic cell. In some embodiments, cell 204(3)(E) represents a logical function NAND, eg, a two-input NAND (NAND2).

CPP，且因此緊鄰之MD圖案彼此相距一個軌道。在一些實施例中，軌道間距(PT)為PT

½CPP，且因此緊鄰之MD圖案彼此相距兩個軌道。在一些實施例中，相對於X軸，每一MD圖案(例如，MD圖案210(1))之寬度為WMD

CPP。 In the layout diagram 200E, the MD patterns 210(17) to 210(21) are arranged relative to the X-axis according to a grid of virtual tracks substantially parallel to the Y-axis. In some embodiments, the pitch of tracks (PT) is PT with respect to the X-axis

The CPP, and thus the immediately adjacent MD patterns, are one track apart from each other. In some embodiments, the track pitch (PT) is PT

½ CPP, and therefore immediately adjacent MD patterns are two tracks apart from each other. In some embodiments, the width of each MD pattern (eg, MD pattern 210(1)) is WMD relative to the X-axis

CPP.

CPP之一些實施例中，對應MD圖案210(15)及210(18)之長軸 大體上與第一軌道共線，MD圖案210(16)及210(19)之長軸大體上與第二軌道共線，且對應MD圖案210(17)及210(19)之長軸大體上與第三(且最後)軌道共線。 Relative to the X-axis, where the track pitch (PT) is PT

In some embodiments of the CPP, the long axes of the corresponding MD patterns 210(15) and 210(18) are substantially collinear with the first track, and the long axes of the MD patterns 210(16) and 210(19) are substantially in line with the second track. The tracks are collinear, and the major axes of the corresponding MD patterns 210(17) and 210(19) are generally collinear with the third (and last) track.

CPP之一些實施例中，軌道界定MD行(MD-column)。如此，MD圖案210(15)及210(18)位於第一MD行中，MD圖案210(16)及210(19)位於第二MD行中，且MD圖案210(17)及210(19)位於第三(且最後)MD行中。 Relative to the X-axis, where the track pitch (PT) is PT

In some embodiments of the CPP, the tracks define MD-columns. As such, MD patterns 210(15) and 210(18) are located in the first MD row, MD patterns 210(16) and 210(19) are located in the second MD row, and MD patterns 210(17) and 210(19) in the third (and last) MD row.

In Figure 2E, M0 patterns 218(17)-218(20) are within cell 204(3)(E). One end of each of M0 patterns 218(17) and 218(20) is positioned proximate the side boundary 230 of cell 204(3)(E) with respect to the X-axis.

(1/6)CPP。 In some embodiments, relative to the X-axis, to help provide a first cell region corresponding to cell 204(3)(E) and an adjacent (eg, contiguous) first cell region disposed to the right of side boundary 230 of the first cell region Isolation between two cell regions (not shown) provides a gap 232 between the right end of each of M0 patterns 218(17) and 218(20) and the side boundary 230 of cell 204(3)(E). In some embodiments, the length of the slit 232 is L232, where L232

(1/6) CPP.

CPP。 In the layout diagram 200E, with respect to the X-axis, the M0 patterns 218(18), 218(19), and 218(20) each have a width substantially equal to the minimum width Lmin of the level M0. The minimum width Lmin represents the minimum length of a conductive segment in layer M0 in a semiconductor element relative to typical manufacturing tolerances of the semiconductor technology process generation from which the semiconductor element is produced. The minimum width Lmin is less than CPP, Lmin<CPP. In some embodiments, Lmin is based on the spacing between cut M0 (CM0) patterns (not shown). In some embodiments, Lmin

CPP.

1.5CPP。 In some embodiments, design rule 3 is as follows: if a given MD pattern is in the first or last MD row of the cell, and if the given MD pattern is covered by the corresponding VGD pattern, and if the corresponding M0 of the corresponding VGD pattern is covered If the pattern is not a PG pattern, the width (relative to the X axis) of the corresponding M0 pattern is set to be at least L2, where CPP<L2. In some embodiments, L2

1.5CPP.

In Figure 2E, MD patterns 210(15) and 210(18) are in the first MD row, and MD patterns 210(17) and 210(20) are in the last MD row. Each of MD patterns 210(15), 210(17), 210(18), and 210(20) are VD patterns (ie, corresponding to VD patterns 216(17), 216(18), 216(23) ) and 216(22)) coverage.

In layout 200E, MD pattern 210(20) is covered by M0 pattern 218(20), which is not a PG pattern. Therefore, Design Rule 3 applies to the MD pattern 210 (20).

The result of applying Design Rule 3 to Figure 2E is shown in Figure 2F. Cell 204(3)(F) of floorplan 200F is the result of applying the method including design rule 3 to floorplan 200E, and more specifically to M0 pattern 218(20). The result of applying Design Rule 3 to Figure 2E includes changing the M0 pattern 218(20) of Figure 2E to the M0 pattern 218(20)' of Figure 2F. An increase ΔW, ΔW in the width of the M0 pattern 218 ( 20 )' is shown as reference numeral 234 in FIG. 2F . In some embodiments, with respect to the X-axis, L2 represents the minimum separation distance between CM0 patterns (not shown) corresponding to the semiconductor technology process generation. By increasing the width of M0 pattern 218(20)' enough to be designated as a pinhole pattern, floorplan 200F has improved M0 routing resources compared to floorplan 200E. In some embodiments, layout 200F is considered to be a given M0 pattern designated as a pinhole pattern, and because layout 200F compared to layout 200E has one additional M0 pattern that can be designated as a pinhole pattern There are improved M0 routing resources relative to floorplan 200E.

3A-3H are corresponding layout diagrams 300A- 300H according to some embodiments.

Layouts 300A, 300C, 300E, and 300G represent initial layouts, and layouts 300B, 300D, 300F, and 300H represent corresponding layouts (post-method) generated by one or more of the methods disclosed herein in accordance with some embodiments. -method) layout diagram). For example, floor plan 300A represents an initial floor plan, and floor plan 300B represents a corresponding post-method floor plan resulting from one or more of the methods disclosed herein, according to some embodiments. More specifically, cell 304(1)(B) of floorplan 300B represents that a method including a fourth design rule (Design Rule 4) (discussed below) has been applied to floorplan 300A of Figure 3A in accordance with some embodiments. An example of a cell region corresponding to cells 304(1)(B), 304(2)(D), 304(3)(F), and 304(4)(H) is cell region 104 of FIG. 1 .

The layout diagrams 300A to 300H are similar to the layout diagrams 200A to 200F of the corresponding Figures 2A to 2F. Figures 3A-3H follow a similar numbering convention to that of Figures 2A-2F. Although correspondingly, But some parts are still different. Figures 2A-2F use 2-sequence numbering, while Figures 3A-3H use 3-sequence numbering. To help identify corresponding but still different parts, the numbering convention uses bracket numbers. For example, pattern 318(1)(A) in Figure 3A and pattern 218(11) in Figure 2C are both M0 patterns, with similarities reflected in common root_18(_), and where The differences are reflected in sequence numbers 3_(_)(_) and 2_(_) and in brackets _(1)(_) and _(11). To help reflect the difference between the corresponding initial layout and post-method layout, some elements include second brackets. For example, pattern 318(1)(A) in Figure 3A and pattern 318(1)(B) in Figure 3B are both M0 patterns, with the difference reflected in the second bracket _(_)(A) and _(_)(B). For the sake of brevity, the discussion will focus more on the differences between Figures 3A-3H and Figures 2A-2F than on similarities.

In Figure 3A, floorplan 300A includes portions of cell 304(1)(A). Layout diagram 300A further includes: gate patterns 312(1), 312(2), 314(1), and 314(2); VGD pattern 316(1): M0 pattern 318(1)(A); and VIA0 pattern 320 (1). For simplicity of description, (except for other patterns), the fin pattern, the MD pattern, and the M1 pattern are omitted from FIGS. 2C to 2D. In some embodiments, cell 304(1)(A) includes: gate patterns 312(1)-312(2) and 314(1)-314(2): VGD pattern 316(1); and M0 pattern 318 (1)(A).

In layout diagram 300A, VGD pattern 316(1) is covered by M0 pattern 318(1)(A), and M0 pattern 318(1)(A) is covered by VIA0 pattern 320(1). The first portion of the M0 pattern 318(1)(A) extends to the right of the VIA0 pattern 320(1) by a width 336(2) relative to the horizontal.

0.2CPP)

WOH

(

0.3CPP)。在一些實施例中，相對於產生半導體元件之半導體技術製程世代的典型製造容限，若半導體中之M0區段的最小高度Hmin(相對於Y軸)為(

20nm)<Hmin，則WOH

0.2CPP。在一些實施例中，若對應半導體技術製程世代之最小高度Hmin為(

9nm)

Hmin

(

20nm)，則WOH

0.3CPP。在一些實施例中，在M0圖案突出於對應VIA0圖案且M0圖案之突出部分的寬度為大致OH 336(_)的情況下，則將突出部分稱作短節部分。 The first portion of M0 pattern 318(1)(A) protrudes to the right of VIA0 pattern 320(1) by width 336(2), and thus width 336(2) is referred to as overhang (OH) 336(2). In some embodiments, OH 336(_) (eg, OH 336(1), OH 336(2), or the like) represents the smallest protrusion in a semiconductor element that can be produced within typical manufacturing tolerances by the corresponding semiconductor technology process generation Width WHO (relative to the X-axis), eg, the corresponding first conductive segment in layer M0 protrudes beyond the first VIA0 structure, where the first VIA0 structure is represented by VIA0 pattern 320(1), and the first conductive segment in layer M0 is The segment is represented by the M0 pattern 318(1)(A). In some embodiments, (

0.2CPP)

WOH

(

0.3CPP). In some embodiments, relative to the typical manufacturing tolerances of the semiconductor technology process generation in which the semiconductor device is produced, if the minimum height Hmin (relative to the Y-axis) of the M0 segment in the semiconductor is (

20nm)<Hmin, then WOH

0.2CPP. In some embodiments, if the minimum height Hmin corresponding to the semiconductor technology process generation is (

9nm)

Hmin

(

20nm), then WOH

0.3CPP. In some embodiments, where the M0 pattern protrudes beyond the corresponding VIA0 pattern and the width of the protruding portion of the M0 pattern is approximately OH 336(_), the protruding portion is referred to as a subsection.

The second portion of the M0 pattern 318(1)(A) extends to the left of the VGD pattern 316(1) by a width 336(1) relative to the horizontal, and the third portion 338 of the M0 pattern 318(1)(A) (1) extends to the left of the second portion of the M0 pattern 318(1)(A).

In some embodiments, Design Rule 4 is as follows: With respect to the X-axis, if a given M0 pattern covers a given VGD pattern or is given a VIA0 pattern Overlay, then the first and second wing portions of a given M0 pattern (in the present range) are reduced to the corresponding first and second puppet portions, where (A) the first wing portion extends to the leftmost via The left side of the hole pattern (which is a VG pattern or a VIA0 pattern) by an amount greater than OH 336(_), (B) the second wing portion extends to the right of the rightmost via pattern (which is a VG pattern or a VIA0 pattern) by up to an amount greater than OH 336(_), (C) the first subsection portion extends to the left of the leftmost via pattern (which is a VG pattern or a VIA0 pattern) and has a width substantially equal to OH 336(_), and (D) The second subsection extends to the right of the rightmost via pattern (which is the VG pattern or the VIAO pattern) and has a width substantially equal to OH 336(_). In some embodiments, reducing the wing portion of a given M0 pattern to a puppet portion is referred to as a trim wing portion.

In Figure 3A, the leftmost via pattern is VGD pattern 316(1) relative to the protrusion of M0 pattern 318(1)(A). The first wing portion of the M0 pattern 318(1)(A) corresponds to the combination of the third portion 338(1) of the M0 pattern 318(1)(A) and the second portion of the M0 pattern 318(1)(A), This second portion extends to the left of VGD pattern 316(1) by width 336(1).

The first wing portion extends to the left of VGD pattern 316(1) by an amount greater than OH 336(2). Therefore, Design Rule 4 applies to the first wing portion of M0 pattern 318(1)(A). In particular, the first wing portion of M0 pattern 318(1)(A) extends beyond OH 336(2) by an amount equal to the width of the third portion 338(1) of M0 pattern 318(1)(A).

In layout diagram 300A, with respect to the protrusion of M0 pattern 318(1)(A), the rightmost via pattern is VIA0 pattern 320(1). The second wing portion of M0 pattern 318(1)(A) corresponds to the second wing portion of M0 pattern 318(1)(A) part. The second wing portion of M0 pattern 318(1)(A) extends to the right of VIA0 pattern 320(1), but not by an amount greater than OH 336(2). Therefore, Design Rule 4 does not apply to the second wing portion of M0 pattern 318(1)(A).

The result of applying Design Rule 4 to Figure 3A is shown in Figure 3B. Cell 304(1)(B) of floorplan 300B is the result of applying the method including Design Rule 4 to floorplan 300A, and more specifically to the first wing portion of M0 pattern 318(1)(A) . The results of applying Design Rule 4 to Figure 3A include that the narrower (relative to the X-axis) M0 pattern 318(1)(B) has replaced the wider M0 pattern 318(1)(A). M0 pattern 318(1)(B) is narrower than M0 pattern 318(1)(A) because third portion 338(1) of M0 pattern 318(1)(A) has been removed from FIG. 3A, as shown by The corresponding dashed shape 338(1)' in Figure 3B is indicated.

With the third portion 338(1) of the M0 pattern 338(1)(A) removed, the floorplan 300B is less congested than the floorplan 300A. With the third portion 338(1) of the M0 pattern 338(1)(A) removed, the floorplan 300B has improved M0 routing resources compared to the floorplan 300A. In some embodiments, floorplan 300B is considered relative to floorplan 300A because M0 pattern 318(1)(B) of floorplan 300B is narrower than M0 pattern 318(1)(A) of floorplan 300A Features improved M0 routing resources.

With regard to Figures 3C and 3D, it should be remembered that cell 304(2)(D) of floorplan 300D represents that a method including design rule 4 has been applied to floorplan 300C of Figure 3C according to some embodiments.

In layout diagram 300C, with respect to the protrusion of M0 pattern 318(2)(C), the leftmost via pattern is VIA0 pattern 316(1), such that M0 pattern 316(1) The first wing portion of pattern 318(2)(C) is the same as the first wing portion of M0 pattern 318(1)(A). Therefore, Design Rule 4 applies to the first wing portion of M0 pattern 318(2)(C).

In layout diagram 300C, with respect to the protrusion of M0 pattern 318(2)(C), the rightmost via pattern is VGD pattern 316(1). With respect to M0 pattern 318(2)(C), the fourth portion of M0 pattern 318(2)(C) extends to the right of VGD pattern 316(1) by width 336(3), and M0 pattern 318(2)(C) ) of the fifth portion 338(2) extends to the right of the fourth portion of the M0 pattern 318(2)(C). The second wing portion of M0 pattern 318(2)(C) corresponds to the combination of fifth portion 338(2) of M0 pattern 318(2)(C) and the fourth portion of M0 pattern 318(2)(C). The second wing portion extends to the right of VGD pattern 316(1) by an amount greater than OH 336(3). Therefore, Design Rule 4 applies to the second wing portion of M0 pattern 318(2)(C). In particular, the second wing portion of M0 pattern 318(2)(C) extends beyond OH 336(3) by an amount equal to the width of fifth portion 338(2) of M0 pattern 318(2)(C).

The result of applying Design Rule 4 to Figure 3C is shown in Figure 3D. Cell 304(2)(D) of floorplan 300D is the result of applying the method including design rule 4 to floorplan 300C, and more specifically to the first and second elements of M0 pattern 318(2)(C). Two wings. The results of having applied Design Rule 4 to Figure 3C include that the narrower (relative to the X-axis) M0 pattern 318(2)(D) has replaced the wider M0 pattern 318(2)(C). M0 pattern 318(2)(D) is narrower than M0 pattern 318(1)(C) because third portion 338(1) and fifth portion of M0 pattern 318(2)(C) have been removed from Figure 3C Portion 338(2), as indicated by the corresponding dashed shapes 338(1)' and 338(2)' in Figure 3D indicated. In some embodiments, floorplan 300D is considered relative to floorplan 300C because M0 pattern 318(2)(D) of floorplan 300D is narrower than M0 pattern 318(2)(C) of floorplan 300C Features improved M0 routing resources.

The result of applying Design Rule 4 to Figure 3E is shown in Figure 3F. Cell 304(3)(F) of floorplan 300F is the result of applying the method including design rule 4 to floorplan 300E, and more specifically to the first wing portion of M0 pattern 318(3)(E) . The results of applying Design Rule 4 to Figure 3E include that the narrower (relative to the X-axis) M0 pattern 318(3)(F) has replaced the wider M0 pattern 318(3)(E). M0 pattern 318(3)(F) is narrower than M0 pattern 318(3)(E) because portion 338(3) of M0 pattern 318(3)(E) has been removed from Fig. 3E, as shown by Fig. 3F The corresponding dashed shape 338(3)' in the figure is indicated. In some embodiments, floorplan 300F is considered relative to floorplan 300E because M0 pattern 318(3)(F) of floorplan 300F is narrower than M0 pattern 318(3)(E) of floorplan 300E Features improved M0 routing resources.

The result of applying Design Rule 4 to Figure 3G is shown in Figure 3H. Cell 304(4)(H) of floorplan 300H is the result of applying the method including design rule 4 to floorplan 300G, and more specifically to the first and second of M0 pattern 318(4)(G) Two wings. The results of applying Design Rule 4 to Figure 3G include that the narrower (relative to the X-axis) M0 pattern 318(4)(H) has replaced the wider M0 pattern 318(4)(G). M0 pattern 318(4)(H) is narrower than M0 pattern 318(4)(G) because portions 338(3) and 338(4) of M0 pattern 318(4)(G) have been removed from Figure 3G ), as indicated by the Corresponding dashed shapes 338(3)' and 338(4)' in Figure 3H are indicated. In some embodiments, floorplan 300H is considered relative to floorplan 300G because M0 pattern 318(4)(H) of floorplan 300H is narrower than M0 pattern 318(4)(G) of floorplan 300G Features improved M0 routing resources.

FIGS. 4A-4C are corresponding cross-sectional views 400A-400C of corresponding portions of corresponding semiconductor elements according to some embodiments.

More specifically, the cross-sectional views 400A-400B illustrate corresponding portions of the semiconductor device based on the layout diagram 200A of FIG. 2A. Cross-sectional views 400C to 400D show corresponding portions of the semiconductor device based on the layout diagram 200 of FIG. 2B. Portions corresponding to cross-sectional views 400C to 400D and semiconductor elements including such portions are corresponding examples of cell region 104 and semiconductor element 100 of FIG. 1 .

FIGS. 4A to 4C assume an orthogonal XYZ coordinate system, wherein the X-axis, the Y-axis and the Z-axis represent the corresponding first, second and third directions. In some embodiments, the first, second and third directions correspond to a different orthogonal coordinate system than the XYZ coordinate system.

Cross-sectional views 400A-400D follow a similar numbering convention to that of Figures 2A-2F. Figures 2A-2F use 2-sequence numbering, while Figures 4A-4D use 4-sequence numbering. For example, the fin 408P of FIG. 4A corresponds to the fin pattern 208P of FIG. 2A.

In FIG. 4A, the portion corresponding to cross-sectional view 400A includes transistor layer 452; M0 metallization layer over transistor layer 452; V0 layer 456 over M0 layer 454: and between V0 layer 456 458 on the M1 floor.

Transistor layer 452 includes: fin 408P; interlayer dielectric (ILD) 460 in a sublayer corresponding to fin 408P; MD structure 410(2) on fin 408P; gate on fin 408P structure 412(2); ILD 462 in the sublayer corresponding to MD structure 410(2) and gate structure 412(2); VGD structure 416(3) on MD structure 410(2); ILD 464 in a sublayer of VGD structure 416(3). M0 layer 454 includes conductive M0 segment 418( 2 ) overlying VGD structure 416( 3 ) and ILD 466 . VO layer 456 includes VIA0 structure 420( 2 ) (which is on M0 section 418( 2 )) and ILD 468 . M1 layer 458 includes M1 sections 422( 2 ) and 422( 3 ) (the latter overlying V0 420( 2 )) and ILD 450 .

The long axis of the fin 408P extends in a direction generally parallel to the X axis. The long axes of MD structure 410(2) and gate structure 412(2) extend in the Y direction (not shown in FIG. 4A). With respect to the Z-axis, MD structure 410(2) and gate structure 412(2) are disposed on fin 408P.

A VGD structure (eg, VGD structure 416(3)) is a contact structure that electrically couples an overlying conductive segment (eg, M0 segment 418(2)) and an underlying MD structure (eg, MD structure) in layer M0 410(2)) or the underlying gate structure. In some embodiments, VGD is an acronym for the phrase Via Gate or Via Drain/Source.

In FIG. 4B, with respect to the portion corresponding to the cross-sectional view 400B, the transistor layer 452 includes: an interlayer dielectric (ILD) 460 in a sublayer corresponding to the fin 408P (not shown in FIG. 4B); a gate Pole structures 412(1) and 412(2); ILD 462; VGD structure 416(3) on gate structure 412(1); and ILD 464. M0 layer 454 includes conductive M0 segment 418(4) (which overlies VGD structure 416(3)) and 418(5) and ILD 466. VO layer 456 includes VIA0 structure 420( 1 ) (which is on M0 section 418( 4 )) and ILD 468 . M1 layer 458 includes conductive M1 segment 422( 1 ) (which is on VIA0 structure 420( 1 )), 422( 2 ) and 422( 3 ), and ILD 450 .

In Figure 4C, compared to Figure 4A, some structures have been removed. In particular, the M1 pattern 422(2) of Figure 4A has been removed in Figure 4C, as indicated by the corresponding dashed shape 422(2)'.

In Figure 4D, compared to Figure 4B, some structures have been removed. In particular, VIA0 pattern 420(1) of FIG. 4B has been removed in FIG. 4D, as indicated by the corresponding dashed shape 420(1)'. Also, the M1 patterns 422(1) and 422(2) of Fig. 4B have been removed in Fig. 4D, as indicated by the corresponding dashed shapes 422(1)' and 422(2)'.

FIG. 5 is a flowchart of a method 500 of fabricating a semiconductor device in accordance with some embodiments.

Examples of semiconductor devices that may be fabricated according to method 500 include semiconductor device 100 of FIG. 1 .

In FIG. 5, method 500 includes blocks 502-504. At block 504, a floorplan is generated that includes, among other things, improved placement of M0 routing resources. Examples of semiconductor devices that include cell regions with improved M0 routing resources that correspond to the layout produced by method 500 include semiconductor device 100 of FIG. 1 . Block 502 is discussed in more detail below with reference to FIG. 6A. From block 502, flow proceeds to block 504.

At block 504, based on the layout, at least one of: (A) performing one or more photolithography exposures; or (B) fabricating a or a plurality of semiconductor masks; or (C) one or more components in a layer in which a semiconductor element is fabricated. See the description of Figure 8 below.

FIG. 6A is a flowchart of a method of generating a layout map according to some embodiments.

More particularly, the method of FIG. 6A illustrates block 502 of FIG. 5 in greater detail, in accordance with one or more embodiments.

Examples of layouts that can be generated according to the method of FIG. 6A include layouts of the embodiments disclosed herein, or the like. In some embodiments, the layouts and their corresponding versions are stored on a non-transitory computer-readable medium, eg, layout(s) 708 stored as computer-readable medium 704 of Figure 7 (discussed below). According to some embodiments, the method of FIG. 6A may be implemented, for example, using EDA system 700 (FIG. 7, discussed below). Examples of semiconductor elements that can be fabricated based on the layout produced according to the method of FIG. 6A include the semiconductor element 100 of FIG. 1, and semiconductors based on layouts 200B, 200D, 200F, 300B, 300D, 300F, 300G, or the like element.

In Figure 6A, block 502 includes blocks 602-606. At block 602, a candidate pattern is selected, the candidate pattern being the first conductive pattern in the M_2nd level or the M_1st level of the layout. In some embodiments, the M_2nd level is the M1 level, and the M_1st level is the M0 level. Examples of patterns in the M_2nd level include M1 patterns 222(1), 222(2), and 222(4) in the M1 level of Figure 2A, or the like. Examples of patterns in the M_1st level include M0 patterns 218(12) and 218(14) in the M0 level of Fig. 2C, M0 pattern 218(20) in the M0 level of Fig. 2F, 3A The M0 pattern 318(1)(A) in the M0 level of Fig. 3C, the M0 pattern 318(2)(C) in the M0 level of Fig. 3C, the M0 pattern 318(3)(E) of the M0 level of Fig. 3E ), the M0 pattern 318(4)(G) in the M0 level of Figure 3G, or the like. From block 602, flow proceeds to block 604.

At block 604, it is determined that the candidate pattern satisfies one or more criteria. Examples of criteria are those corresponding to Design Rules 1, 2, 3, or 4, or the like. From block 604, flow proceeds to block 606.

At block 606, the size of the candidate pattern is changed. In some embodiments, the size of the candidate pattern is changed by reduction, eg, as shown in Figure 3B, Figure 3D, Figure 3F, or Figure 3H, or the like. In some embodiments, the size of the candidate pattern is changed by removing the candidate pattern from the layout, eg, as shown in Figure 2B, Figure 2D, or the like. In some embodiments, the size of the candidate pattern is changed by increasing, eg, as shown in Figure 2F or the like.

6B is a flowchart of a method of generating a layout map according to some embodiments.

More particularly, the method of FIG. 6B illustrates blocks 604 and 606 of FIG. 6A in greater detail, respectively, in accordance with one or more embodiments. The context of Figure 6B is Design Rule 1.

An example of a floor plan that can be generated according to the method of FIG. 6B is floor plan 200B, or the like. Examples of semiconductor elements that can be fabricated based on the layout produced according to the method of FIG. 6B include the semiconductor element 100 of FIG. 1, the semiconductor element based on the layout 200B, or the like.

In Figure 6B, block 604 includes blocks 620-622. In blocks 620-622, the candidate pattern is the first M_2nd pattern. At block 620, it is determined that the first M_2nd pattern is designated as the pinhole pattern. Examples of M_2nd patterns designated as pinhole patterns include M1 patterns 222(1), 222(2), and 222(4).

In some embodiments, the relationship of a given M1 pattern relative to the overlying pattern is analyzed in order to decide whether to designate a given M1 as a pinhole pattern. In some embodiments, the state designated as a pinhole pattern is a property associated with a given M1 pattern, such that examining the properties of a given M1 pattern reveals whether the given M1 pattern is a pinhole pattern. From block 620, flow proceeds to block 622.

At block 622, the first via pattern in the first interconnect level (the first VIA_1st pattern) is determined to be the only VIA_1st pattern covered by the first M_2nd pattern. Continuing with the example of the M1 pattern 222(1) of the pinhole pattern, the VIA0 pattern 222(1) is the only VIA0 pattern covered by the M1 pattern 222(2). From block 622, flow leaves block 604 and proceeds to block 606.

In Figure 6B, block 606 includes block 610. At block 610, at least the size of the candidate pattern is reduced. Block 610 includes block 612 . At block 612, candidate patterns are removed from the layout map. An example of removing a candidate pattern is removing the M1 pattern 222(1) from Figure 2B, as indicated by the corresponding dashed shape 222(1)' in Figure 2B. In some embodiments, the corresponding via pattern, eg, VIA0 pattern 220(1), is also removed, as indicated by the corresponding dashed shape 222(1)' in Figure 2B.

In some embodiments, after the candidate patterns have been removed, the method further includes alternatively designating a corresponding underlying first pattern in the first level (the first M_1st pattern) as the pinhole pattern. An example of an alternative designation of the M_1st pattern as the pinhole pattern is to designate the M0 pattern 218(4) of Figure 2B as the pinhole pattern after the corresponding M1 pattern 222(1) has been removed.

FIG. 6C is a flowchart of a method of generating a layout map according to some embodiments.

More particularly, the method of FIG. 6C illustrates blocks 604 and 606 of FIG. 6A in greater detail, respectively, in accordance with one or more embodiments. The context of Figure 6C is Design Rule 2.

An example of a layout that can be generated according to the method of FIG. 6C is layout 200D, or the like. Examples of semiconductor elements that can be fabricated based on the layout generated according to the method of FIG. 6C include the semiconductor element 100 of FIG. 1, the semiconductor element based on the layout 200D, or the like.

In Figure 6C, block 604 includes blocks 630-632. In blocks 630-632, the candidate pattern is the first M_1st pattern. At block 630, it is determined that the first M_1st pattern does not cover at least the first via pattern in the VIA_1st level (the first VIA_1st pattern). Examples of M_1st patterns that do not cover at least the first VIA_1st pattern include M0 patterns 218(12) and 218(14) of Figure 2C, or the like. From block 630, flow proceeds to block 632.

At block 632, it is determined that the first M_1st pattern is not covered by at least the first VIA_2nd pattern. Examples of M_1st patterns not covered by at least the first VIA_1st pattern include M0 patterns 218(12) and 218(14) of Figure 2C, or the like.

In Figure 6C, block 606 includes block 640. At block 640, at least the size of the candidate pattern is reduced. Block 640 includes block 642 . At block 642, candidate patterns are removed from the layout map. An example of removing a candidate pattern is the removal of the M0 pattern 218(12) from Figure 2C, as indicated by the corresponding dashed shape 218(12)' in Figure 2D.

Figure 6D is a flowchart of a method of generating a layout according to some embodiments.

More particularly, the method of FIG. 6D illustrates blocks 604 and 606 of FIG. 6A in greater detail, respectively, in accordance with one or more embodiments. The context of Figure 6D is Design Rule 4.

Examples of floor plans that can be generated according to the method of FIG. 6D are floor plans 300B, 300D, 300F, 300H, or the like. Examples of semiconductor elements that can be fabricated based on the layout produced according to the method of FIG. 6D include semiconductor element 100 of FIG. 1 , semiconductor elements based on layouts 300B, 300D, 300F, 300H, or the like.

In Figure 6D, block 604 includes blocks 650-652. In blocks 650-652, the candidate pattern is the first M_1st pattern. As shown in Figure 6D, flow proceeds to either block 650 or block 652. At block 650, it is determined that the first M_1st pattern covers at least the first via pattern in the VIA_1st level (the first VIA_1st pattern). Examples of M_1st patterns covering at least the first VIA_1st pattern include M0 patterns 318(1)(A), 318(2)(C), 318(3 corresponding to Figures 3A, 3C, 3E, and 3G )(E) and 318(4)(G), or the like.

At block 652, it is determined that the first M_1st pattern is covered by at least the first via pattern in the VIA_2nd level (the first VIA_2nd pattern). Examples of M_1st patterns covered by at least the first VIA_2nd pattern include M0 patterns 318(1)(A) and 318(3)(E) corresponding to Figures 3A and 3E, or the like.

In Figure 6D, block 606 includes block 660. At block 660, at least the size of the candidate pattern is reduced. Block 660 includes block 662 . At block 662, the size of the wing portion of the candidate pattern is trimmed to result in a smaller nub portion. Examples of wing portions and corresponding wing portions are as follows. An example of a wing portion is the first wing portion of the M0 pattern 318(1)(A), which corresponds to the third portion 338(1) of the M0 pattern 318(1)(A) and the M0 pattern 318(1)(A) A combination of the second portion extending to the left of the VGD pattern 316(1) by the width 336(1) in Figure 3A. An example of a corresponding pup portion is the second portion of M0 pattern 318(1)(B), which extends to the left of VGD pattern 316(1) by width 336(1) in Figure 3B.

Figure 6E is a flow diagram of a method of generating a layout map according to some embodiments.

More particularly, the method of FIG. 6E illustrates blocks 604 and 606 of FIG. 6A in greater detail, respectively, in accordance with one or more embodiments. The context of Figure 6E is Design Rule 3.

An example of a floor plan that can be generated according to the method of FIG. 6E is floor plan 200F, or the like. Examples of semiconductor elements that can be fabricated based on the layout produced according to the method of FIG. 6E include the semiconductor element 100 of FIG. 1, the semiconductor element based on the layout 200F, or the like.

In Figure 6E, block 604 includes blocks 670-678. In blocks 670-678, the candidate pattern is the first M_1st pattern. In block 670, it is determined that the first MD pattern is in the first or last MD row. Examples of MD patterns in the first MD row include MD patterns 210(15) and 210(18) of Figure 2E, or the like. Examples of MD patterns in the last MD row include MD patterns 210(17) and 210(20) of Figure 2E, or the like. From block 670, flow proceeds to block 672.

At block 672, it is determined that the first MD pattern is covered by the first via pattern in the VIA_1st level (the first VIA_1st pattern) (referred to herein as the first VGD pattern). Examples of MD patterns covered by the first VIA_1st pattern include MD patterns 210(15), 210(17), 210(18), 210(20) of Figure 2E, or the like. From block 672, flow proceeds to block 674.

At block 674, it is determined that the first VIA_1st pattern is also covered by the first M_1st pattern. Examples of VIA_1st patterns that are also covered by the first M_1st pattern include VIA0 patterns 216(17), 216(18), 216(23), and 216(22) of Figure 2E, or the like. From block 674, flow proceeds to block 676.

At block 676, it is determined that the first M_1st pattern is also not a PG pattern. An example of a first M_1st pattern that is also not a PG pattern is the M0 pattern 218(20) of Figure 2E, or the like. From block 676, flow proceeds to block 678.

At block 678, it is determined that the length of the M_1st pattern is less than the first reference distance. An example of the first reference distance is L2 (see Figures 2E-2F).

In Figure 6E, block 606 includes block 680. At block 680, the size of the candidate pattern is increased. Block 680 includes block 682 . At block 682, the size of the candidate pattern is increased to be at least substantially equal to the first reference distance. An example of increasing the size of the candidate pattern is that the size of the M0 pattern 218(20)' of Figure 2F has been increased by the amount ΔW, as indicated by reference numeral 234 in Figure 2F.

FIG. 7 is a block diagram of an electronic design automation (EDA) system 700 in accordance with some embodiments.

In some embodiments, EDA system 700 includes an automated place and route (APR) system. According to some embodiments, for example, the EDA system 700 may be used to implement the methods described herein for generating a PG floorplan in accordance with one or more embodiments.

In some embodiments, the EDA system is a general-purpose computing device that includes a hardware processor 702 and a non-transitory computer-readable storage medium (also referred to as memory, storage medium, or the like) 704 . Storage medium 704 is encoded with (ie, stores) computer code, ie, a set of executable instructions 706, among other things. Execution of instructions 706 by hardware processor 702 represents (at least in part) an EDA tool that implements some or all of a method according to an embodiment, eg, a method described herein (hereinafter, in accordance with one or more embodiments) , the process and/or method).

Processor 702 is electrically coupled to computer-readable storage medium 704 via bus 708 . Processor 702 is also electrically coupled to I/O interface 710 via bus 708 . The network interface 712 is also electrically connected to the processor 702 via the bus bar 708 . The network interface 712 is connected to the network 714 so that the processor 702 and the computer The readable storage medium 704 can be connected to external components via a network 714 . Processor 702 is used to execute computer code 706 encoded in computer-readable storage medium 704 so that system 700 can be used to perform some or all of the processes and/or methods. In one or more embodiments, processor 702 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or device or apparatus). For example, computer readable storage medium 704 includes semiconductor or solid state memory, magnetic tape, removable computer disk, random access memory (RAM), read only memory (ROM), rigid disk and/or CD. In one or more embodiments using optical disks, the computer-readable storage medium 704 includes compact disk-read only memory (CD-ROM), compact disk-read/write (CD-R/W), and/or digital Video Disc (DVD).

In one or more embodiments, computer-readable storage medium 704 stores computer code (instructions) 706 for enabling system 700 (wherein the execution represents (at least in part) an EDA tool) to perform the process and/or some or all of the methods. In one or more embodiments, the computer-readable storage medium 704 also stores information that facilitates performing some or all of the processes and/or methods. In one or more embodiments, computer-readable storage medium 704 stores a library 707 of standard cells (ie, standard cell library), which library 707 includes such standard cells as disclosed herein and a A plurality of floorplans 708 .

EDA system 700 includes I/O interface 710 . The I/O interface 710 is coupled to external circuitry. In one or more embodiments, I/O interface 710 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to the processor 702.

The EDA system 700 also includes a network interface 712 coupled to the processor 702 . Network interface 712 allows system 700 to communicate with network 714 that connects one or more other computer systems. The network interface 712 includes a wireless network interface such as Bluetooth, WIFI, WIMAX, GPRS or WCDMA; or a wired network interface such as ETHERNET, USB or IEEE-1364. In one or more embodiments, some or all of the processes and/or methods are implemented in two or more systems 700 .

System 700 is configured to receive information via I/O interface 710 . Information received via I/O interface 710 includes one or more of instructions, data, design rules, a library of standard cells, and/or other parameters for processing by processor 702 . The information is communicated to processor 702 via bus 708 . The EDA system 700 is configured to receive UI-related information via the I/O interface 710 . The information is stored in the computer-readable medium 704 as a user interface (UI) 742 .

In some embodiments, some or all of the processes and/or methods are implemented as a stand-alone software application for execution by a processor. In some embodiments, some or all of the processes and/or methods are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the process and/or method is implemented as a plug-in to a software application. In some embodiments, at least one of the processes and/or methods is implemented as a software application that is part of an EDA tool Mode. In some embodiments, some or all of the processes and/or methods are implemented as software applications running on the EDA system 700 . In some embodiments, a layout drawing including standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool.

In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external/removable and/or internal/embedded storage or memory units, eg, optical disks (such as DVDs), magnetic disks ( such as hard disk), semiconductor memory (such as ROM, RAM, memory card), and one or more of the like.

FIG. 8 is a block diagram of an integrated circuit (IC) fabrication system 800 and an IC fabrication flow associated therewith, according to some embodiments. In some embodiments, fabrication system 800 is used to fabricate (A) one or more semiconductor masks or (B) at least one component of a layer of a semiconductor integrated circuit based on the layout.

In FIG. 8, IC manufacturing system 800 includes entities that interact with each other in the design, development, and manufacturing cycles and/or services related to manufacturing IC components 860, such as design room 820, mask room 830, and IC manufacturer/ Manufacturer ("Fab") 850. The entities in the system 800 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. Communication networks include wired and/or wireless communication channels. Each entity interacts with and provides services to and/or receives services from one or more of the other entities. in some implementations In an example, two or more of design room 820, mask room 830, and IC fab 850 are owned by a single larger company. In some embodiments, two or more of design room 820, mask room 830, and IC fab 850 coexist in a common facility and use common resources.

A design house (or design team) 820 generates an IC design layout 822 . IC design layout 822 includes various geometric patterns designed for IC element 860 . The geometric patterns correspond to the patterns of metal, oxide, or semiconductor layers that make up the various components of the IC device 860 to be fabricated. Various layers are combined to form various IC features. For example, a portion of the IC design layout 822 includes various IC features to be formed in a semiconductor substrate, such as a silicon wafer, such as active regions, gate electrodes, source and drain electrodes, metal lines for interlayer interconnects or vias, and openings for bonding pads; and various layers of materials disposed on semiconductor substrates. Design house 820 implements appropriate design procedures to form IC design layout 822 . Design procedures include one or more of logical design, physical design, or placement and routing. The IC design layout 822 is presented in one or more data files with geometric pattern information. For example, the IC design layout 822 can be expressed in a GDSII file format or a DFII file format.

Mask chamber 830 includes data preparation 832 and mask fabrication 844 . Mask chamber 830 uses IC design layout 822 to fabricate one or more masks 845 that are used to fabricate various layers of IC element 860 according to IC design layout 822 . Mask room 830 performs mask data preparation 832, in which IC design layout 822 is converted into a representative data file ("RDF"). Mask data preparation 832 provides RDF to mask fabrication 844 . Mask fabrication 844 includes a mask direct writer. Mask direct writer converts RDF to Instead, an image on a substrate, such as a mask (master mask) 845 or a semiconductor wafer 853 . The design layout 822 is manipulated by the mask data preparation 832 to meet the specific characteristics of the mask direct writer and/or IC fab 850 requirements. In FIG. 8, mask data preparation 832 and mask fabrication 844 are illustrated as separate elements. In some embodiments, mask data preparation 832 and mask fabrication 844 may be collectively referred to as mask data preparation.

In some embodiments, mask data preparation 832 includes Optical Proximity Correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as images that may be caused by diffraction, interference, other process effects, and the like error. The OPC adjusts the IC design layout 822. In some embodiments, mask data preparation 832 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase transfer masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, mask data preparation 832 includes a mask rule checker (MRC) that examines an IC design layout 822 that has undergone processing in an OPC having a set of mask generation rules, such masks The generation rules contain certain geometric and/or wiring constraints to ensure sufficient margin to account for the variability of the semiconductor manufacturing process, and the like. In some embodiments, MRC modifies the IC design layout 822 to compensate for constraints during mask fabrication 844, which may offset part of the modifications performed by OPC to comply with mask generation rules.

In some embodiments, mask data preparation 832 includes lithography process check (LPC), the simulation of which will be performed by IC fab 850 to fabricate IC cells processing of item 860. LPC simulates this process based on the IC design layout 822 to produce simulated fabricated components, such as IC components 860 . Process parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, and the like or combinations thereof. In some embodiments, after LPC has produced analog fabricated components, if the shapes of the analog components are not close enough to meet the design rules, then the OPC and/or MRC are repeated to further refine the IC design layout 822.

It should be appreciated that the above description of mask data preparation 832 has been simplified for clarity. In some embodiments, data preparation 832 includes additional features such as logic operations (LOPs) to modify IC design layout 822 according to manufacturing rules. Additionally, the processes applied to IC design layout 822 during data preparation 832 may be performed in a variety of different orders.

After mask data preparation 832 and during mask fabrication 844, masks 845 and groups of masks 845 are fabricated based on the modified IC design layout 822. In some embodiments, mask fabrication 844 includes performing one or more lithographic exposures based on IC design layout 822 . In some embodiments, a mechanism using an electron beam (e-beam) or multiple electron beams is used to form a pattern on a mask (reticle or master) based on the modified IC design layout 822. Mask 845 may be formed by various techniques. In some embodiments, the mask 845 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. Used to expose layers of image-sensitive materials that have been coated on wafers (e.g. A radiation beam, such as a photoresist, such as an ultraviolet (UV) beam, is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of mask 845 includes a transparent substrate (eg, fused silica) and an opaque material (eg, chrome) coated in the opaque regions of the binary mask. In another example, the mask 845 is formed using a phase transfer technique. In a phase transfer mask (PSM) version of mask 845, the various features in the pattern formed on the phase transfer mask are configured to have suitable phase differences in order to enhance resolution and imaging quality. In various examples, the phase transfer mask may be attenuated PSM or alternating PSM. The mask(s) produced by mask fabrication 844 are used in various processes. For example, the mask(s) are used in an ion implantation process for forming various doped regions in semiconductor wafer 853, in an etch process for forming various etch regions in semiconductor wafer 853, and/or Or used in other suitable processes.

IC fab 850 includes wafer fabrication 852 . IC fab 850 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC fab 850 is a semiconductor foundry. For example, there may be a fabrication facility for front-end manufacturing of multiple IC products (front-end-of-process (FEOL) fabrication), while a second fabrication facility may provide back-end fabrication for interconnection and packaging of IC products (front-end fabrication (FEOL) (BEOL) manufacturing), and a third manufacturing facility may provide additional services to foundry companies.

IC fab 850 uses mask(s) 845 fabricated from mask chamber 830 to fabricate IC device 860 . Thus, IC fab 850 uses IC design floorplan 822 at least indirectly to manufacture IC components 860 . In some embodiments, semiconductor wafer 853 is fabricated by IC fab 850 using mask(s) 845 to form IC element 860 . In some embodiments, IC fabrication includes at least One or more lithographic exposures are performed indirectly based on the IC design floorplan 822 . The semiconductor wafer 853 includes a silicon substrate or other suitable substrate with material layers formed thereon. Semiconductor wafer 853 further includes one or more of various doped regions, dielectric features, multi-level interconnects, and the like (formed in subsequent fabrication steps).

Details regarding an integrated circuit (IC) manufacturing system (eg, system 800 of FIG. 8 ) and the IC manufacturing process associated therewith can be found in, eg, US Pat. No. 9,256,709, 2015, issued February 9, 2016 Found in US Patent Application Publication No. 20150278429, issued October 1, US Patent Application Publication No. 0140040838, issued February 6, 2014, and US Patent No. 7,260,442, issued August 21, 2007, these The entire contents of each of these cases are hereby incorporated by reference herein.

In an embodiment, a method (of fabricating a semiconductor device) includes (for a layout stored on a non-transitory computer-readable medium, the semiconductor device is based on a layout including a first and an overlying second metal) Metallization levels (corresponding to the M_1st and M_2nd levels) and the first interconnection level therebetween (VIA_1st level), corresponding to the first and overlying second metallization layers in the semiconductor element and the first interconnection layer in between), generate a layout Figure, including the following steps. Select a candidate pattern in the layout diagram, the candidate pattern is the first conductive pattern in the M_2nd level (the first M_2nd pattern) or the first conductive pattern in the M_1st level (the first M_1st pattern); determine that the candidate pattern satisfies one or more criteria; and at least reducing the size of the candidate patterns, thereby revising the layout. In an embodiment, the layout includes first and overlying second metallization levels (corresponding to the M_1st and M_2nd levels) and a first interconnect level therebetween (VIA_1st level), corresponding to the first and overlying second metallization layers in the semiconductor element and the first interconnect layer therebetween; and the candidate pattern is the first M_2nd pattern; determining that the candidate pattern satisfies one or more criteria includes: determining that the first M_2nd pattern is designated as the pinhole pattern; determining that the first via pattern in the first interconnect level (the first VIA_1st pattern) is the only VIA_1st pattern covered by the first M_2nd pattern; and reducing at least The size of the candidate pattern includes removing the first M_2nd pattern from the layout. In an embodiment, generating the layout map further includes instead specifying a corresponding underlying first pattern (the first M_1st pattern) in the first level as the pin hole pattern. In an embodiment, the first M_1st pattern is designated as the pinhole pattern because the first VIA_1st pattern in the VIA_1st interconnect level has at least first and second allowed overlying locations at which at least one of the M_2nd levels The corresponding first M_2nd pattern and the second M_2nd pattern can be positioned to cover the first VIA_1st pattern; or the first M_2nd pattern can be designated as the pinhole pattern because the corresponding first via in the second interconnect level (VIA_2nd level) The pattern (the first VIA_2nd pattern) has at least first and second allowable overlying positions at which at least the corresponding first and second conductive patterns (the first and the second conductive patterns in the third metallization level (M_3rd) Two M_3rd patterns) can be positioned to cover the first VIA_2nd pattern. In an embodiment, the layout diagram further includes a second interconnect level (VIA_2nd level) overlying the first M_1st level and corresponding to a second interconnect level, the second interconnect level overlying the first metallization layer in the semiconductor device; and the candidate pattern is the first M_1st pattern; determining that the candidate pattern satisfies one or more criteria includes: a first sub-method, the first sub-method includes determining that the first M_1st pattern does not cover at least the first via pattern in the VIA_1st level (the first VIA_1st pattern); and determining that the first M_1st pattern is not covered by at least the first via pattern in the VIA_2nd level (the first VIA_2nd pattern); or the second sub-method , the second sub-method includes, relative to the first direction, determining that the first M_1st pattern covers at least the first via pattern (the first VIA_1st pattern) in the VIA_1st level; or relative to the first direction, determining that the first M_1st pattern is to be At least the first via pattern (the first VIA_2nd pattern) in the VIA_2nd level covers; in the context of the first sub-method, reducing the size of at least the candidate pattern includes removing the first M_1st pattern from the layout; and in the second In the context of the sub-method, reducing at least the size of the candidate pattern includes trimming the first wing portion of the first M_1st pattern to result in a smaller first short section; and wherein, with respect to the first direction, there is a first VIA_1st pattern or a At least one of a VIA_2nd pattern such that the first wing portion is located between the first end of the first M_1st pattern and the first VIA_1st pattern or the first VIA_2nd pattern without correspondingly underlying or overlying the first wing portion Other VIA_1st or VIA_2nd patterns. In an embodiment, the layout diagram further includes a transistor level, which corresponds to a transistor layer in the semiconductor device, and there is no metallization level between the M_1st level and the transistor layer. In an embodiment, the method further comprises: based on the layout, performing at least one of: (A) performing one or more photolithographic exposures; (B) fabricating one or more semiconductor masks; or (C) Fabrication of at least one component in a layer of a semiconductor integrated circuit.

In an embodiment, a system (for manufacturing semiconductor components) includes at least one processor and at least one memory, the at least one Memory includes computer code for one or more programs; at least one memory, computer code, and at least one processor for causing the system to execute (for layouts stored on non-transitory computer-readable media, The semiconductor device is based on a layout diagram that includes first and overlying second metallization levels (corresponding to the M_1st and M_2nd levels) and a first interconnection level therebetween (VIA_1st level), corresponding to the first and upper metallization levels in the semiconductor device overlying the second metallization layer and the first interconnect layer therebetween), and generating the layout diagram includes the following steps. A candidate pattern in the layout is selected; the candidate pattern is the first conductive pattern in the M_2nd level (the first M_2nd pattern) or the first conductive pattern in the M_1st level (the first M_1st pattern); the candidate pattern is determined to satisfy one or more criteria , and changing the size of the candidate pattern, thereby revising the layout; and wherein the layout further includes a transistor level, the transistor level corresponding to the transistor layer in the semiconductor device, and no metal between the M_1st level and the transistor layer level. In an embodiment, the layout diagram includes first and overlying second metallization levels (corresponding to M_1st and M_2nd levels) and a first interconnection level therebetween (VIA_1st level), corresponding to first and overlying second metallization levels in the semiconductor device two metallization layers and a first interconnect layer therebetween; and the candidate pattern is a first M_2nd pattern; determining that the candidate pattern satisfies one or more criteria includes: determining that the first M_2nd pattern is designated as a pin hole pattern; The first via pattern in the (first VIA_1st pattern) is the only VIA_1st pattern covered by the first M_2nd pattern; changing the size of the candidate pattern includes removing the first M_2nd pattern from the layout; and generating the layout further includes replacing The corresponding underlying first pattern (the first M_1st pattern) in the first level is designated as the pin hole pattern. In an embodiment, the first M_2nd pattern is specified As a pin hole pattern, since the first VIA_1st pattern in the VIA_1st interconnect level has at least first and second allowable overlying positions, at least the corresponding first and second M_2nd patterns in the M_2nd level at these positions Can be positioned to cover the first VIA_1st pattern; or designate the first M_2nd pattern as the pinhole pattern, since the corresponding first via pattern (the first VIA_2nd pattern) in the second interconnect level (VIA_2nd level) has at least the first and second allowable overlying locations at which at least corresponding first and second conductive patterns (first and second M_3rd patterns) in the third metallization level (M_3rd) can be positioned to cover the third metallization level (M_3rd) A VIA_2nd pattern. In an embodiment, the layout diagram further includes a second interconnect level (VIA_2nd level) overlying the first M_1st level and corresponding to a second interconnect level, the second interconnect level overlying the first metallization layer in the semiconductor device; and the candidate pattern is the first M_1st pattern; determining that the candidate pattern satisfies one or more criteria includes: a first sub-method, the first sub-method includes determining that the first M_1st pattern does not cover at least the first via pattern in the VIA_1st level (the first VIA_1st pattern); and determining that the first M_1st pattern is not covered by at least the first via pattern in the VIA_2nd level (the first VIA_2nd pattern); or the second sub-method , the second sub-method includes determining, with respect to the first direction, that the first M_1st pattern covers at least the first via pattern (the first VIA_1st pattern) in the VIA_1st level or the first M_1st pattern is covered by at least the first via pattern in the VIA_2nd level Layer hole pattern (first VIA_2nd pattern) overlay; in the context of the first sub-method, changing the size of the candidate pattern includes removing the first M_1st pattern from the layout; and in the context of the second sub-method, changing the size of the candidate pattern Size includes trim first the first wing portion of the M_1st pattern to result in a correspondingly smaller first nub portion; and wherein relative to the first direction, there is at least one of the first VIA_1st pattern or the first VIA_2nd pattern such that the first wing portion It is located between the first end of the first M_1st pattern and the first VIA_1st pattern or the first VIA_2nd pattern without corresponding other VIA_1st or VIA_2nd patterns underlying or overlying the first wing portion. In an embodiment, the layout diagram further includes a transistor level, which corresponds to a transistor layer in the semiconductor device, and there is no metallization level between the M_1st level and the transistor layer. In an embodiment, the system further includes at least one of: a masking facility for fabricating one or more semiconductor masks based on the layout; or a fabrication facility for fabricating based on The layout fabricates at least one component in a layer of the semiconductor integrated circuit. In embodiments, as aspects included in the fabrication of one or more semiconductor masks, the mask facility is further configured to perform one or more lithographic exposures based on the layout; or as a layer included in a semiconductor integrated circuit During the fabrication of at least one component in the fab, the fabrication facility is further configured to perform one or more lithographic exposures based on the layout.

1.5CPP。在實施例中，此方法進一步包括：基於佈局圖，進行如下各者中之至少一者：(A)進行一或多次光微影曝光；(B)製造一或多個半導 體遮罩；或(C)製造半導體積體電路之層中的至少一個部件。 In an embodiment, a method (of fabricating a semiconductor device) includes (for a layout stored on a non-transitory computer-readable medium, the semiconductor device is based on a layout, the layout includes a first and an overlying second metal The metallization level (corresponding to the M_1st and M_2nd levels) and the first interconnection level therebetween (VIA_1st level), corresponding to the first and overlying second metallization layers in the semiconductor element and the first interconnection layer in between) generate a layout diagram , including: selecting a candidate pattern in the layout, the candidate pattern being the first conductive pattern in the M_1st level (the first M_1st pattern); determining that the candidate pattern satisfies one or more criteria; and increasing the size of the candidate pattern, thereby revising Layout. In an embodiment, the layout diagram further includes a transistor level, the transistor level corresponding to a transistor layer in the semiconductor element; the cells of the layout diagram are organized into MD rows, the MD rows extending in the first direction; relative to A second direction, substantially perpendicular to the first direction, for the first and last rows in the MD row positioned proximate to the first and second boundaries of the cells, determining that the candidate pattern satisfies one or more criteria includes: determining a transistor level a first metal-to-drain/source (MD) pattern in the first or last MD row; determining that the first MD pattern is covered by a first gate-drain/source (VGD) via pattern; determining The first VGD pattern is covered by the first conductive pattern (the first M_1st pattern) in the M_1st level; and determining that the length of the first M_1st pattern is smaller than the first reference distance; increasing the size of the candidate pattern includes: with respect to the second direction, changing the The length of the first M_1st pattern is increased to at least substantially equal to the first reference distance, and wherein the first MD pattern and the first VGD pattern represent corresponding MD and VGD structures in the transistor layer of the semiconductor element. In an embodiment, the first reference distance is greater than the second reference distance; and the second reference distance represents the minimum length of the conductive segment in layer M0 relative to typical manufacturing tolerances of the semiconductor technology process generation in which the semiconductor device is produced. In an embodiment, the first reference distance is denoted by L2; and L2 is greater than a contact polysilicon pitch (CPP) corresponding to a semiconductor technology process generation of the semiconductor device. In an embodiment, the layout diagram further includes a transistor level, the transistor level corresponding to a transistor layer in the semiconductor device; no metallization level between the M_1st level and the transistor layer; and L2

1.5CPP. In an embodiment, the method further comprises: based on the layout, performing at least one of: (A) performing one or more photolithographic exposures; (B) fabricating one or more semiconductor masks; or (C) Fabrication of at least one component in a layer of a semiconductor integrated circuit.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand aspects of the embodiments of the present disclosure. Those skilled in the art should appreciate that they may readily use the embodiments of the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may be made herein without departing from the spirit and scope of the embodiments of the present disclosure Various changes, substitutions and substitutions.

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Claims (11)

A method of fabricating a semiconductor device, comprising: for a layout stored on a non-transitory computer-readable medium, a semiconductor device is based on the layout, the layout including a first metallization level and overlying A second metallization level of the first metallization level and a first interconnection level between the first metallization level and the second metallization level, the layout corresponding to a first one in the semiconductor device A metallization layer, a second metallization layer overlying the first metallization layer, and a first interconnection layer between the first metallization layer and the second metallization layer, generating the layout, including: Selecting a candidate pattern in the layout, the candidate pattern is a first conductive pattern in the second metallization level or a first conductive pattern in the first metallization level, and the candidate pattern corresponds to the semiconductor A structure in an element; determining that the candidate pattern satisfies one or more criteria corresponding to generating the layout, comprising: a first sub-method comprising: determining that the first conductive pattern in the first metallization level does not cover at least a first via pattern in the first interconnect level; and determining that the first conductive pattern in the first metallization level is not affected by at least the first via pattern in the second interconnect level Override; or a second submethod, including: Relative to a first direction, it is determined that the first conductive pattern in the first metallization level covers at least the first via pattern in the first interconnection level; or relative to a first direction, the first conductive pattern is determined to cover at least the first via pattern in the first interconnection level. The first conductive pattern in a metallization level is covered by at least the first via pattern in the second interconnect level; or a third sub-method comprising: determining the first via pattern in the second metallization level a conductive pattern is designated as a pin hole pattern; and a first via pattern in the first interconnect level is determined as a unique first via pattern covered by the first conductive pattern in the second metallization level an interconnect pattern; and reducing at least a size of one of the candidate patterns, thereby revising the layout. The method for manufacturing a semiconductor device according to claim 1, wherein: the first metallization level, the second metallization level and the first interconnection level correspond to the first metallization layer, the second metallization layer and the first interconnect layer; the candidate pattern is the first conductive pattern in the second metallization level; the step of reducing at least one size of the candidate pattern includes: removing the first conductive pattern in the second metallization level from the layout; the step of generating the layout further comprising: alternatively designating a corresponding one of the underlying first patterns in the first metallization level as a pinhole pattern; and designating the first conductive pattern in the first metallization level as a pin hole pattern because the first via pattern in the first interconnect level has a first allowable overlying location and a first At least one of two permitted overlying locations, at least one of the first permitted overlying location and the second permitted overlying location, the corresponding second metallization in the second metallization level The first conductive pattern in the level and a second conductive pattern in the second metallization level can be positioned to cover the first via pattern in the first interconnect level; or designate the second metallization The first conductive pattern in the level acts as a pin hole pattern because a corresponding first via pattern in a second interconnect level has the first allowable overlying position and the second allowable overlying position in the At least one, at at least one of the first allowable overlying position and the second allowable overlying position, a first conductive pattern and a second conductive pattern corresponding to at least one third metallization level can be is positioned to cover the corresponding first via pattern in the second interconnect level. The method of manufacturing a semiconductor device of claim 1, wherein: the layout further includes a second interconnection level, the second interconnection level overlying the first metallization level and corresponding to a second interconnection level , the second interconnect layer overlies the first metallization layer in the semiconductor device, and the candidate pattern is the first conductive pattern in the first metallization level; in the context of one of the first sub-methods, at least the step of reducing the size of the candidate pattern comprises: removing the first conductive pattern from the layout the first conductive pattern in a metallization level; and in the context of one of the second sub-methods, at least reducing the size of the candidate pattern comprises: trimming the first conductive pattern in the first metallization level a first wing portion of the pattern to result in a smaller first nub portion; and wherein relative to the first direction, there is the first via pattern or the second interconnect in the first interconnect level at least one of the first via patterns in the level such that the first wing portion is located in a first end of the first conductive pattern in the first metallization level and in the first interconnect level between the first via pattern or the first via pattern in the second interconnect level without correspondingly underlying or overlying the first wing portion in the other first interconnect levels The first via pattern or the first via pattern in the second interconnect level. The method for manufacturing a semiconductor device according to claim 1, further comprising: based on the layout diagram, performing at least one of the following: (A) performing one or more photolithography exposures; (B) manufacturing one or more multiple semiconductor masks; or (C) Fabricating at least one component in a layer of a semiconductor integrated circuit. A system for manufacturing a semiconductor device, comprising: at least one processor; and at least one memory including computer code for one or more programs; wherein the at least one memory, the computer code and the at least one memory A processor for causing the system to execute: for a layout stored on a non-transitory computer-readable medium, the semiconductor device is based on the layout, the layout including a first metallization level and overlying A second metallization level of the first metallization level and a first interconnection level between the first metallization level and the second metallization level, the layout corresponding to a first one in the semiconductor device A metallization layer, a second metallization layer overlying the first metallization layer, and a first interconnection layer between the first metallization layer and the second metallization layer, generating the layout, including: Selecting a candidate pattern in the layout, the candidate pattern is a first conductive pattern in the second metallization level or a first conductive pattern in the first metallization level, and the candidate pattern corresponds to the semiconductor A structure in the component; determining that the candidate pattern satisfies one or more criteria corresponding to generating the layout, including: a first sub-method, including: determining that the first conductive pattern in the first metallization level does not cover at least a first via pattern in the first interconnection level; and determining that the first conductive pattern in the first metallization level is not covered by at least the first via pattern coverage in the second interconnect level; or a second sub-method comprising: determining, with respect to a first direction, the first conductive pattern coverage in the first metallization level at least The first via pattern in the first interconnect level or the first conductive pattern in the first metallization level is covered by at least the first via pattern in the second interconnect level; or a A third sub-method includes: determining that the first conductive pattern in the second metallization level is designated as a pin hole pattern; determining a first via pattern in the first level to be designated by the second metal a unique first interconnect pattern covered by the first conductive pattern in the chemical layer; and changing a size of the candidate pattern, thereby revising the layout; and wherein: the layout further includes a transistor level, the a transistor level corresponding to a transistor layer in the semiconductor element; and There is no metallization level between the first metallization level and the transistor layer. The system for manufacturing a semiconductor device of claim 5, wherein: the first metallization level, the second metallization level, and the first interconnection level correspond to the first metallization in the semiconductor device, respectively layer, the second metallization layer and the first interconnect layer; the candidate pattern is the first conductive pattern in the second metallization level; the step of changing a size of the candidate pattern includes: shifting from the layout The step of removing the first conductive pattern in the second metallization level; and the step of generating the layout further includes: alternatively assigning a corresponding one of the underlying first patterns in the first metallization level as a pin hole pattern; and assigning The first conductive pattern in the first metallization level acts as a pin hole pattern because the first via pattern in the first interconnect level has a first allowable overlying location and a second allowable overlying location at least one of the overlying locations, at least one of the first permitted overlying location and the second permitted overlying location, the one of the second metallization levels corresponding to the one of the second metallization levels The first conductive pattern and a second conductive pattern in the second metallization level can be positioned to cover the first via pattern in the first interconnect level; or specify the one in the second metallization level The first conductive pattern acts as a pin hole pattern because a second interconnect level corresponds to a first The layer hole pattern has at least one of the first allowable overlying position and the second allowable overlying position, at at least one of the first allowable overlying position and the second allowable overlying position, A corresponding first conductive pattern and a second conductive pattern in at least a third metallization level can be positioned to cover the corresponding first via pattern in the second interconnect level. The system for fabricating semiconductor devices of claim 5, wherein: the layout further includes a second interconnect level, the second interconnect level overlying the first metallization level and corresponding to a second interconnect level an interconnect layer, the second interconnect layer overlies the first metallization layer in the semiconductor device, and the candidate pattern is the first conductive pattern in the first metallization level; in one of the first sub-methods In the context, the step of changing a size of the candidate pattern comprises: removing the first conductive pattern in the first metallization level from the layout; and in the context of one of the second sub-methods, changing the candidate pattern The step of a size includes: trimming a first wing portion of the first conductive pattern in the first metallization level to result in a correspondingly smaller first nub portion; and wherein with respect to the first direction, At least one of the first via pattern in the first interconnect level or the first via pattern in the second interconnect level is present such that the first wing portion is located in the The relationship between a first end of the first conductive pattern in the first metallization level and the first via pattern in the first interconnection level or the first via pattern in the second interconnection level There is no corresponding first via pattern in the other first interconnect level or the first via pattern in the second interconnect level underlying or overlying the first wing portion. A method of fabricating a semiconductor device, comprising: for a layout stored on a non-transitory computer-readable medium, the semiconductor device is based on the layout, the layout including a first metallization level and overlying A second metallization level of the first metallization level and a first interconnection level between the first metallization level and the second metallization level, the layout corresponding to a first one in the semiconductor device A metallization layer, a second metallization layer overlying the first metallization layer, and a first interconnection layer between the first metallization layer and the second metallization layer, generating the layout, including: Selecting a candidate pattern in the layout diagram, the candidate pattern is a first conductive pattern in the first metallization level, and the candidate pattern corresponds to a structure in the semiconductor device; determining that the candidate pattern satisfies the requirements corresponding to the generation of One or more criteria of the layout, including: determining that a first metal-to-drain/source pattern in the transistor level is located in the first MD row or the last MD row; determining the first metal-to-drain the electrode/source pattern is covered by a first gate-drain/source via pattern; determining that the first gate-drain/source via pattern is covered by the first conductive pattern in the first metallization level; and determining a length of the first conductive pattern in the first metallization level less than a first reference distance; and increasing a size of the candidate pattern, thereby revising the layout. The method of manufacturing a semiconductor device of claim 8, wherein: the layout further includes a transistor level, the transistor level corresponding to a transistor layer in the semiconductor device; a cell of the layout is organized into A plurality of MD rows, the MD rows extending in a first direction; with respect to a second direction substantially perpendicular to the first direction, for those of the MD rows positioned proximate the first boundary of the cell and the second direction A first MD row and a last MD row of two boundaries, the step of increasing a size of the candidate pattern includes: with respect to the second direction, a length of the first conductive pattern in the first metallization level increased to at least substantially equal to the first reference distance; and wherein the first metal-to-drain/source pattern and the first gate-drain/source via pattern represent the transistor of the semiconductor device Corresponding MD and VGD structures in layers. The method of manufacturing a semiconductor device as claimed in claim 8, wherein: A first reference distance is denoted by L2; L2 is greater than a contact polysilicon pitch (CPP) corresponding to a semiconductor technology process generation of the semiconductor device; the layout further includes a transistor level corresponding to the semiconductor device a transistor layer; no metallization level between the first metallization level and the transistor layer; and L2 is about 1.5 CPP. The method for manufacturing a semiconductor device according to claim 8, further comprising: based on the layout diagram, performing at least one of the following: (A) performing one or more photolithography exposures; (B) manufacturing one or more a plurality of semiconductor masks; or (C) fabricating at least one component in a layer of a semiconductor integrated circuit.

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