TWI764297B - accumulator circuit - Google Patents

Abstract

An accumulating circuit includes a signal detector, a counter and a plurality of basic circuits. The plurality of basic circuits are connected to the signal detector and the counter, and respectively receive a plurality of signals. When the signal received by the Mth basic circuit of the plurality of basic circuits is at the first level, the Mth basic circuit provides a preset response data to the signal detector and the counter, so that the signal detector and the count value of the counter is increased to accumulate the number of signals having the first level.

Description

accumulator circuit

The present invention relates to an accumulating circuit, in particular to an accumulating circuit with a simple structure and a small area.

In the memory, bad memory bits will be generated due to various non-ideal factors in the manufacturing process. Therefore, when the memory is initially designed, some of the internal space is used to set up redundant memory bits. When the memory is tested and found to have When the bad memory bits are bad, the bad memory bits can be replaced by the surplus memory bits, so as to exert the repairing effect and improve the manufacturing yield of the memory. The traditional way of repairing memory is to add auxiliary circuits for row redundancy or column redundancy in the design, so that when a bad memory bit is found in the memory, it can replace the bad memory bit. A row or column of elements.

However, the conventional method is to replace an entire row or column of memory bits, so in addition to replacing bad memory, good memory bits in a row or column are also replaced, causing waste. In addition, as the memory size shrinks and the memory capacity increases, the density of the memory bit array increases, so the number of bad memory bits also increases, and the space requirement for setting redundant rows or columns also increases, resulting in To allocate enough extra rows or extra columns of memory bits to replace, the extra area required is quite large. Therefore, the method of replacing a whole row or a whole column of memory bits is not suitable for a small-volume and large-capacity memory. Compared with the conventional method, the present invention uses the bit-to-bit method to achieve a more efficient repair effect under the condition of having the same or less redundant memory as the conventional method.

One of the objectives of the present invention is to provide an accumulating circuit.

According to the present invention, an accumulating circuit includes a signal detector and a counter and a plurality of basic circuits. The plurality of basic circuits are connected to the signal detector and the counter, and respectively receive a plurality of signals. When the signal received by the Mth basic circuit of the plurality of basic circuits is at the first level, the Mth basic circuit provides a preset response data to the signal detector and the counter, so that the signal detector and the count value of the counter is increased to accumulate the number of signals having the first level. The plurality of basic circuits are composed of logic gates, so the structure of the accumulating circuit is relatively simple and the area is small.

1 shows a memory 10 to which the present invention is applied, which includes a plurality of memory bits G1 ˜Gm and R1 ˜Rn, a reordering circuit 12 and a plurality of input and output terminals I/O1 ˜I/Om, wherein m and n are positive Integer. Memory bits G1~Gm are general memory bits, while memory bits R1~Rn are redundant memory bits, data DG1 to data DGm are data stored in memory bits G1~Gm, data DR1 to data DRn are memory bits Data stored in elements R1~Rn. In the following description, for convenience of description and easier understanding of the technology of the present invention, the data DG1 ˜DGm and DR1 ˜DRn are regarded as memory bits G1 ˜Gm and R1 ˜Rn, respectively. The memory 10 generates a plurality of bit repair data RPG1 to RPGm and RPR1 to RPRn after detection, wherein the bit repair data RPG1 to RPGm respectively correspond to the general memory bits G1 to Gm, and the bit repair data RPR1 to RPRn respectively correspond to the redundant bits. The memory bits R1~Rn, a plurality of bit repair data RPG1~RPGm and RPR1~RPRn are used to mark whether the corresponding memory bits are bad bits. The reordering circuit 12 selects m good memory bits from the plurality of memory bits 12 according to the plurality of bit patching data RPG1 ˜RPGm and RPR1 ˜ RPRn, and sequentially couples them to the plurality of input and output terminals I/ O1~I/Om. The reordering circuit 12 will determine whether the general memory bits G1~Gm are good bits, and if so, couple them to the input and output terminals I/O1~I/Om, if there are bad bits in the general memory bits G1~Gm For bits, good bits are selected from the redundant memory bits R1 ˜Rn to replace the bad general memory bits, and are coupled to the input and output terminals I/O1 ˜I/Om.

In the embodiment of FIG. 1 , the bit G2, the bit Gm-1 and the bit R1 among the plurality of memory bits G1-Gm and R1-Rn are bad memory bits. When the reordering circuit 12 wants to When the memory bit corresponds to the input and output terminals I/O1~I/Om, it determines that the first general memory bit G1 is a good memory bit according to the bit patching data RPG1, so the bit G1 is coupled to the first input The output terminal I/O1, so the data DG1 of the bit G1 can be accessed from the input and output terminal I/O1. Then, the reordering circuit 12 learns from the bit patch data RPG2 that the second general memory bit G2 is a bad memory bit, so it discards the bit G2 and selects one of the redundant memory bits R1-Rn to replace the bit G2, at this time, the reordering circuit 12 can know from the bit repair data RPR1 and RPR2 that the first redundant memory bit R1 is a bad memory bit and the second redundant memory bit R2 is a good memory bit, so reordering The sorting circuit 12 selects the second redundant memory bit R2 to replace the bit G2, and couples it to the second I/O terminal I/O2, so that the bit R2 can be accessed from the I/O terminal I/O2. Data DR2. By analogy, the reordering circuit 12 sequentially determines whether the bits G3 to Gm are good memory bits according to the bit patch data RPG3 to RPGm, and if so, the reordering circuit 12 is coupled to the input and output terminals I/O3 to I/Om. For bad memory bits, such as bit Gm-1, a good and unused memory bit R3 is selected from the surplus memory bits and coupled to the input and output terminals I/Om-1. After the reordering circuit 12 associates the input and output terminals I/O1 to I/Om with the memory bits one-to-one, the host can access the data of the corresponding memory bits through the input and output terminals I/O1 to I/Om.

FIG. 2 shows an embodiment of the reordering circuit 12 in FIG. 1 , which includes a plurality of judgment circuits 20 , 22 , 24 and 26 , a plurality of multiplexers 30 , 32 , 34 and 36 , and a redundant bit sorting circuit 40 . The first judgment circuit 20 among the plurality of judgment circuits 20 , 22 , 24 and 26 generates a selection signal Se1 and an accumulation signal Sol according to the bit patch data RPG1 . The second judging circuit 22 generates the selection signal Se2 and the accumulation signal So2 according to the bit patch data RPG2 and the accumulation signal So1. The third judging circuit 24 generates the selection signal Se3 and the accumulation signal So3 according to the bit patch data RPG3 and the accumulation signal So2. By analogy, the plurality of judgment circuits 20 , 22 , 24 and 26 each receive a bit patch data RPG1 to RPGm and output a selection signal Se1 to Sem respectively. Except for the first judgment circuit 20 , the rest of the judgment circuits 22, 24 and 26 all generate selection signals Se2 to Sem according to the received bit patch data and the accumulated signals So1 to Som-1 output by the previous judgment circuit, wherein the plurality of accumulated signals So1 to Som-1 record the next one. The amount of spare memory that can be used or records the amount of spare memory bits that have been used. The redundant bit sorting circuit 40 connects the good memory bits among the redundant memory bits R1 ˜Rn (DR1 ˜DRn) to each of the multiplexers 30 , 32 , 34 and 36 according to the plurality of bit repair data RPR1 ˜RPRn. Referring to FIG. 1 , in this embodiment, the memory bit R1 has defects, so the redundant bit sorting circuit 40 excludes the bit R1, so that the output RI of the redundant bit sorting circuit 40 is DR2˜DRn (R2˜Rn). The output terminals of the multiplexers 30 , 32 , 34 and 36 are each connected to an input and output terminal I/O1 ˜I/Om. The first multiplexer 30 determines to couple the normal memory bit G1 or one of the redundant memory bits R2 to Rn (DG1 or DR2 to DRn) to the first input according to the bit patch data RPG1 and the selection signal Se1 The output terminal I/O1, in this embodiment, the general memory bit G1 is a good bit, so the multiplexer 30 selects to couple the general memory bit G1 (DG1) to the input and output terminal I/O1. The second multiplexer 32 couples one of the general memory bit G2 or the redundant memory bits R2 to Rn to the second input/output terminal I/O2 according to the bit patch data RPG2 and the selection signal Se2, In this embodiment, the general memory bit G2 is a bad bit, so the multiplexer 32 selects the bit R2 (DR2) from the redundant memory bits R2-Rn (DR2-DRn) to be coupled to the input and output terminals I/ O2. By analogy, each of the multiplexers 30 , 32 , 34 and 36 couples a memory bit to the corresponding input and output terminals I/O1 ˜I/Om.

FIG. 3 shows the multiplexer 30 of FIG. 2, which includes a plurality of inverters 3002, 3003, 3005, 3007, 3009, 3011, 3013, 3015, 3017 and 3019, a plurality of switches 3004, 3008, 3012, 3016 and 3020 and a plurality of AND gates 3006, 3010, 3014 and 3018, the selection signal Se1 includes a plurality of signals RENB11-RENB1n respectively input to a plurality of inverters 3005, 3009, 3013, 3017 and 3019, a plurality of inverters 3005, 3009, The outputs of 3013, 3017 and 3019 are respectively connected to one input terminal of the multiple AND gates 3006, 3010, 3014 and 2018, and the other input terminal of the multiple AND gates 3006, 3010, 3014 and 3018 receives the bit repair data RPG1. The switch 3004 is connected between the general memory bit G1 ( DG1 ) and the input/output terminal I/O1 , and the bit patch data RPG1 controls the switch 3004 to be turned on or off through the inverters 3002 and 3003 . The switch 3008 is connected between the redundant memory bit R2 (DR2) and the input/output terminal I/O1, and the gate 3006 controls the switch 3008 to be turned on or off according to the bit repair data RPG1 and the signal RENB11. The switch 3012 is connected between the redundant memory bit R3 (DR3) and the input/output terminal I/O1, and the gate 3010 controls the switch 3012 to be turned on or off according to the bit repair data RPG1 and the signal RENB12. The switch 3016 is connected between the redundant memory bit R4 (DR4) and the input/output terminal I/O1, and the gate 3014 controls the switch 3016 to be turned on or off according to the bit repair data RPG1 and the signal RENB13. The switch 3020 is connected between the redundant memory bit Rn (DRn) and the input/output terminal I/O1, and the gate 3018 controls the switch 3020 to be turned on or off according to the bit repair data RPG1 and the signal RENB1n. When the bit patch data RPG1 is "0", the switch 3004 is turned on, so that the memory bit G1 (DG1) is coupled to the input/output terminal I/O1, and the gates 3006, 3010, 3014 and 3018 all output a low level A logic signal "0" causes switches 3008, 3012, 3016 and 3020 to close. When the bit patch data RPG1 is "1", the switch 3004 is closed, and the switches to be turned on are determined by the signals RENB11~RENB1n. For example, when the signal RENB11 is "0" and the other signals REN12~REN1n are "1", the switch 3008 is turned on so that the redundant memory bit R2 (DR2) is coupled to the input/output terminal I/O1. When the signal REN1n is "0" and the remaining signals REN11~REN1n-1 are "1", the switch 3020 is turned on to make The redundant memory bits Rn (DRn) are coupled to the input and output terminals I/O1.

Although only the circuit of the multiplexer 30 is shown in FIG. 3 , the circuits and operations of the other multiplexers 32 , 34 and 36 are similar to the multiplexer 30 , and other multiplexers can be easily deduced from the multiplexer 30 of FIG. 3 Circuitry and operation of 32, 34 and 36.

FIG. 4 shows a basic circuit 50 constituting the judgment circuit in FIG. 2 . Each of the judgment circuits 20 , 22 , 24 and 26 is composed of a plurality of basic circuits 50 , as shown in FIG. 5 . The basic circuit 50 of FIG. 4 is a logic circuit composed of logic gates, which includes three inversion gates 52 , 56 and 58 and an inverter 54 , and the output terminal of the inversion gate 52 is connected to the inversion gates 56 and 58 . An input terminal, the bit repair data RP is input to the other input terminal of the inversion gate 56 through the inverter 54, and the other input terminal of the inversion gate 58 receives the bit repair data RP, and the output of the inversion gate 58 is used for to form the selection signal output by the judgment circuit. When one of the inputs of the inversion gate 52 is "0" (reaction data), the bit patch data RP will determine the preset reaction data on the input of the inversion gate 52 as the output of the inversion gate 56 or 58, In this embodiment, the response data is "0", when the bit repair data RP is "1", it means that the current general memory bit is a bad bit, and the output of the anti-and gate 58 is the response data "0" ”, select an extra memory bit to replace the current general memory bit, and is coupled to the input and output terminals of the memory 10 . When the bit patch data RP is "0", it means that the current general memory bit is a good bit, and the output of the anti-and gate 56 is the response data "0", so that the current general memory bit is coupled to the memory 10 input and output terminals. Fig. 6 shows the concept of the circuit of Fig. 4. When the bit repair data RP is "1", it is equivalent to move the preset response data "0" to the output of the inverse gate 58 at the lower right, so that the response data "0" , appear in different positions relative to the input, and when the bit patch data RP is "0", it is equivalent to moving the output of the inversion gate 52 to the right to the output of the inversion gate 56, so that the designed data appears in the The same position relative to the input.

In FIG. 5, each of the judgment circuits 20, 22 and 24 is formed by stacking more than n basic circuits 50, where n is the number of redundant memory bits, and the output of each basic circuit 50 becomes the output of the next judgment circuit. enter. Because the preset response data GND=“0” is placed on the input of the basic circuit 50 at the upper left, the output at the lower right of the relative position becomes the accumulated number of bit repairs and the desired selection signal, wherein the inversion gate in the judgment circuit 20 is The signals RENB11, RENB12 and RENB13 output by 58 constitute the selection signal Se1 in FIG. 2, and the signals Sa11, Sa12, Sa13, RENB11, RENB12 and RENB13 output by the reverse gates 56 and 58 constitute the accumulation of the judgment circuit 20 in FIG. 2. Signal So1. The signals RENB21, RENB22 and RENB23 output by the inversion gate 58 in the judgment circuit 22 constitute the selection signal Se2 in FIG. 2, and the signals Sa21, Sa22, Sa23, RENB21, RENB22 and RENB23 output by the inversion gates 56 and 58 constitute The output So2 of the judgment circuit 22 in FIG. 2 . The signals RENB31, RENB32 and RENB33 output by the inversion gate 58 in the judgment circuit 24 constitute the selection signal Se2 in FIG. 2, while the signals Sa31, Sa32, Sa33, RENB31, RENB32 and RENB33 output by the inversion gates 56 and 58 constitute The output So3 of the judgment circuit 24 in FIG. 2 . Figure 7 shows the concept of the circuit in Figure 5. Referring to Figures 5 and 7, in the judgment circuit 22, since the bit repair data RPG2 is "1", the response data "0" moves downward, as shown in Figure 7, so that The selection signal Se2 becomes "011", so the first good redundant memory bit R2 is selected to be coupled to the input and output terminals I/O2, and the position of the response data "0" in the selection signal determines the redundant memory bit to be selected For example, when the selection signal is "101", the second good redundant memory bit R3 will be selected to be coupled to the input and output I/O, and when the selection signal is "110", the third good memory bit R3 will be selected. The redundant memory bit R4 is coupled to the input and output terminals I/O, and so on. FIG. 5 only shows part of the circuits of the judgment circuits 20 , 22 and 24 , and those skilled in the art can deduce the complete circuits of the judgment circuits 20 , 22 and 24 from the content disclosed in FIG. 5 . In this embodiment, the judging circuits 20, 22 and 24 are realized by a plurality of inverting gates 52, 56 and 58, but the judging circuits 20, 22 and 24 are not limited to be realized by inverting and An inverse-OR gate can be implemented by using a variety of different logic gate elements. For example, when the default response data is "1 (VDD)", the inverse-OR gates 52, 56 and 58 can be replaced by inverse-OR gates.

In other embodiments, the basic circuit 50 of FIG. 4 can also be modified to the switch circuit of FIG. 8, which includes a PMOS transistor 60 and an NMOS transistor 62, and the input terminals of the transistors 60 and 62 receive the response data “1” or “ 0", the control end receives the bit repair data RP. When the bit repair data RP is "0", the PMOS transistor 60 is turned on and the NMOS transistor 62 is turned off, so the response data "1" or "0" is output from the upper PMOS transistor 60. When the bit repair data RP is "1", the PMOS transistor 60 is turned off and the NMOS transistor 62 is turned on, so the response data "1" or "0" is output from the NMOS transistor 60 below.

FIG. 9 shows another embodiment of the present invention for reordering memory bits. The reordering circuit 12 in FIG. 9 sequentially couples the good bits in the plurality of memory bits G1 ˜Gm and R1 ˜Rn to a plurality of inputs and outputs Terminal I/O1~I/Om. The reordering circuit 12 can determine whether the plurality of memory bits G1~Gm and R1~Rn are bad bits through the bit repair data RPG1~RPGm and RPR1~RPRn. As shown in FIG. 9, the reordering circuit 12 passes the bits The meta-patching data RPG1 knows that the first memory bit G1 is a good bit, so the memory bit G1 is coupled to the first input/output terminal I/O1, when the reordering circuit 12 knows the second memory bit G1 through the bit-patching data RPG2 When one memory bit G2 is a bad bit, the memory bit G2 is discarded, and then the reordering circuit 12 couples the memory bit G3 when it knows the third memory bit G3 is a good bit through the bit patch data RPG3 to the second input/output terminal I/O2, and so on, until all the input/output terminals I/O1-I/Om are coupled to a memory bit.

FIG. 10 shows an embodiment of the reordering circuit 12 in FIG. 9 , which includes a plurality of determination circuits 70 , 72 , 74 and 76 and a plurality of multiplexers 78 , 80 , 82 and 84 . The first judging circuit 70 receives the first bit repair data RPG1 and the following N bit repair data RPG2 to RPGN+1 among the plurality of bit repair data RPG1 to RPGm and RPR1 to RPRn, and generates a selection accordingly. Signal Se1. The second judging circuit 72 receives the second bit repair data RPG2 among the plurality of bit repair data and the following N bit repair data RPG3 to RPGN+2, and generates the selection signal Se2 accordingly. By analogy, the Mth judging circuit receives the Mth bit repair data and the N subsequent bit repair data among the plurality of bit repair data, and generates the Mth selection signal SeM accordingly. In this embodiment, N is equal to n, that is, N is equal to the number of redundant memory bits. In other embodiments, N may be larger or smaller than n. The first multiplexer 78 is coupled to the judgment circuit 70 and the memory bits G1 to GN+1 (DG1 to DGN+1) corresponding to the bit patch data RPG1 to RPGN+1. G1~GN+1(DG1~DGN+1) select one of the good bits G1(DG1) to be coupled to the input/output terminal I/O1. The second multiplexer 80 is coupled to the judgment circuit 72 and the memory bits G2 to GN+2 (DG2 to DGN+2) corresponding to the bit patch data RPG2 to RPGN+2, and from the plurality of memory bits according to the selection signal Se2 G2~GN+2 (DG2~DGN+2) select one of the good bits to be coupled to the input/output terminal I/O2. In this embodiment, since the memory bit G2 (DG2) is a bad bit, there are many The processor 80 selects to couple the memory bit G3 (DG3) to the input/output terminal I/O2. The third multiplexer 82 is coupled to the judgment circuit 74 and the memory bits G3 to GN+3 (DG3 to DGN+3) corresponding to the bit patch data RPG3 to RPGN+3, and selects the memory bits from the plurality of memory bits according to the selection signal Se3. G3~GN+3 (DG3~DGN+3) select one of the good bits to be coupled to the input/output terminal I/O2. In this embodiment, since the memory bit G3 (DG3) has been selected to be coupled to the input/output terminal I/O2, so the multiplexer 82 selects to couple the memory bit G4 (DG4) to the input and output terminal I/O3. By analogy, the M-th multiplexer is coupled to the M-th judgment circuit and the memory bits corresponding to the M-th to M+N-th bit repair data. According to the selection signal SeM provided by the M-th judgment circuit, from One of the good and unused memory bits selected from the Mth to M+Nth memory bits is coupled to the Mth input/output terminal I/OM.

Figure 11 shows the multiplexer 78 of Figure 10, which includes a plurality of inverters 7802, 7803, 7805, 7807, 7809, 7811, 7813, 7815, 7817 and 7819 and a plurality of switches 7804, 7808, 7812, 7816 and 7820 , the selection signal Se1 includes a plurality of signals RENB11 ˜ RENB1N+1 , which are respectively input to the plurality of inverters 7802 , 7805 , 7809 , 7813 , 7817 and 7819 . The switch 7804 is connected between the memory bit G1 ( DG1 ) and the input/output terminal I/O1 , and the signal RENB11 controls the switch 7804 to be turned on or off through the inverters 7802 and 7803 . The switch 7808 is connected between the memory bit G2 (DG2) and the input/output terminal I/O1, and the signal RENB12 controls the switch 7808 to be turned on or off through the inverters 7805 and 7807. The switch 7812 is connected between the memory bit G3 (DG3) and the input/output terminal I/O1, and the signal RENB13 controls the switch 7812 to be turned on or off through the inverters 7809 and 7811. The switch 7816 is connected between the memory bit G4 (DG4) and the input/output terminal I/O1, and the signal RENB14 controls the switch 7816 to be turned on or off through the inverters 7813 and 7815. The switch 7820 is connected between the memory bit GN (DGN) and the input/output terminal I/O1, and the signal RENB1N+1 controls the switch 7820 to be turned on or off through the inverters 7817 and 7819. When the signal RENB11 is "0", the switch 7804 is turned on, so that the memory bit G1 (DG1) is coupled to the input/output terminal I/O1. When the signal RENB12 is "0", the switch 7808 is turned on so that the memory bit G2 (DG2) is coupled to the input/output terminal I/O1. By analogy, when the signal REN1N+1 is "0", the switch 7820 is turned on so that the memory bit GN+1 (DRn) is coupled to the input/output terminal I/O1.

Although only the circuit of multiplexer 78 is shown in FIG. 11, the circuits and operations of other multiplexers 80, 82, and 84 are similar to multiplexer 78, and other multiplexers can be easily deduced from multiplexer 78 of FIG. Circuitry and operation of 80, 82 and 84.

FIG. 12 shows a basic circuit 90 constituting the judgment circuit of FIG. 10 . Each of the judgment circuits 70 , 72 , 74 and 76 is composed of a plurality of basic circuits 90 . The basic circuit 90 of FIG. 12 is a logic circuit composed of logic gates, which includes three inversion gates 92, 96 and 98 and an inverter 94, and the output terminal of the inversion gate 92 is connected to the inversion gates 96 and 98. An input terminal, the bit repair data RP is input to the other input terminal of the inversion gate 98 through the inverter 94, and the other input terminal of the inversion gate 96 receives the bit repair data RP. The output of the inversion gate 98 is used for to form the selection signal output by the judgment circuit. When one of the inputs of the inversion gate 92 is "0" (reaction data), the bit repair data RP will determine that the response data "0" on the input terminal of the inversion gate 92 is output by the inversion gate 96 or 98, and in the other In the embodiment, the reaction data may also be "1". When the bit repair data RP is "1", it means that the corresponding memory bit is a bad bit. At this time, the output of the inverse gate 98 is the response data "0", and the memory corresponding to the bit repair data RP is a bad bit. The body element will not be coupled to the input and output terminals I/Om. Figure 13 shows the concept of the circuit in Figure 12. When the bit repair data RP is "1", it is equivalent to moving the response data "0" to the output of the inverse gate 96 on the right, so that the response data "0" appears relative to the The same position of the input, and when the bit repair data RP is "0", it is equivalent to moving the response data "0" to the lower right to the output of the anti-and gate 98, so that the response data "0" appears in a different position relative to the input .

FIG. 14 shows an embodiment of the judgment circuits 70 , 72 and 74 in FIG. 10 , and each judgment circuit 70 , 72 and 74 is formed by connecting N basic circuits 90 in series. Because the preset response data GND "0" is placed at the input of the basic circuit 90 at the upper left, the output at the lower right at the relative position becomes the desired selection signal. In FIG. 14 , the signals RENB11 , RENB12 , RENB13 and RENB14 output from the inverting gate 98 of the judgment circuit 70 constitute the selection signal Se1 in FIG. 10 . The signals RENB21 , RENB22 and RENB23 output from the inverting gate 98 in the judgment circuit 72 constitute the selection signal Se2 in FIG. 10 . The signals RENB31 and RENB32 output by the inversion gate 98 in the judgment circuit 74 constitute the selection signal Se3 in FIG. 10 . FIG. 14 only shows part of the circuits of the judgment circuits 70 , 72 and 74 , and those skilled in the art can deduce the complete circuits of the judgment circuits 70 , 72 and 74 from the content disclosed in FIG. 14 . FIG. 15 shows the concept of the circuit of FIG. 14. Referring to FIG. 11, FIG. 14 and FIG. 15, in the judgment circuit 70, the first basic circuit 90 receives the response data "0 (GND)" and the bit repair data RPG1 is "0" , so the response data "0" is output by the inversion gate 98, and the input signals of the inversion and gate 92 of the second and subsequent basic circuits 90 are all "1", so no matter what the bit repair data RPG2, RPG3, RPG4 are, The outputs of the inverter gate 98 are all “1”, as shown in FIG. 15, the selection signal Se1 becomes “0111”, so the multiplexer 78 selects to couple the memory bit G1 (DG1) to the input and output terminals I/ O1, the position of the response data "0" in the selection signal determines the redundant memory bits to be selected. In the judgment circuit 72, the first basic circuit 90 receives the response data "0" and the bit repair data RPG2 is "1", so the inversion gate 98 outputs a signal "0", and the response data "0" will be transmitted by the inversion gate 96 is sent to the second basic circuit 90. Since the bit repair data RPG3 of the second basic circuit 90 is "0", the response data "0" will be output by the inversion gate 98, and the third and subsequent basic circuits 90 The input signals of s are all "1", so no matter what the bit patch data RPG4 is, the output of the inverter gate 98 is "1", so the selection signal Se2 can be obtained as "101", so that the multiplexer 80 selects its The second memory bit G3 ( DG3 ) of the coupled memory bits is coupled to the input/output terminal I/O2 . The selection signals Se3 to Sem are also generated in the same way, so they will not be described again. In this embodiment, the judging circuits 70, 72 and 74 are realized by a plurality of inverting gates 92, 96 and 98, but the judging circuits 70, 72 and 74 are not limited to be realized by inverting and An inverse-OR gate can be implemented by a variety of different logic gate elements. For example, when the preset response data is "1", the inverse-OR gates 92, 96 and 98 can be replaced by inverse-OR gates.

In other embodiments, the basic circuit 90 of FIG. 12 can also be modified to the switch circuit of FIG. 16, which includes an NMOS transistor 100 and a PMOS transistor 102, and the input terminals of the transistors 100 and 102 receive the response data "1" or "" 0", the control end receives the bit repair data RP. When the bit repair data RP is "0", the NMOS transistor 100 is turned off and the PMOS transistor 102 is turned on, so the response data "1" or "0" is output from the PMOS transistor 102 below. When the bit repair data RP is "1", the NMOS transistor 100 turns on the PMOS transistor 102 and turns off, so the response data "1" or "0" is output from the upper NMOS transistor 100.

The circuit of Figure 5 can be used as an accumulation circuit. Referring to FIG. 5 and FIG. 7, as mentioned above, when the bit repair data RPGm is "1", it means that the corresponding memory bit is a bad bit, and the position of the set data "0" in the selection signal will be changed. Following the change, as shown in Figure 7, each time a bad bit occurs, the data "0" moves down one position, so the position of the bad memory bit can be judged according to the position of the response data "0" in the selection signal. For example, when the selection signal is "011", the data "0" appears in the first position, which means that there is a bad bit, if the selection signal is "110", the data "0" appears in the third position position, which means there are three bad bits. The judging circuits 20 , 22 , 24 and 26 of the present invention can not only be used for judging whether the corresponding memory bit is a bad bit, but also can be used as a bad bit accumulating circuit to accumulate the number of bad bits. The accumulating circuit shown in FIG. 5 is not limited to be applied to the memory, but can also be applied to circuits other than the memory to determine the number of “0” or “1” levels in a plurality of signals (RPG1 to RPGm). Similarly, the circuit of FIG. 14 can also be used as an accumulator circuit.

FIG. 17 shows an accumulating circuit 110 according to the circuit concept of FIG. 5, which includes a plurality of basic circuits 112, a plurality of switches 116, a signal detector and a counter 118, and the plurality of basic circuits 112 respectively receive a plurality of signals S1-Sm, When the accumulating circuit 110 is used to count the number of bad bits in the memory, the signals S1 ˜ Sm are bit repair data. In this embodiment, the structure of the basic circuit 112 is similar to the basic circuit 50 in FIG. 5 , and each basic circuit 112 includes three inverting gates 1121 , 1123 and 1124 and an inverter 1122 . In other embodiments, the basic circuit 112 is basically Circuit 112 may also be implemented with multiple inverting OR gates, or a combination of multiple logic gate elements. Since the basic circuit 112 is composed of simple logic gates, the structure of the accumulating circuit 110 is simple and the area is small. In the first basic circuit 112, the first input terminal of the inversion gate 1121 receives the signal GND=“0” or VDD=“1”, and the second input terminal of the inversion gate 1121 receives the signal VDD=“1”, wherein The signal GND=“0” is the default response data, the output terminal of the inverter gate 1121 is connected to an input terminal of the inverter gate 1123 and 1124 , the signal S1 is connected to the other input terminal of the inverter gate 1124 and the inverter 1122 Connect the other input terminal of the inverter gate 1123. When the signal VDD received by the first input terminal of the inversion gate 1121 of the first basic circuit 112 indicates that the accumulating circuit 110 is in a closed state, when the signal received by the first input terminal of the inversion gate 1121 is GND, it indicates that the accumulation circuit 110 is in a closed state. Circuit 110 is in an enabled state. When the signal of the first input terminal of the inversion gate 1121 of the first basic circuit 112 changes from VDD to GND, if the signal S1 is "1", then the inversion gate 1123 outputs the signal "1" and the inversion gate 1124 The output signal "0", the signal detector and the counter 118 detect that the signal output by the inversion gate 1124 is the response data "0", the count value of the signal detector and the counter 118 is increased by 1, and the signal detector And the counter 118 outputs the control signal Sc. Conversely, if the signal S1 is "0", the inversion gate 1123 outputs a signal "0" and the inversion gate 1124 outputs a signal "1", and the signal detector and counter 118 detect the output signal of the inversion gate 1124. When the signal is not the response data "0", the counter does not operate. The output terminal of the inverting and gate 1123 of the basic circuit 112 of the previous stage is connected to the first input terminal of the inverting and gate 1121 of the basic circuit 112 of the subsequent stage, and the switch 116 is connected to the second input of the inverting and gate 1121 of the basic circuit 112 of the subsequent stage. The switch 116 is controlled by the signal detector and the control signal Sc output by the counter 118. In the initial state, the initial level of the second input terminal of the inverting gate 1121 of the basic circuit 112 of the subsequent stage is set to VDD ( (not shown in the figure), when the signal output by the inverting gate 1124 is the response data "0", the signal detector and the counter 118 output the control signal Sc, so that the switch 116 switches the inverting gate 1124 of the basic circuit 112 of the previous stage The output terminal of φ is connected to the second input terminal of the inverting gate 1121 of the basic circuit 112 of the subsequent stage, so that the preset response data GND=“0” is input to the basic circuit 112 of the subsequent stage. To put it simply, in the embodiment of FIG. 17 , the M-th basic circuit 112 receives the M-th signal SM, and when the level of the M-th signal SM is “1”, the M-th basic circuit provides a preset response The data GND=“0” to the signal detector and counter 118 increases the count value of the signal detector and counter 118 to accumulate the number of signals with a level of “1”. In other embodiments, the signal detector and counter 118 may also accumulate the number of signals whose level is "0" in the signals S1 to Sm. In one embodiment, the basic circuit 112 may also be implemented with the circuit shown in FIG. 8 .

10: Memory 12: Reordering the circuit 20: Judgment circuit 22: Judgment circuit 24: Judgment circuit 26: Judgment circuit 30: Multiplexer 3002: Inverter 3003: Inverter 3004: switch 3005: Inverter 3006: and gate 3007: Inverter 3008: switch 3009: Inverter 3010: and gate 3011: Inverter 3012: switch 3013: Inverter 3014: and gate 3015: Inverter 3016: Switch 3017: Inverter 3018: and gate 3019: Inverter 3020: Switch 32: Multiplexer 34: Multiplexer 36: Multiplexer 40: redundant bit sorting circuit 50: Basic Circuit 52: Reverse and gate 54: Inverter 56: Reverse and gate 58: Reverse and gate 60: PMOS transistor 62: NMOS transistor 70: Judgment circuit 72: Judgment circuit 74: Judgment circuit 76: Judgment circuit 78: Multiplexer 7802: Inverter 7804: Switch 7803: Inverter 7805: Inverter 7807: Inverter 7808: Switch 7809: Inverter 7811: Inverter 7812: Switch 7813: Inverter 7815: Inverter 7816: switch 7817: Inverter 7819: Inverter 7820: switch 80: Multiplexer 82: Multiplexer 84: Multiplexer 90: Basic Circuits 92: Reverse and gate 94: Inverter 96: Reverse and gate 98: Reverse and gate 100: NMOS transistor 102: PMOS transistor 110: Accumulator circuit 112: Basic Circuits 116: switch 118: Signal detectors and counters

FIG. 1 shows a memory to which the reordering circuit of the present invention is applied. FIG. 2 shows an embodiment of the reordering circuit of FIG. 1 . FIG. 3 shows an embodiment of the multiplexer of FIG. 2 . FIG. 4 shows the basic circuit applied to the judgment circuit in FIG. 2 . FIG. 5 shows an embodiment of the judgment circuit in FIG. 2 . FIG. 6 shows a conceptual diagram of the basic circuit of FIG. 4 . FIG. 7 is a conceptual diagram of the circuit of FIG. 5 . FIG. 8 shows another embodiment of the basic circuit of FIG. 4 . FIG. 9 shows another embodiment of the method for reordering memory bits according to the present invention. FIG. 10 shows an embodiment of the reordering circuit of FIG. 9 . FIG. 11 shows the multiplexer of FIG. 10 . FIG. 12 shows a basic circuit constituting the judgment circuit in FIG. 10 . FIG. 13 is a conceptual diagram of the circuit of FIG. 12 . FIG. 14 shows an embodiment of the judgment circuit in FIG. 10 . FIG. 15 is a conceptual diagram of the circuit of FIG. 14 . FIG. 16 shows another embodiment of the basic circuit of FIG. 12 . Figure 17 shows an embodiment of an accumulation circuit.

110: Accumulator circuit

112: Basic Circuits

116: switch

118: Signal detectors and counters

Claims (8)

An accumulating circuit comprising: a signal detector and counter; and A plurality of basic circuits are connected to the signal detector and the counter to receive a plurality of signals respectively; Wherein, when the signal received by the Mth basic circuit of the plurality of basic circuits is at the first level, the Mth basic circuit provides a preset response data to the signal detector and the counter, so that the signal detection The count values of the detector and the counter are increased to accumulate the number of signals having the first level. The accumulating circuit of claim 1, wherein the plurality of basic circuits comprise a plurality of inverting or inverting or gates. The accumulation circuit of claim 1, wherein the plurality of basic circuits include MOS transistors. An accumulating circuit comprising: a plurality of judging circuits for receiving a plurality of signals and for counting the number of signals having a first level in the plurality of signals, each of the judging circuits having a plurality of basic circuits; wherein, each of the judging circuits receives a selection signal, and the selection signal has a plurality of bits, and one of the plurality of bits is a response data; Wherein, each of the judging circuits corresponds to one of the plurality of signals, and each of the judging circuits judges whether the corresponding signal is a first level; Wherein, when the corresponding signal is at the first level, each of the judgment circuits moves the position of the response data, and transmits the adjusted selection signal to the next judgment circuit; Wherein, when the corresponding signal is at the second level, each of the judging circuits transmits the selection signal to the next judging circuit; Wherein, in the selection signal output by the last judgment circuit of the plurality of judgment circuits, the position of the response data represents the number of signals having the first level among the plurality of signals. The accumulation circuit of claim 4, wherein the plurality of base circuits receive the corresponding signals. The accumulation circuit of claim 4, wherein one of the plurality of basic circuits receives the corresponding signal. The accumulating circuit of claim 4, wherein the plurality of basic circuits comprise a plurality of inverting or inverting or gates. The accumulation circuit of claim 4, wherein the plurality of basic circuits include MOS transistors.

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