TWI750698B - Display panel - Google Patents

Abstract

A display panel includes a substrate, a pixel array layer and a cathode. The pixel array layer is disposed on the substrate and has a plurality of light-emitting areas and a plurality of non-light-emitting areas. The pixel array layer includes a plurality of electroluminescent layers, and the electroluminescent layers are respectively located in the light-emitting areas. The cathode is disposed on the pixel array layer and electrically connected to these electroluminescent layers. The thickness of the cathode in the light-emitting area is thicker than the thickness of the cathode in the non-light-emitting area. The difference between the thickness of the cathode in the light-emitting area and the thickness of the cathode in the non-light-emitting area ranges between 1 nm and 22 nm.

Description

display panel

The present invention relates to a display panel, and more particularly, to a self-luminous display panel.

Nowadays, mobile devices, such as smart phones, use organic light-emitting diode (OLED) display panels (Organic Light Emitting Diode Display Panel, OLED Display Panel) as display screens. An image sensor is installed under the body display panel, allowing users to take pictures or take pictures from the display screen. Therefore, in the above-mentioned smart phone, the OLED display panel usually adopts electrodes made of a transparent conductive layer, such as indium tin oxide (ITO), so that the external light can pass through the organic light emitting diode. The polar body display panel is incident on the image sensor, so that the smartphone can perform the function of taking pictures or photography.

At least one embodiment of the present invention provides a display panel including cathodes with non-uniform thicknesses.

A display panel provided by at least one embodiment of the present invention includes a substrate, a pixel array layer and a cathode. The pixel array layer is disposed on the substrate and has a plurality of light-emitting regions and a plurality of non-light-emitting regions, wherein the pixel array layer includes a plurality of electroluminescent layers, and the electroluminescent layers are respectively located in the light-emitting regions. The cathode is arranged on the pixel array layer and is electrically connected to these electroluminescent layers, wherein the thickness of the cathode in the light-emitting region is greater than the thickness of the cathode in the non-light-emitting region, and the thickness of the cathode in the light-emitting region is the same as the thickness of the cathode in the non-light-emitting region The difference is between 1 nm and 22 nm.

In at least one embodiment of the present invention, the thickness of the cathode in the light-emitting region is between 16 nm and 30 nm.

In at least one embodiment of the present invention, the thickness of the cathode in the non-emitting region is between 8 nm and 15 nm.

In at least one embodiment of the present invention, the cathode includes a mixed layer and a plurality of conductive layers. The mixed layer is disposed on the pixel array layer and distributed in the light-emitting regions and the non-light-emitting regions. The conductive layers are disposed on the mixed layer and distributed in the light-emitting regions, wherein the conductive layers overlap with the electroluminescent layers respectively.

In at least one embodiment of the present invention, the mixed layer and the conductive layer both include a first metal material, and the mixed layer further includes a second metal material, wherein the surface energy of the second metal material is smaller than that of the first metal material.

In at least one embodiment of the present invention, the volume percentage of the second metal material in the mixed layer is about 10% or less.

In at least one embodiment of the present invention, each electroluminescent layer includes an electron transport layer, wherein the lowest unoccupied molecular orbital (Lowest Unoccupied Molecular Orbital, LUMO) of the second metal material is between the electron transport layer and the first metal material between the lowest unoccupied molecular orbitals of the two.

In at least one embodiment of the present invention, the cathode further includes a buffer layer. The buffer layer is disposed on the pixel array layer and distributed in the non-light-emitting regions, wherein the mixed layer covers the buffer layer.

In at least one embodiment of the present invention, the cathode includes a mixed layer and a plurality of conductive layers. The mixed layer and the conductive layers are both disposed on the pixel array layer, and the mixed layer is distributed in the non-light-emitting regions but not distributed in the light-emitting regions. The conductive layers are respectively distributed in the light-emitting regions, wherein the conductive layers overlap with the electroluminescent layers respectively, and are electrically connected to the mixed layer, and the thickness of each conductive layer is greater than that of the mixed layer.

In at least one embodiment of the present invention, the cathode includes a buffer layer and a conductive layer. The buffer layer is disposed on the pixel array layer, and distributed in the non-light-emitting regions, but not distributed in the light-emitting regions. The conductive layer is disposed on the pixel array layer and distributed in the light-emitting regions and the non-light-emitting regions, wherein the conductive layer covers the buffer layer, and the thickness of the conductive layer in the light-emitting region is greater than that in the non-light-emitting region.

In at least one embodiment of the present invention, the surface energy of the buffer layer is smaller than the surface energy of the conductive layer.

In at least one embodiment of the present invention, the lowest unoccupied molecular orbital region of the buffer layer is between the lowest unoccupied molecular orbital region of the electron transport layer and the conductive layer.

Based on the above, since the thickness of the cathode in the light-emitting region is greater than that of the cathode in the non-light-emitting region, part of the cathode in the light-emitting region has a thicker thickness, while part of the cathode in the non-light-emitting region has a thinner thickness, so that the thickness of the cathode in the non-light-emitting region is thinner. The cathode in the light emitting area is easily penetrated by light. In this way, the image photosensitive element disposed under the non-light-emitting area can smoothly receive the light from the outside from the display panel, so as to take pictures or take pictures.

In order to make the features and advantages of the present invention more obvious and easy to understand, the following specific embodiments are given in conjunction with the accompanying drawings, and are described in detail as follows.

In the following text, the dimensions (such as length, width, thickness and depth) of elements (such as layers, films, substrates and regions, etc.) in the drawings are exaggerated in unequal proportions in order to clearly present the technical features of the present application. . Therefore, the descriptions and explanations of the following embodiments are not limited to the dimensions and shapes of the elements in the drawings, but should cover the dimensions, shapes and deviations caused by actual manufacturing processes and/or tolerances. For example, the flat surfaces shown in the figures may have rough and/or non-linear features, while the acute angles shown in the figures may be rounded. Therefore, the elements shown in the drawings in this application are mainly for illustration, and are not intended to accurately depict the actual shapes of the elements, nor are they intended to limit the scope of the patent application of this application.

Secondly, words such as "about", "approximately" or "substantially" appearing in the content of this case not only cover the clearly stated numerical value and numerical value range, but also cover the understanding of those with ordinary knowledge in the technical field to which the invention belongs. The allowable deviation range of , wherein the deviation range can be determined by the error generated during measurement, for example, the error is caused by the limitations of both the measurement system or the process conditions. Further, "about" can mean within one or more standard deviations of the above-mentioned numerical value, eg, within ±30%, ±20%, ±10%, or ±5%. Words such as "about", "approximately" or "substantially" appearing in this text may be used to select acceptable ranges or standard deviations based on optical properties, etching properties, mechanical properties or other properties, not a single Standard deviation to apply all of the above optical, etch, mechanical and other properties.

FIG. 1 is a schematic cross-sectional view of a display panel according to at least one embodiment of the present invention. Referring to FIG. 1 , the display panel 100 includes a substrate 110 and a pixel array layer 120 , wherein the pixel array layer 120 is disposed on the substrate 110 and includes a plurality of electroluminescent layers 128 . Each electroluminescent layer 128 can emit light L1 and can be an organic light emitting diode (OLED), wherein each electroluminescent layer 128 can include an electron transport layer 128a, a light emitting layer (not shown) and a hole transport layer ( not shown).

The electroluminescent layers 128 may be arranged in an array, and the colors of the light rays L1 emitted by the electroluminescent layers 128 may not all be the same. For example, the light L1 emitted by three of the electroluminescent layers 128 is red light, blue light and green light, respectively. Each electroluminescent layer 128 can be regarded as a sub-pixel, and the display panel 100 can display images by utilizing the red light, blue light and green light emitted by the electroluminescent layers 128 .

In addition, the colors of the light beams L1 emitted by these electroluminescent layers 128 may all be the same. For example, the display panel 100 may further include a color filter substrate (not shown), and the light L1 emitted by the electroluminescent layers 128 may all be white light, wherein the light L1 (white light) can penetrate the color filter substrate , so that the light L1 can be converted into red light, green light and blue light, so that the display panel 100 can display images.

The pixel array layer 120 has a plurality of light-emitting regions A10 and a plurality of non-light-emitting regions A11, wherein the electroluminescent layers 128 are respectively located in the light-emitting regions A10 but not in the non-light-emitting regions A11. In the embodiment shown in FIG. 1, the pixel array layer 120 may further include a pixel definition layer 127, wherein the pixel definition layer 127 has a plurality of openings 127h, and the electroluminescent layers 128 are respectively located in the openings 127h. For example, the electroluminescent layers 128 are respectively disposed at the bottoms of the openings 127h. Therefore, the openings 127h can be basically regarded as the light-emitting area A10, and the areas other than the openings 127h can basically be regarded as the non-light-emitting area A11.

The pixel array layer 120 may further include multiple insulating layers 121 , 122 , 123 and 124 , wherein the insulating layers 121 , 122 , 123 and 124 are sequentially stacked on the substrate 110 . Therefore, the insulating layers 122 and 123 may be formed between the insulating layers 121 and 124 . In addition, the pixel definition layer 127 may be disposed on the insulating layer 124 , so the insulating layers 121 , 122 , 123 and 124 may be located between the substrate 110 and the pixel definition layer 127 .

The pixel array layer 120 may further include a plurality of control elements 126, such as transistors or diodes. Taking FIG. 1 as an example, each control element 126 may be a thin film transistor (TFT), and includes a gate electrode G26 , a drain electrode D26 , a source electrode S26 and a channel layer C26 . The channel layer C26 is formed on the substrate 110 and covered by the insulating layer 121, and the constituent material of the channel layer C26 may be a semiconductor material.

In the same control element 126, the gate electrode G26 is formed on the insulating layer 121, and is located directly above the channel layer C26. Therefore, the gate electrode G26 overlaps with the channel layer C26, and the gate electrode G26, the insulating layer 121 and the channel layer C26 form a capacitor structure. The insulating layer 122 covers the gate G26 and the insulating layer 121, and the drain D26 and the source S26 are formed on the insulating layer 122, wherein the drain D26 and the source S26 penetrate the insulating layers 122 and 121 and are connected to the channel layer below C26, so that both the drain electrode D26 and the source electrode S26 can be electrically connected to the channel layer C26.

It should be noted that, in the embodiment shown in FIG. 1 , the control element 126 is a top-gate thin film transistor (top-gate TFT), but in other embodiments, the control element 126 may be a bottom gate type thin film Transistor (bottom-gate TFT). Therefore, FIG. 1 is for illustration only, and does not limit the control element 126 to be only a top-gate type thin film transistor.

The pixel array layer 120 may further include a plurality of anodes 125 . The anodes 125 can be metal layers and are formed on the insulating layer 124, and the insulating layer 124 has a plurality of contact windows 124h, wherein the anodes 125 extend into the contact windows 124h respectively, and contact and connect the drain electrodes D26, so as to The drain electrodes D26 can be electrically connected to the anode electrodes 125 respectively.

The pixel definition layer 127 covers the anodes 125 and the insulating layer 124, wherein the openings 127h are located above the anodes 125, and the pixel definition layer 127 does not cover the anodes 125 at the openings 127h, so that the electroluminescent layer located in the openings 127h 128 can be disposed on the anode 125 and further contact and connect the anode 125. In this way, the electroluminescent layer 128 can be electrically connected to the anode 125 , wherein the anode 125 of the present embodiment can be electrically connected to the hole transport layer (not shown) of the electroluminescent layer 128 .

The pixel array layer 120 further includes a cathode 130 , wherein the cathode 130 is disposed on the pixel array layer 120 and is electrically connected to the electroluminescent layers 128 . Taking FIG. 1 as an example, the cathode 130 is disposed on the pixel definition layer 127 and extends into the openings 127h, so that the cathode 130 can contact and connect to the electroluminescent layers 128, wherein the cathode 130 can be connected to the electroluminescent layer 128 The electron transport layer 128a is shown in FIG. 1 . In this way, the cathode 130 can be electrically connected to the electroluminescent layers 128 , and each electroluminescent layer 128 can be sandwiched between the anode 125 and the cathode 130 .

Since the drain electrode D26 of the control element 126 is electrically connected to the anode 125, the gate electrode G26 can be used to turn on or off the control element 126, thereby controlling the electroluminescent layer 128 to emit light. In addition, the pixel array layer 120 may further include a plurality of scan lines and a plurality of data lines (both not shown), wherein the scan lines are respectively electrically connected to the gate electrodes G26, and the data lines are respectively electrically connected to the Source S26. In this way, the scan lines can turn on or off the control elements 126 to control the data lines to input currents to the anodes 125 , thereby controlling the electroluminescent layers 128 to emit light, so that the display panel 100 can display images.

The cathode 130 has a non-uniform thickness, wherein the thickness T11 of the cathode 130 in the light-emitting region A10 is greater than the thickness T12 of the cathode 130 in the non-light-emitting region A11, and the difference between the thickness T11 and the thickness T12 is about 1 nm to 22 nm. For example, the thickness T11 of the cathode 130 in the light-emitting area A10 may be between 16 nm and 30 nm, and the thickness T12 of the cathode 130 in the non-emitting area A11 may be between 8 nm and 15 nm. The difference between T11 and thickness T12 may be between 1 nm and 22 nm.

The cathode 130 may include a mixed layer 131, wherein the mixed layer 131 is disposed on the pixel array layer 120 and distributed in the light-emitting areas A10 and the non-light-emitting areas A11. Taking FIG. 1 as an example, the mixed layer 131 is disposed on the pixel definition layer 127 and comprehensively covers the pixel definition layer 127, wherein the mixed layer 131 further covers the sidewalls in the openings 127h, and the mixed layer 131 can be adjusted by pixel The surface relief of the definition layer 127 conformally covers the pixel definition layer 127 . Therefore, the mixed layer 131 is distributed in the light-emitting area A10 and the non-light-emitting area A11. In addition, the mixed layer 131 may have a thickness T12 as shown in FIG. 1 .

The cathode 130 may further include a plurality of conductive layers 133, and the conductive layers 133 are disposed on the mixed layer 131 and distributed in the light-emitting regions A10 respectively. The conductive layers 133 may be respectively disposed in the openings 127h, but are not substantially disposed in the regions outside the openings 127h, so the conductive layers 133 are distributed in the light-emitting regions A10 and overlap with the electroluminescent layers 128 respectively, that is, The conductive layers 133 are aligned with the electroluminescent layers 128, respectively. Since the electroluminescent layers 128 can be arranged in an array, the conductive layers 133 can be arranged in an array along with the electroluminescent layers 128 . In addition, the thickness T11 is substantially equal to the thickness of the conductive layer 133 plus the thickness T12 of the mixed layer 131 .

The mixed layer 131 and the conductive layer 133 can be made of metal material, and the entire cathode 130 can be a metal film layer, wherein the mixed layer 131 and the conductive layer 133 can be formed by evaporation and photolithography. Since the general vapor deposition does not generate plasma, the electroluminescent layer 128 will not be damaged by the plasma during the above-mentioned vapor deposition to form the cathode 130, so as to prevent the electroluminescent layer 128 from failing or malfunctioning, thereby allowing the electroluminescent layer 128 to fail. The electroluminescent layer 128 retains the original light-emitting function.

Since the thickness T11 of the cathode 130 in the light-emitting area A10 is greater than the thickness T12 of the cathode 130 in the non-light-emitting area A11, part of the cathode 130 in the light-emitting area A10 has a thicker thickness (for example, between 16 nm and 30 nm). It has a lower resistance value to help increase the current input to the electroluminescent layer 128 , thereby improving the luminous efficiency of the electroluminescent layer 128 .

The part of the cathode 130 in the non-light-emitting area A11 has a relatively thin thickness (eg, between 8 nm and 15 nm), so that light can easily penetrate the part of the cathode 130 in the non-light-emitting area A11. Therefore, an image sensing element can be disposed under the non-light-emitting area A11 of the display panel 100 in FIG. 1 , and the image sensing element can smoothly receive light from the outside world from the display panel 100 for photographing or photographing.

It should be noted that although the cathode 130 is a metal layer and has a relatively thick thickness T11 at the light-emitting area A10, the cathode 130 does not completely block the light L1 emitted by the electroluminescent layer 128, and most of the light L1 is still Cathode 130 may be penetrated. Therefore, the image displayed by the display panel 100 is not affected by the cathode 130 in the light emitting area A10 as a whole. In detail, the thickness T11 of the cathode 130 is within about 100 nm, for example, between 16 nm and 30 nm, so most of the light L1 can still penetrate the portion of the cathode 130 with the thickness T11. Therefore, on the whole, the cathode 130 does not affect the image displayed by the display panel 100 .

It is particularly mentioned that, in the embodiment shown in FIG. 1 , the conductive layer 133 is formed in the openings 127h and does not cover the upper surface 131a of the mixed layer 131 outside the openings 127h. However, in other embodiments, the conductive layer 133 may cover a small portion of the upper surface 131a adjacent the edge of the opening 127h. That is, the edge portion of the conductive layer 133 may cover one point of the upper surface 131a. From this, it can be seen that the conductive layers 133 do not cover at least a part of the upper surface 131a other than the openings 127h. In addition, since the openings 127h can basically be regarded as the light emitting areas A10, the conductive layers 133 also do not cover at least a part of the upper surface 131a outside the light emitting areas A10. Therefore, the conductive layer 133 shown in FIG. 1 is for illustration only, and does not limit that the conductive layer 133 cannot cover the upper surface 131a.

Since the mixed layer 131 and the conductive layer 133 can be made of metal materials, both the mixed layer 131 and the conductive layer 133 can include the first metal material, wherein the mixed layer 131 further includes the second metal material. The first metal material may be the main material of the conductive layer 133 , that is, the conductive layer 133 may be mainly made of the first metal material. In this embodiment, the volume percentage of the second metal material in the mixed layer 131 may be less than about 10%, so the mixed layer 131 can be substantially regarded as the conductive layer 133 doped with the second metal material. However, in other embodiments, the volume percentage of the second metal material in the mixed layer 131 It can also exceed 10%, so the above volume percentage is not limited to less than 10%.

The surface energy of the second metal material is smaller than that of the first metal material, so the surface energy of the mixed layer 131 may be smaller than that of the conductive layer 133, and the second metal material can repair the surface defects of the mixed layer 131, so that the mixed layer 131 can be repaired. 131 has a flat upper surface 131a, wherein the root mean square roughness (Root Mean Square Roughness, RMS Roughness) of the upper surface 131a may be between 0 nm and 2 nm. In this way, even if the mixed layer 131 has a thin thickness T12 , the mixed layer 131 with the flat upper surface 131 a still has a lower resistance value to help increase the current input to the electroluminescent layer 128 , thereby improving the electroluminescent layer 128 luminous efficiency.

The lowest unoccupied molecular orbital (LUMO) of the second metal material may be between the lowest unoccupied molecular orbital of both the electron transport layer 128a and the first metal material, so the lowest unoccupied molecular orbital of the mixed layer 131 is also May be between the lowest unoccupied molecular orbitals of both conductive layer 133 and electron transport layer 128a. Therefore, the energy level of the mixed layer 131 is between the energy level of the conductive layer 133 and the energy level of the electron transport layer 128a. When the electrons of the conductive layer 133 are transported to the electron transport layer 128 a, the electrons first transition from the energy level of the conductive layer 133 to the energy level of the mixed layer 131 . After that, electrons transition from the energy level of the mixed layer 131 to the electron transport layer 128a. In this way, it is helpful to inject electrons into the electroluminescent layer 128 , thereby improving the luminous efficiency of the electroluminescent layer 128 .

In addition, the surface energy of the second metal material is smaller than that of the first metal material, and the lowest unoccupied molecular orbital of the second metal material is between the electrical Under conditions between the lowest unoccupied molecular orbitals of the sub-transport layer 128a and the first metal material, the first metal material may be silver, and the second metal material may be magnesium, aluminum, and ytterbium. However, the first and second metal materials can also be other metal materials, and are not limited to the aforementioned metal materials.

FIG. 2 is a schematic cross-sectional view of a display panel according to another embodiment of the present invention. Please refer to FIG. 2 , the embodiment shown in FIG. 2 is similar to the previous embodiment, and the display panel 200 shown in FIG. 2 has the same function as the display panel 100 shown in FIG. 1 , wherein the display panels 100 and 200 are both It includes the same elements: the substrate 110 and the pixel array layer 120 . The only difference between the display panels 100 and 200 is that the cathode 230 included in the display panel 200 is different from the cathode 130 in the foregoing embodiments. The above differences are mainly described below, and the similarities between the two will not be repeated in principle.

In the display panel 200 , the cathode 230 includes a mixed layer 231 and a plurality of conductive layers 233 , wherein the material of the mixed layer 231 can be the same as the material of the mixed layer 131 , and the material of the conductive layer 233 can be the same as the material of the conductive layer 133 constituent material. In other words, the mixed layer 231 and each conductive layer 233 both include the aforementioned first metal material, and the mixed layer 231 further includes the aforementioned second metal material, wherein the volume percentage of the second metal material in the mixed layer 231 can also be about 10 %the following.

The mixed layer 231 and the conductive layers 233 are all disposed on the pixel array layer 120 , wherein the mixed layer 231 is distributed in the non-light-emitting area A11 but not distributed in the light-emitting area A10 . For example, the mixed layer 231 is disposed on the pixel definition layer 127 and is located on the surface of the pixel definition layer 127 outside the opening 127h, but not distributed in the opening 127h, as shown in FIG. 2 . Therefore, mixed The shape of the layer 231 may be mesh. The conductive layers 233 are respectively distributed in the light emitting regions A10, for example, in the openings 127h.

The conductive layers 233 overlap with the electroluminescent layers 128 respectively, and are electrically connected to the mixed layer 231 and the electroluminescent layers 128 , so that the cathode 230 is electrically connected to the electroluminescent layers 128 . The thickness T21 of each conductive layer 233 is greater than the thickness T22 of the mixed layer 231 . Therefore, the thickness of the cathode 230 in the light-emitting region A10 (ie, the thickness T21 ) is also greater than the thickness of the cathode 230 in the non-light-emitting region A11 (ie, the thickness T22 ). Furthermore, the range of the thickness T21 may be equal to the range of the aforementioned thickness T11 , and the range of the thickness T22 may be equal to the aforementioned range of the thickness T12 .

It is particularly mentioned that the formation methods of the conductive layers 233 and 133 can be the same, and the formation methods of the mixed layers 231 and 131 can be the same. That is, the conductive layer 233 and the mixed layer 231 can be formed by vapor deposition and photolithography, so the shape of these conductive layers 233 can be designed by a photomask. The above-mentioned mask can design the conductive layer 233 to have a larger width, so that the width of each conductive layer 233 can be larger than the diameter of the opening 127h, so that the conductive layer 233 can cover a part of the mixed layer 231 adjacent to the edge of the opening 127h, but Other parts of the upper surface of the mixed layer 231 other than the opening 127h (ie, the light emitting area A10 ) are not covered, as shown in FIG. 2 . In this way, each conductive layer 233 can be in contact with the mixed layer 231 to ensure that the conductive layers 233 are electrically connected to the mixed layer 231 , thereby avoiding disconnection or poor contact between the conductive layer 233 and the mixed layer 231 .

3 is a schematic cross-sectional view of a display panel according to another embodiment of the present invention. Please refer to FIG. 3, the embodiment shown in FIG. 3 and the embodiment shown in FIG. 1 Similarly, the display panel 300 in FIG. 3 has the same function as the display panel 100 in FIG. 1 , and includes the same elements: the substrate 110 and the pixel array layer 120 . The differences between the display panels 300 and 100 are mainly described below, and the similarities between the two will not be repeated in principle.

Different from the display panel 100 in the foregoing embodiment, the display panel 300 includes a cathode 330 , and the cathode 330 includes a buffer layer 332 and a conductive layer 333 , wherein the conductive layer 333 and the buffer layer 332 are both disposed on the pixel array layer 120 . The buffer layers 332 are distributed in the non-light-emitting regions A11, but not distributed in the light-emitting regions A10. The conductive layers 333 are distributed in the light-emitting regions A10 and the non-light-emitting regions A11 and cover the buffer layer 332 .

Taking FIG. 3 as an example, both the conductive layer 333 and the buffer layer 332 are disposed on the pixel definition layer 127, wherein the buffer layer 332 is distributed on the surface of the pixel definition layer 127 outside the opening 127h, but not distributed in the opening 127h, so the buffer layer 332 is distributed on the surface of the pixel definition layer 127 outside the opening 127h. The shape of layer 332 may be mesh. The conductive layer 333 comprehensively covers the pixel definition layer 127 and the buffer layer 332, and further covers the sidewalls in the openings 127h, so the conductive layer 333 is distributed in the light-emitting area A10 and the non-light-emitting area A11. In addition, the conductive layer 333 has a non-uniform thickness.

From FIG. 3 , the thickness T33a of the conductive layer 333 in the light-emitting area A10 is significantly larger than the thickness T33b of the conductive layer 333 in the non-light-emitting area A11. The buffer layer 332 may have a relatively thin thickness T32, which may be less than or equal to 1 nm. Since the thickness T32 of the buffer layer 332 is relatively thin, the thickness of the cathode 330 in the light-emitting region A10 (equal to the thickness T33a) is still greater than the thickness of the cathode 330 in the non-light-emitting region A11 (equal to the thickness T32 plus the thickness T33b). The range of thickness T33a may be equal to the range of thickness T11 The thickness of the cathode 330 in the non-light-emitting area A11 (equal to the thickness T32 plus the thickness T33b) can be substantially equal to the range of the thickness T12.

The constituent material of the conductive layer 333 may be the same as the constituent material of the conductive layer 133 , so the conductive layer 333 may include the aforementioned first metal material. The surface energy of the buffer layer 332 may be smaller than that of the conductive layer 333 . For example, the buffer layer 332 can be made of the aforementioned second metal material, wherein both the conductive layer 333 and the buffer layer 332 can be formed by evaporation. Since the surface energy of the buffer layer 332 may be smaller than that of the conductive layer 333, during the process of forming the conductive layer 333 on the buffer layer 332 (eg, evaporation), the conductive layer 333 can be easily dispersed on the buffer layer 332 to The conductive layer 333 can form a flat surface, and its root mean square roughness (RMS Roughness) can be between 0 nm and 2 nm.

In this way, even if the conductive layer 333 has a thin thickness T33b, the conductive layer 333 with a flat surface still has a lower resistance value to help increase the current input to the electroluminescent layer 128 . In addition, the lowest unoccupied molecular orbital region of the buffer layer 332 may be between the lowest unoccupied molecular orbital regions of the electron transport layer 128 a and the conductive layer 333 , so the energy level of the buffer layer 332 will be between the energy level of the conductive layer 333 The level is between the energy level of the electron transport layer 128 a , so as to facilitate electron injection into the electroluminescent layer 128 and improve the luminous efficiency of the electroluminescent layer 128 .

In this embodiment, the conductive layer 333 may be formed by photolithography, and may be formed by a secondary process. Specifically, the conductive layer 333 may include a first conductive layer 333a and a second conductive layer 333b, wherein the first conductive layer 333a is first formed in the non-light-emitting area A11. After that, the second time The conductive layer 333b is formed in the light emitting area A10.

In the process of forming the second conductive layer 333b, evaporation and photolithography may be performed successively. The photomask used in photolithography can design the second conductive layer 333b to have a larger width, so that the width of the second conductive layer 333 can be larger than the diameter of the opening 127h. In this way, the second conductive layer 333b can cover a portion of the first conductive layer 333a adjacent to the edge of the opening 127h to ensure that the second conductive layer 333b is electrically connected to the first conductive layer 333a. Therefore, the second conductive layer 333b forms a raised portion at the edge of the opening 127h, as shown in FIG. 3 .

4 is a schematic cross-sectional view of a display panel according to another embodiment of the present invention. Please refer to FIG. 4 , the display panel 400 shown in FIG. 4 is similar to the display panel 200 shown in FIG. 2 , and both have the same functions, and include the substrate 110 and the pixel array layer 120 . The following mainly describes the difference between the display panels 200 and 400 , that is, the cathode 430 included in the display panel 400 . In principle, the similarities between the display panels 200 and 400 will not be repeated.

Different from the cathode 230 in FIG. 2 , the cathode 430 in FIG. 4 not only includes the mixed layer 231 and the plurality of conductive layers 233 , but also includes the buffer layer 332 . The mixed layer 231 , the buffer layer 332 and the conductive layers 233 are all disposed on the pixel array layer 120 , wherein the mixed layer 231 and the buffer layer 332 are all disposed on the pixel definition layer 127 and distributed in the non-emitting areas A11 . The mixed layer 231 covers the buffer layer 332, and the buffer layer 332 may be sandwiched between the mixed layer 231 and the pixel definition layer 127, as shown in FIG. 4 .

5 is a schematic cross-sectional view of a display panel according to another embodiment of the present invention. Please refer to FIG. 5 , the display panel 500 shown in FIG. 5 is the same as the display panel 500 shown in FIG. 1 . The display panels 100 are similar, and both have the same functions, so the similarities between the display panels 500 and 100 will not be repeated in principle. The only difference between the display panels 500 and 100 is that the cathode 530 of the display panel 500 not only includes the mixed layer 131 and the conductive layer 133 , but also includes the buffer layer 332 . The buffer layer 332 is only distributed in the non-light-emitting area A11, and the mixed layer 131 not only covers the pixel definition layer 127, but also covers the buffer layer 332, so that the buffer layer 332 is sandwiched between the pixel definition layer 127 and the mixed layer 131 .

To sum up, in at least one embodiment of the present invention, the display panel has cathodes with non-uniform thicknesses, wherein the thickness of the cathodes in the light-emitting region is greater than the thickness of the cathodes in the non-light-emitting regions. In other words, a portion of the cathode located in the light-emitting region has a thicker thickness, while a portion of the cathode located in the non-light-emitting region has a thinner thickness. Therefore, the cathode in the non-light-emitting area is easily penetrated by light, so that the image-sensing element disposed under the non-light-emitting area can smoothly receive the light from the outside from the display panel for photographing or photographing. The cathode in the light-emitting region has a lower resistance value to help increase the current input to the electroluminescent layer, thereby improving the light-emitting efficiency of the electroluminescent layer.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the appended patent application.

100, 200, 300, 400, 500: Display panel

110: Substrate

120: pixel array layer

121, 122, 123, 124: insulating layer

124h: Contact window

125: Anode

126: Control elements

127: Pixel Definition Layer

127h: Opening

128: Electroluminescent layer

128a: electron transport layer

130, 230, 330, 430, 530: Cathode

131, 231: Hybrid layer

131a: upper surface

133, 233, 333: Conductive layer

332: Buffer Layer

A10: Light-emitting area

A11: Non-emitting area

C26: Channel Layer

D26: drain

G26: Gate

S26: Source

L1: light

T11, T12, T21, T22, T32, T33a, T33b: Thickness

FIG. 1 is a schematic cross-sectional view of a display panel according to at least one embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a display panel according to another embodiment of the present invention. 3 is a schematic cross-sectional view of a display panel according to another embodiment of the present invention. 4 is a schematic cross-sectional view of a display panel according to another embodiment of the present invention. 5 is a schematic cross-sectional view of a display panel according to another embodiment of the present invention.

100: Display panel

110: Substrate

120: pixel array layer

121, 122, 123, 124: insulating layer

124h: Contact window

125: Anode

126: Control elements

127: Pixel Definition Layer

127h: Opening

128: Electroluminescent layer

128a: electron transport layer

130: Cathode

131: Blend Layer

131a: upper surface

133: Conductive layer

A10: Light-emitting area

A11: Non-emitting area

C26: Channel Layer

D26: drain

G26: Gate

S26: Source

L1: light

T11, T12: Thickness

Claims (16)

A display panel, comprising: a substrate; a pixel array layer disposed on the substrate and having a plurality of light-emitting regions and a plurality of non-light-emitting regions, wherein the pixel array layer includes a plurality of electroluminescent layers, and the The electroluminescent layers are respectively located in the light-emitting regions; and a cathode is disposed on the pixel array layer and electrically connected to the electroluminescent layers, wherein the thickness of the cathode in the light-emitting region is greater than that of the cathode in the non-electroluminescent region The thickness of the light-emitting region, and the difference between the thickness of the cathode in the light-emitting region and the thickness of the cathode in the non-light-emitting region is between 1 nm and 22 nm, wherein the cathode comprises: a mixed layer disposed on the pixel array layer, and has an upper surface; a plurality of conductive layers are arranged on the mixed layer and distributed in the light-emitting regions, wherein the conductive layers respectively overlap with the electroluminescent layers and do not cover the at least a portion of the upper surface outside the light emitting area. The display panel of claim 1, wherein the thickness of the cathode in the light-emitting region is between 16 nm and 30 nm. The display panel according to claim 1 or 2, wherein the thickness of the cathode in the non-light-emitting region is between 8 nm and 15 nm. The display panel of claim 1, wherein the mixed layer is distributed in the light-emitting regions and the non-light-emitting regions. The display panel of claim 4, wherein the mixed layer and the conductive layer both comprise a first metal material, and the mixed layer further comprises a second metal material, wherein the surface energy of the second metal material is smaller than that of the first metal material The surface energy of a metal material. The display panel of claim 5, wherein the volume percentage of the second metal material in the mixed layer is about 10% or less. The display panel of claim 4, wherein each of the electroluminescent layers includes an electron transport layer, the mixed layer and the conductive layer both include a first metal material, and the mixed layer further includes a second metal material, Wherein the lowest unoccupied molecular orbital of the second metal material is between the lowest unoccupied molecular orbital of both the electron transport layer and the first metal material. The display panel of claim 4, wherein the cathode further comprises a buffer layer, the buffer layer is disposed on the pixel array layer and distributed in the non-light-emitting regions, wherein the mixed layer covers the buffer layer. The display panel as claimed in claim 1, wherein the mixed layer is distributed in the non-light-emitting regions but not in the light-emitting regions, and the conductive layers are electrically connected to the mixed layer, wherein the thickness of each conductive layer is greater than the thickness of the mixed layer. The display panel of claim 9, wherein the mixed layer and each of the conductive layers comprise a first metal material, and the mixed layer further comprises a second metal material, wherein the surface energy of the second metal material is smaller than the surface energy of the second metal material Surface energy of the first metallic material. The display panel of claim 10, wherein the volume percentage of the second metal material in the mixed layer is about 10% or less. The display panel of claim 9, wherein each of the electroluminescent layers includes an electron transport layer, the mixed layer and each of the conductive layers both include a first metal material, and the mixed layer further includes a second metal material , wherein the lowest unoccupied molecular orbital of the second metal material is between the lowest unoccupied molecular orbital of both the electron transport layer and the first metal material. The display panel of claim 9, wherein the cathode further comprises a buffer layer, the buffer layer is disposed on the pixel array layer and distributed in the non-light-emitting regions, wherein the mixed layer covers the buffer layer. A display panel, comprising: a substrate; a pixel array layer disposed on the substrate and having a plurality of light-emitting regions and a plurality of non-light-emitting regions, wherein the pixel array layer includes a plurality of electroluminescent layers, and the The electroluminescent layers are respectively located in the light-emitting regions; and a cathode is disposed on the pixel array layer and electrically connected to the electroluminescent The light-emitting layer, wherein the thickness of the cathode in the light-emitting region is greater than the thickness of the cathode in the non-light-emitting region, and the thickness of the cathode in the light-emitting region differs from the thickness of the cathode in the non-light-emitting region by 1 nm to 22 nm wherein the cathode comprises: a buffer layer disposed on the pixel array layer and distributed in the non-light emitting regions but not distributed in the light emitting regions; and a conductive layer disposed on the pixel array layer on the light-emitting regions and the non-light-emitting regions, wherein the conductive layer covers the buffer layer, and the thickness of the conductive layer in the light-emitting region is greater than the thickness of the conductive layer in the non-light-emitting region. The display panel of claim 14, wherein the surface energy of the buffer layer is smaller than the surface energy of the conductive layer. The display panel of claim 14, wherein each of the electroluminescent layers includes an electron transport layer, and a lowest unoccupied molecular orbital of the buffer layer is between the lowest unoccupied molecules of both the electron transport layer and the conductive layer between orbits.

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