TWI748758B - Circuit board having asymmetrical structure - Google Patents

Abstract

A circuit board having an asymmetrical structure is provided. The circuit board includes a core substrate structure and a build-up structure. The core substrate structure includes a substrate, an inner patterned circuit, and a bottom patterned circuit. The substrate includes a first board surface and a second board surface opposite to the first board surface. The inner patterned circuit is formed on the first board surface, and the bottom patterned circuit is formed on the second surface. The build-up structure includes a dielectric layer and a top patterned circuit. The dielectric layer is formed on the first board surface, and the top patterned circuit is formed on a side surface of the dielectric layer. The core substrate has a first thickness, the dielectric layer has a second thickness, and the fist thickness is greater than the second thickness to form an asymmetrical structure.

Description

Circuit board with asymmetric structure

The invention relates to a circuit board, in particular to a circuit board with an asymmetric structure.

Generally speaking, the number of circuit layers of existing circuit boards is usually designed to be an even number of layers. For example, the number of circuit layers in an existing circuit board is usually four, six, or eight. However, the existing circuit boards have the problems of high manufacturing cost and the overall board thickness cannot be effectively reduced.

Therefore, how to reduce the manufacturing cost and overall thickness of the circuit board by improving the structural design to provide a circuit board with an asymmetric structure to overcome the above-mentioned shortcomings has become one of the important issues to be solved by this business. .

The technical problem to be solved by the present invention is to provide a circuit board with an asymmetric structure in view of the shortcomings of the prior art. Compared with the existing circuit board, the circuit board provided by the present invention can have a lower manufacturing cost and a smaller size. Overall board thickness.

In order to solve the above technical problems, one of the technical solutions adopted by the present invention is to provide a circuit board with an asymmetric structure, which includes: a core substrate structure, which includes: a substrate with a first substrate on the opposite side Surface and a second surface; an inner layer patterned circuit formed on the first surface; and a bottom surface patterned circuit formed on the second surface; and a circuit build-up structure including : A dielectric layer formed on the first surface of the substrate and covering the inner patterned circuit, and the surface of the dielectric layer on the side away from the substrate is defined as a A third surface; and a top surface patterned circuit formed on the third surface; wherein the substrate has a first thickness, the dielectric layer has a second thickness, and the first The thickness is greater than the second thickness to form an asymmetric structure.

One of the beneficial effects of the present invention is that the circuit board with an asymmetric structure provided by the present invention can pass "the circuit board with an asymmetric structure includes a core substrate structure and a circuit build-up structure" and "the The substrate has a first thickness, the dielectric layer has a second thickness, and the first thickness is greater than the second thickness to form an asymmetric structure." The symmetrical structure of the circuit board can have relatively low manufacturing cost and overall board thickness.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings about the present invention. However, the provided drawings are only for reference and description, and are not used to limit the present invention.

The following is a specific embodiment to illustrate the implementation of the "circuit board with asymmetric structure" disclosed in the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be based on different viewpoints and applications, and various modifications and changes can be made without departing from the concept of the present invention. In addition, the drawings of the present invention are merely schematic illustrations, and are not drawn according to actual size, and are stated in advance. The following embodiments will further describe the related technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention.

It should be understood that although terms such as “first”, “second”, and “third” may be used herein to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are mainly used to distinguish one element from another, or one signal from another signal. In addition, the term "or" used in this document may include any one or a combination of more of the associated listed items depending on the actual situation.

[Circuit board with asymmetric structure]

Refer to FIG. 1, which is a schematic cross-sectional view of a circuit board according to an embodiment of the present invention. The present invention provides a circuit board 100 with an asymmetric structure (hereinafter referred to as the circuit board 100 for short). The circuit board 100 includes a core substrate structure 1 and a circuit build-up structure 2. The core substrate structure 1 includes a substrate 11, an inner patterned circuit 12, and a bottom patterned circuit 13. The substrate 11 has a first surface 111 and a second surface 112 on opposite sides, the inner patterned circuit 12 is formed on the first surface 111, and the bottom patterned circuit 13 is formed On the second surface 112. In addition, the second surface 112 of the core substrate structure 1 may have no other line build-up structure formed on it, but the present invention is not limited to this.

The circuit build-up structure 2 includes a dielectric layer 21 and a patterned circuit 22 on the top surface. The dielectric layer 21 is formed on the first surface 111 of the substrate 11 and covers the inner patterned circuit 12. The side surface of the dielectric layer 21 away from the substrate 11 is defined as a third surface 211, and the top surface patterned circuit 22 is formed on the third surface 211.

The substrate 11 has a first thickness T1, the dielectric layer 21 has a second thickness T2, and the first thickness T1 is greater than the second thickness T2 to form an asymmetric structure. The first thickness T1 of the substrate may be 1.2 to 2.0 times the second thickness T2 of the dielectric layer 21. Specifically, the first thickness T1 of the substrate 11 may be between 50 μm and 80 μm, and the second thickness T2 of the dielectric layer 21 may be between 25 μm and 55 μm. However, the present invention is not limited to this. In addition, the material of the dielectric layer 21 can be, for example, epoxy resin or epoxy resin containing glass fiber, but the present invention is not limited thereto.

It should be noted that the inner layer patterned circuit 12, the bottom surface patterned circuit 13, and the top surface patterned circuit 22 may all include a plurality of metal conductors (not shown in the figure), and a plurality of The metal conductors are arranged spaced apart from each other. The size of the plurality of metal conductors and the distance between any two adjacent metal conductors can be changed according to requirements. That is, the size and the distance are not limited to be the same or different. Each of the metal conductors can be a metal pad or a metal circuit (pattern), but the present invention is not limited thereto.

In addition, in this embodiment, the total number of circuit layers included in the circuit board 100 is three (that is, the inner patterned circuit 12, the bottom patterned circuit 13, and the top patterned circuit The sum of the number of lines 22), therefore, compared to the existing circuit board with a symmetrical structure, the circuit board 100 in this embodiment can have a lower overall board thickness and a relatively low manufacturing cost.

The circuit board 100 may further include a plated-through hole structure 3 (PTH), and the plated-through hole structure 3 is formed through the core substrate structure 1 and the circuit build-up structure 2, and The inner layer patterned circuit 12, the bottom surface patterned circuit 13, and the top surface patterned circuit 22 are electrically connected to each other through the plated through-hole structure 3. Specifically, the plated through hole structure 3 includes a through hole 31 and a metal conductive layer 32 plated on the inner wall of the through hole 31. The electroplated through-hole structure 3 is electrically connected to the inner layer patterned circuit 12, the bottom surface patterned circuit 13, and the top surface patterned circuit 22 through the metal conductive layer 32. conductor.

Please refer to FIG. 2, which is a schematic cross-sectional view of a circuit board including a bottom surface stress buffer structure according to an embodiment of the present invention. Since the first thickness T1 of the substrate 11 is greater than the second thickness T2 of the dielectric layer 21, the circuit board 100 will correspondingly generate a stress, which makes the circuit board 100 It is bent in the direction of the core substrate structure 1. In order to avoid the bending of the circuit board 100 caused by the stress, the core substrate structure 1 may also have a bottom surface stress buffer structure 14.

In detail, the bottom surface stress buffer structure 14 is formed on the second surface 112 of the substrate 11, and the bottom surface stress buffer structure 14 is formed around the bottom surface patterned circuit 13. The bottom surface stress buffer structure 14 is configured on the core substrate structure 1 to generate the stress resisting the bending of the circuit board 100 toward the core substrate structure 1.

Please refer to FIG. 2 and FIG. 5. FIG. 5 is an enlarged schematic diagram of the bottom surface stress buffer structure according to an embodiment of the present invention. The bottom stress buffer structure 14 includes a plurality of bottom stress buffer bumps 141, and the plurality of bottom stress buffer bumps 141 are spaced apart from each other and arranged in a staggered or matrix arrangement. In this embodiment, each bottom surface stress buffer bump 141 is a non-circular geometric figure, and each bottom surface stress buffer bump 141 and its adjacent bottom surface stress buffer bump 141 form a fixed The gap 141a (that is, the distance between any two adjacent bottom surface stress buffer bumps 141 is fixed). Each of the bottom surface stress buffer bumps 141 may be, for example, a metal (for example, copper) formed on the second surface 112 of the substrate 11 by electroplating, but the present invention is not limited thereto. In addition, at least part of the second surface 112 of the substrate 11 is exposed to the fixed gap 141a.

As shown in FIGS. 2 and 5, the fixed gap 141a has a first width W1, each of the bottom stress buffer bumps has a second width W2, and the second width W2 is greater than the first width W1 , And the second width is 5.0 to 15 times the first width W1. The first width W1 of the fixed gap 141a is between 0.1 mm and 0.3 mm, and the second width W2 of each bottom surface stress buffering bump 141 is between 1.0 mm and 1.8 mm And each of the bottom stress buffer bumps 141 has a height H1 ranging from 20 microns to 40 microns, but the present invention is not limited to this.

Furthermore, each of the bottom surface stress buffer bumps 141 may be a pentagonal or hexagonal geometric figure, a plurality of bottom surface stress buffer bumps 141 are spaced apart from each other and arranged in a staggered arrangement, and each bottom surface The stress buffer bump 141 is surrounded by at least five other adjacent bottom stress buffer bumps 141, but the present invention is not limited to this. In this embodiment, each of the bottom stress buffer bumps 141 is hexagonal, and each bottom stress buffer bump 141 is surrounded by six adjacent bottom stress buffer bumps 141, but The present invention is not limited to this.

Please refer to FIG. 3, FIG. 4, and FIG. 6. FIG. 3 is a schematic cross-sectional view of a circuit board including a bottom surface stress buffer structure and a top surface stress buffer structure according to an embodiment of the present invention. FIG. 4 is an embodiment of the present invention. The schematic diagram of the circuit board, FIG. 6 is an enlarged schematic diagram of the top surface stress buffer structure of the embodiment of the present invention. In order to better avoid bending of the circuit board 100, the circuit build-up structure 2 of the circuit board 100 may further include a top surface stress buffer structure 23. The top stress buffer structure 23 is formed on the third surface 211 of the dielectric layer 21, and the top stress buffer structure 23 surrounds the top surface patterned circuit 22. form. The top surface stress buffer structure 23 is disposed on the circuit build-up structure 2 to generate a stress resisting bending of the circuit board 100 toward the circuit build-up structure 2.

Specifically, the top stress buffer structure 23 includes a plurality of top stress buffer bumps 231, and the plurality of top stress buffer bumps 231 are spaced apart from each other and arranged in a staggered or matrix arrangement. In this embodiment, each of the top surface stress buffer bumps 231 is a non-circular geometric figure, and each of the top surface stress buffer bumps 231 and its adjacent top surface stress buffer bumps 231 are between A fixed gap 231a is formed (that is, the distance between any two adjacent top surface stress buffer bumps 2311 is fixed). In addition, at least part of the third surface 211 of the dielectric layer 21 is exposed to the fixed gap 231a.

As shown in FIGS. 3 and 6, the fixed gap 231a has a third width W3, and each of the top stress buffer bumps 231 has a fourth width W4, and the fourth width is greater than the third width. W3, and the fourth width W4 is 5.0 to 15 times the third width. In this embodiment, the third width W3 of the fixed gap 231a is between 0.1 mm and 0.3 mm, and the fourth width W4 of each of the top surface stress buffer bumps 231 is between It is between 1.0 mm and 1.8 mm, and each of the top surface stress buffer bumps 231 has a height H2 between 20 μm and 40 μm, but the present invention is not limited to this.

Furthermore, each of the top surface stress buffer bumps 231 may be a pentagonal or hexagonal geometric figure, and a plurality of the top surface stress buffer bumps 231 are spaced apart from each other and arranged in a staggered arrangement, and each of the The top stress buffer bump 231 is surrounded by at least five other adjacent top stress buffer bumps 231, but the present invention is not limited to this. In this embodiment, each of the top surface stress buffer bumps 231 is hexagonal, and each of the top surface stress buffer bumps 231 is held by six adjacent top surface stress buffer bumps 231. Surrounded, but the present invention is not limited to this.

It is worth mentioning that the bottom surface stress buffer structure 14 is not electrically connected to the bottom surface patterned circuit 13, nor is it electrically connected to the plated through-hole structure 3, and the top surface stress buffer structure 23 is not electrically connected. It is electrically connected to the patterned circuit 22 on the top surface, but not electrically connected to the plated through-hole structure 3. The bottom surface stress buffer structure 14 can be matched with the top surface stress buffer structure 23 so that the circuit board 100 has a warpage of less than 0.75%.

In addition, as shown in FIG. 4, the circuit board 100 defines at least one critical area A and a non-critical area B. The critical area A is located in the middle of the circuit board 100 and the non-critical area B Surround the critical area A. In the core substrate structure 1, the inner layer patterned circuit 12 and the bottom surface patterned circuit 13 are both located in the critical area A, and the bottom stress buffer structure 14 is located in the non-critical area B . In the circuit build-up structure 2, the top surface patterned circuit 22 is located in the critical area A, and the top stress buffer structure 23 is located in the non-critical area B.

To put it another way, the key area A can be regarded as an area where any circuit is formed on the circuit board 100 (such as the inner layer patterned circuit 12, the bottom surface patterned circuit 13, or the top surface patterned circuit 22) , And the non-critical area B can be regarded as an area where no circuit is formed on the circuit board 100. When the circuit board 100 is finally formed, the critical area A of the circuit board 100 will be reserved, and the non-critical area B of the circuit board 100 will be removed.

The plurality of bottom stress buffer bumps 141 of the bottom stress buffer structure 14 have a coverage of between 10% and 15% on the non-critical area B of the second surface 112 of the substrate 11, and The plurality of top stress buffer bumps 231 of the top stress buffer structure 23 have between 10% and 15% in the non-critical area B of the third surface 211 of the dielectric layer 21 The coverage rate of the bottom surface stress buffer structure 14 and the top surface stress buffer structure 23 can provide an effective stress buffer effect and reduce the warpage of the circuit board.

[Method for manufacturing circuit board with asymmetric structure]

Please refer to FIG. 7 to FIG. 11. FIG. 7 is a schematic diagram of the pre-steps of the method of manufacturing a circuit board according to an embodiment of the present invention, and FIG. 8 is a schematic diagram of the build-up steps of the method of manufacturing a circuit board according to an embodiment of the present invention. 9 is a schematic diagram of the drilling step of the circuit board manufacturing method of the embodiment of the invention, FIG. 10 is a schematic diagram of the electroplating step of the circuit board manufacturing method of the embodiment of the invention, and FIG. 11 is a diagram of the circuit board of the embodiment of the invention A schematic diagram of the outer layer patterning step of the manufacturing method.

This embodiment also discloses a method for manufacturing a circuit board with an asymmetric structure. The manufacturing method of the circuit board with an asymmetric structure includes a pre-step, a build-up step, a glue removal step, a drilling step, an electroplating step, and an outer layer patterning step. However, the circuit board with the asymmetric structure of this embodiment may be manufactured by the above-mentioned manufacturing method, but the present invention is not limited to this. Furthermore, the present invention is not limited to the content and sequence of the above-mentioned steps when implementing the above-mentioned method for manufacturing the circuit board with an asymmetric structure.

In the pre-step, a substrate 11 and an inner patterned circuit 12 are provided. The substrate 11 has a first surface 111 and a second surface 112 on opposite sides, and the inner patterned circuit 12 is formed on the first surface 111.

In the layer build-up step, a dielectric layer 21 is formed on the first surface 111 of the substrate 11 and the dielectric layer 21 covers the inner patterned circuit 12. The surface of the dielectric layer 21 away from the substrate 11 is defined as a third surface 211.

In the de-glueing step, the second surface 112 of the substrate 11 is de-glueed. Since there is no other circuit build-up structure formed on the second surface 112 of the substrate 11, after the build-up step, the second surface 112 may be generated during the build-up step. Dust remains, so the second surface 112 needs to be degummed to prevent the dust from negatively affecting the subsequent manufacturing process. In addition, in the degumming step, the second surface 112 of the substrate 11 can be degummed by a sludge removal liquid, ultraviolet rays or plasma.

In the drilling step, the dielectric layer 21 and the substrate 11 are jointly drilled to form a through hole 31, and the through hole 31 penetrates the substrate 11 and the dielectric layer 21 .

In the electroplating step, the dielectric layer 21 and the substrate 11 are jointly electroplated to form a metal conductive layer 32 on the inner sidewall of the through hole 31. The through hole 31 and the metal conductive layer 32 are collectively defined as a plated through hole structure 3.

In the outer layer patterning step, a top surface patterned circuit 13 and a top surface stress buffer structure 23 are formed on the third surface 211 of the dielectric layer 21, and on the substrate 11 The second surface 112 forms a bottom surface patterned circuit 13 and a bottom surface stress buffer structure 14 (as shown in FIG. 11 ). The substrate 11, the inner layer patterned circuit 12, and the bottom surface patterned circuit 13 are collectively defined as a core substrate structure 1, and the dielectric layer 21 and the top surface patterned circuit 22 collectively define For a line build-up structure 2.

It should be noted that, in the step of patterning the outer layer, the third surface 211 of the dielectric layer 21 may not have the top surface stress buffer structure 23 formed, and only on all surfaces of the substrate 11 The second surface 112 forms the bottom stress buffer structure 14 (as shown in FIG. 2), or the circuit board 100 may not include the top stress buffer structure 23 and the bottom stress buffer structure 14 ( As shown in Figure 1), but the present invention is not limited to this.

[Beneficial Effects of Embodiments of the Invention]

One of the beneficial effects of the present invention is that the circuit board with an asymmetric structure provided by the present invention can pass "the circuit board with an asymmetric structure includes a core substrate structure and a circuit build-up structure" and "the The substrate has a first thickness, the dielectric layer has a second thickness, and the first thickness is greater than the second thickness to form an asymmetric structure." The symmetrical structure of the circuit board can have relatively low manufacturing cost and overall board thickness.

Furthermore, the circuit board with an asymmetric structure provided by the present invention can pass "the core substrate structure has the bottom surface stress buffer structure, and the bottom surface stress buffer structure is formed on the substrate "On the second surface" and "the circuit build-up structure package has the top surface stress buffer structure, and the bottom surface stress buffer structure is formed on the third surface of the dielectric layer" technical solutions, In order to effectively reduce the warpage of the circuit board.

The content disclosed above is only a preferred and feasible embodiment of the present invention, and does not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the description and schematic content of the present invention are included in the application of the present invention. Within the scope of the patent.

100: circuit board

1: Core substrate structure

11: substrate

111: first surface

112: second surface

12: inner patterned circuit

13: Patterned circuit on the bottom surface

14: Bottom stress buffer structure

141: Bottom stress buffer bump

141a: fixed gap

2: Line build-up structure

21: Dielectric layer

211: Third Surface

22: Patterned circuit on the top surface

23: Top surface stress buffer structure

231: Top stress buffer bump

231a: fixed gap

3: Plated through hole structure

31: Through hole

32: Metal conductive layer

A: Key area

B: Non-critical area

H1, H2: height

T1: first thickness

T2: second thickness

W1: first width

W2: second width

W3: third width

W4: Fourth width

FIG. 1 is a schematic cross-sectional view of a circuit board according to an embodiment of the present invention.

2 is a schematic cross-sectional view of a circuit board including a bottom surface stress buffer structure according to an embodiment of the present invention.

3 is a schematic cross-sectional view of a circuit board including a bottom surface stress buffer structure and a top surface stress buffer structure according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of a circuit board according to one embodiment of the present invention.

FIG. 5 is an enlarged schematic diagram of the bottom surface stress buffer structure according to an embodiment of the present invention.

FIG. 6 is an enlarged schematic diagram of a top surface stress buffer structure according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of the pre-steps of the manufacturing method of the circuit board according to the embodiment of the present invention.

FIG. 8 is a schematic diagram of the build-up step of the manufacturing method of the circuit board according to the embodiment of the present invention.

FIG. 9 is a schematic diagram of a drilling step of a manufacturing method of a circuit board according to an embodiment of the present invention.

FIG. 10 is a schematic diagram of an electroplating step in a method of manufacturing a circuit board according to an embodiment of the present invention.

FIG. 11 is a schematic diagram of an outer layer patterning step of a method of manufacturing a circuit board according to an embodiment of the present invention.

100: circuit board

1: Core substrate structure

11: substrate

111: first surface

112: second surface

12: inner patterned circuit

13: Patterned circuit on the bottom surface

2: Line build-up structure

21: Dielectric layer

211: Third Surface

22: Patterned circuit on the top surface

3: Plated through hole structure

31: Through hole

32: Metal conductive layer

T1: first thickness

T2: second thickness

Claims (9)

A circuit board with an asymmetric structure, comprising: a core substrate structure, including: a substrate having a first surface and a second surface on opposite sides; and an inner layer patterned circuit formed on all sides On the first surface; a bottom surface patterned circuit formed on the second surface; and a bottom surface stress buffer structure formed on the second surface of the substrate, and the bottom surface stress buffer structure Is formed around the bottom surface patterned circuit; wherein, the bottom surface stress buffer structure is disposed on the core substrate structure to generate a stress that resists bending of the circuit board toward the core substrate structure; And a circuit build-up structure, comprising: a dielectric layer formed on the first surface of the substrate and covering the inner patterned circuit, and the dielectric layer is far away from the One side surface of the substrate is defined as a third surface; and a top surface patterned circuit is formed on the third surface; wherein, the substrate has a first thickness, and the dielectric layer has a A second thickness, and the first thickness is greater than the second thickness to form an asymmetric structure. The circuit board according to claim 1, wherein the first thickness of the substrate is 1.2 to 2.0 times the second thickness of the dielectric layer; wherein the first thickness of the substrate A thickness is between 50 micrometers and 80 micrometers, and the second thickness of the dielectric layer is between 25 micrometers and 55 micrometers; wherein all the substrates of the core substrate structure No other circuit build-up structure is formed on the second surface. The circuit board according to claim 1, further comprising: a plated-through hole structure (plated-through holes, PTH), the plated-through hole structure is formed through the core substrate structure and the circuit build-up structure , And the inner layer is patterned The circuit, the patterned circuit on the bottom surface, and the patterned circuit on the top surface are electrically connected to each other through the plated through-hole structure. The circuit board according to claim 1, wherein the bottom stress buffer structure includes a plurality of bottom stress buffer bumps, and the plurality of bottom stress buffer bumps are spaced apart from each other, and are arranged in a staggered or matrix arrangement. The circuit board according to claim 4, wherein each of the bottom surface stress buffer bumps is a non-circular geometric figure, and each of the bottom surface stress buffer bumps and its adjacent bottom surface stress buffer bumps A fixed gap is formed, and the fixed gap has a first width; wherein each of the bottom stress buffer bumps has a second width, the second width is greater than the first width, and the second The width is 5.0 to 15 times the first width. The circuit board according to claim 5, wherein the first width of the fixed gap is between 0.1 mm and 0.3 mm, and the second width of each of the bottom surface stress buffer bumps is It is between 1.0 mm and 1.8 mm; wherein, each of the bottom stress buffer bumps has a height between 20 μm and 40 μm. The circuit board according to claim 5, wherein each of the bottom surface stress buffer bumps is a pentagonal or hexagonal geometric figure, and a plurality of the bottom surface stress buffer bumps are arranged at intervals and in a staggered arrangement, and Each of the bottom stress buffer bumps is surrounded by at least five other adjacent bottom stress buffer bumps. The circuit board according to claim 1, wherein the circuit build-up structure further comprises: a top surface stress buffer structure formed on the third surface of the dielectric layer, and the top surface The stress buffer structure is formed around the patterned circuit on the top surface; wherein the stress buffer structure on the top surface is configured on the circuit build-up structure to produce A stress that resists bending of the circuit board toward the line build-up structure direction is generated. The circuit board according to claim 8, wherein the circuit board defines a critical area and a non-critical area, the critical area is located in the middle part of the circuit board, and the non-critical area surrounds the critical area. Area; wherein, in the core substrate structure, the inner layer patterned circuit and the bottom surface patterned circuit are located in the critical area, and the bottom stress buffer structure is located in the non-critical area; wherein In the line build-up structure, the top surface patterned line is located in the critical area, and the top surface stress buffer structure is located in the non-critical area.

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