TWI743792B - Vernier mark for semiconductor manufacturing process and lithographic process inspection method using the same - Google Patents

Abstract

A vernier mark for semiconductor manufacturing process includes at least one vernier structure and a plurality of identification symbols formed on or in a semiconductor substrate. The vernier structure includes a plurality of first linear layers extending in X direction and a plurality of second linear layers extending in Y direction, and the first linear layers are intersected with the second linear layers. The length of the center line in the first linear layers is greater than the length of the remaining first linear layers, and the length of the center line in the second linear layer is greater than the length of the remaining second linear layers. The identification symbols are formed on at least one end of each first linear layers and at least one end of each second linear layers to distinguish different first linear layers and different second linear layers in the vernier structure.

Description

Vernier for semiconductor manufacturing process and lithography process detection method using the vernier

The present invention relates to a lithography process inspection technology, and more particularly to a vernier for semiconductor manufacturing process and a lithography process inspection method using the vernier.

With the rapid development of semiconductor process technology, in order to improve the speed and performance of the device, the size of the entire circuit device must be continuously reduced, and the integration degree of the device must be continuously improved. Generally speaking, under the design development of semiconductors that tend to shrink circuit components, the lithography process occupies a pivotal position in the entire manufacturing process.

In order to ensure product yield, at least three inspection sites will be added to the lithography process, and various instruments and manual inspections will be used, such as the use of an optical microscope (OM) for overlapping inspections in the X and Y directions (Overlap Check), Use a scanning electron microscope (SEM tool) to inspect the critical dimension (CD) and perform a visual inspection of the wafer (Visual Check).

However, with the development of semiconductor devices to processes below tens of nanometers, the existing alignment marks used for lithography process detection have been hundreds or thousands of times different from the real device size, which makes it impossible to accurately detect the overlap (OL) deviation. Values such as shift amount affect the product yield. In addition, as the size of semiconductor components shrinks, the CD detection time will also increase significantly, which will affect the sampling rate (Sampling rate).

The invention provides a vernier for a semiconductor manufacturing process, which can cooperate with the development of miniaturization of semiconductor components and improve the accuracy of detection of the lithography manufacturing process.

The present invention also provides a lithography process detection method, which can simultaneously detect OL offset and CD, thereby shortening the detection time and increasing the sampling rate.

A vernier for a semiconductor manufacturing process of the present invention includes at least one vernier structure and a plurality of identification symbols formed on or in the semiconductor substrate. The vernier structure includes a plurality of first linear layers extending in the X direction and a plurality of second linear layers extending in the Y direction, and the first linear layers and the second linear layers are intersected. The length of the center line in the first linear layer is greater than the length of the remaining first linear layers, and the length of the center line in the second linear layer is greater than the length of the remaining second linear layers. The identification symbol is formed on at least one end of each first linear layer and at least one end of each second linear layer to distinguish different first linear layers and different second linear layers in the vernier structure.

In an embodiment of the present invention, the aforementioned vernier structure is formed in a semiconductor substrate, and the first linear layer and the second linear layer are shallow trench isolation structures.

In an embodiment of the present invention, the above-mentioned vernier structure is formed on a semiconductor substrate, and the first linear layer and the second linear layer are polysilicon wires.

In an embodiment of the present invention, the aforementioned identification symbol includes Arabic numerals or Roman numerals.

In an embodiment of the present invention, the shape of the aforementioned identification symbol includes a rectangle, a square, a diamond, a circle, a triangle, a polygon, a cross, or a star.

In an embodiment of the present invention, the line width of each first linear layer and the spacing between the first linear layers are the same, and the line width of each second linear layer and the spacing between the second linear layers same.

In an embodiment of the present invention, the line width of each first line type layer is the same as the line width of each second line type layer, and the spacing between the first line type layers and the spacing between the second line type layers are the same .

In an embodiment of the present invention, the above-mentioned vernier structure is disposed on the cutting lane of the semiconductor substrate.

In another embodiment of the present invention, the above-mentioned vernier structure is disposed directly under the bonding pads of the chip area of the semiconductor substrate.

A lithography process inspection method of the present invention includes providing the vernier for semiconductor manufacturing as described above, which includes a semiconductor substrate, at least one vernier structure, and a plurality of identification symbols. Perform a lithography process to simultaneously form at least one device pattern on the semiconductor substrate and form a contrast pattern on the vernier structure, the contrast pattern having a first pair of edges in the X direction and a second pair of edges in the Y direction side. Obtain the first shortest distances X1 and X2 from the first pair of sides in the X direction to the two sides of the vernier structure, and at the same time obtain the second shortest distances from the second pair of sides to the other two sides of the vernier structure in the Y direction Y1 and Y2. Take the difference between the first shortest distance X1 and X2 (X1-X2) and the difference between the second shortest distance Y1 and Y2 (Y1-Y2) as the overlap (Overlap, OL) shift value (shift value) to determine whether it exceeds OL offset tolerance. _{According to the length X V of the} vernier structure in the X direction, subtract the sum of the first shortest distance X1 and X2 (= X _V -(X1+X2)) to obtain the critical dimension (CD) offset of the control pattern in the X direction Value to determine whether the CD offset tolerance in the X direction is exceeded. _{According to the length Y V of the} vernier structure in the Y direction, subtract the sum of the second shortest distance Y1 and Y2 (= Y _V- (Y1+Y2)) to obtain the critical dimension (CD) offset of the control pattern in the Y direction Value to determine whether the CD offset tolerance in the Y direction is exceeded.

In another embodiment of the present invention, if the above-mentioned OL offset tolerance is exceeded, it may also include performing overlap check (overlap check) or performing rework (rework).

In another embodiment of the present invention, if the allowable amount of CD offset in the X direction is exceeded, it may also include performing SEM check or performing rework.

In another embodiment of the present invention, if the allowable amount of CD offset in the Y direction is exceeded, it may also include performing SEM inspection or performing rework.

In another embodiment of the present invention, the method for obtaining the first shortest distances X1 and X2 and obtaining the second shortest distances Y1 and Y2 includes: using an optical microscope (OM) to observe the first and second opposite sides relative to the cursor The position of the ruler structure is used to determine the first shortest distances X1 and X2 and the second shortest distances Y1 and Y2 according to the above identification symbols.

In another embodiment of the present invention, the method of obtaining the first shortest distances X1 and X2 and obtaining the second shortest distances Y1 and Y2 includes: using a scanning electron microscope (SEM) to capture images, and observe the Image to obtain the positions of the first and second opposite sides relative to the vernier structure, and determine the first shortest distances X1 and X2 and the second shortest distances Y1 and Y2 according to the identification symbols.

In another embodiment of the present invention, the method for obtaining the first shortest distance X1 and X2, obtaining the second shortest distance Y1 and Y2, and determining whether the OL offset tolerance is exceeded includes: using a SEM tool to obtain The first shortest distances X1 and X2 and the second shortest distances Y1 and Y2 are fed back to the machine performing the lithography process.

In another embodiment of the present invention, the machine of the lithography process may further include adjusting the lithography process after receiving the detection result.

In another embodiment of the present invention, the above-mentioned lithography process includes a lithography process for etching or a lithography process for implantation.

In another embodiment of the present invention, the aforementioned control pattern includes a patterned photoresist, a patterned dielectric layer, or a patterned metal layer.

In another embodiment of the present invention, a dielectric layer may be formed on the semiconductor substrate to cover the vernier structure before performing the lithography process, so that the control pattern and the vernier structure are separated by the dielectric layer.

In another embodiment of the present invention, the size of the comparison pattern is less than 10 times the size of the element pattern.

Based on the above, the present invention can obtain the OL offset and CD value in the X direction and the Y direction at the same time through a detection step by using the vernier placed under the cutting bead or the solder pad, thus reducing the time required for lithography process detection. It even directly omitted the OL inspection site among the original three inspection sites to increase the sampling rate. In addition, since the size of the vernier is close to the actual component size, more accurate detection results can be obtained.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Hereinafter, some embodiments are listed in conjunction with the accompanying drawings for detailed description, but the provided embodiments are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only, and are not drawn in accordance with the original dimensions. To facilitate understanding, the same elements in the following description will be described with the same symbols. In addition, the terms "include", "include", "have" and so on used in the text are all open terms; that is, include but are not limited to. Moreover, the directional terms mentioned in the text, such as "上", "下", etc., are only used to refer to the directions of the drawings. Therefore, the directional terms used are used to illustrate, but not to limit the present invention.

FIG. 1A is a schematic top view of a vernier for semiconductor manufacturing according to the first embodiment of the present invention. FIG. 1B is a schematic cross-sectional view of a vernier used in a semiconductor process on the line I-I in FIG. 1A.

Referring to FIGS. 1A and 1B, the vernier for the semiconductor process of the first embodiment includes at least one vernier structure 102 and a plurality of identification symbols 104 formed in the semiconductor substrate 100. The vernier structure 102 includes a plurality of first linear layers 106 extending in the X direction and a plurality of second linear layers 108 extending in the Y direction. The first linear layers 106 and the second linear layers 108 are intersected, wherein The line width w1 of each first linear layer 106 is, for example, the same as the spacing s1 between the first linear layers 106, and the line width w2 of each second linear layer 108 is, for example, the spacing between the second linear layers 108 s2 is the same. In an embodiment, the first linear layer 106 and the second linear layer 108 are, for example, a shallow trench isolation structure (STI). The identification symbol 104 is formed on at least one end of each first linear layer 106 and at least one end of each second linear layer 108 to distinguish between different first linear layers 106 and different second linear layers 106 in the vernier structure 102.线型层108。 Line type layer 108. In this embodiment, the identification symbol 104 is an Arabic numeral (0, 1, 2...), but the present invention is not limited to this, and the identification symbol 104 may also be a Roman numeral (I, II, III...). In the case that the component size is getting smaller and smaller, the identification symbol 104 can also be replaced with a symbol of a different row shape, such as a rectangle, a square, a diamond, a circle, a triangle, a polygon, a cross, or a star.

In FIG. 1A, five first linear layers 106 and five second linear layers 108 are shown. However, the present invention is not limited to this. According to the wavelength of the light source used by the exposure machine, thinner linear layers and more can be formed. Line type layer. For example, I-line light source (wavelength 365nm) can produce minimum line width of 350nm; KrF light source (wavelength 248nm) can produce minimum line width of 150nm, ArF light source (wavelength 193nm) can produce minimum line width of 65nm , ArF light source immersion lithography can produce the smallest line width is 19nm, so if the I-line lithography process is to be tested, the vernier structure 102 can use the ArF lithography process to form 5 lines with a line width w1 of 65nm. The linear layer 106 and five second linear layers 108 with a line width w2 of 65 nm, the spacing s1 between the first linear layers 106 is also 65 nm, and the spacing s2 between the second linear layers 108 is also 65 nm. When the pattern that should be formed in the center of the vernier structure 102 (the dotted line represents a square with 350 nm in length and width) is shifted to the pattern 110 in the lower left corner, the X-direction offset ∆X can be directly obtained from the vernier structure 102 The offset from the Y direction is ∆Y. Once any of the X-direction offset ∆X and Y-direction offset ∆Y exceeds the allowable offset, the lithography process needs to be corrected or reworked. By analogy, if the KrF lithography process is to be tested, the vernier structure 102 can use ArF light source immersion lithography to form 15 first linear layers (not shown) with a line width w1 of about 20 nm and 15 line widths. The second linear layer (not shown) with w2 of about 20 nm, and the spacing s1 between the first linear layers and the spacing s2 between the second linear layers are also about 20 nm.

In addition, if the inspection is performed for a lithography process with a larger line width (such as I-line), as shown in FIG. 2, the vernier structure 200 can be formed by using immersion lithography such as an ArF light source to form a first line with a smaller line width w1 The type layer 202 and the second line type layer 204 with the smaller line width w2 can not only directly obtain the X-direction offset ∆X and Y-direction offset ∆Y from the vernier structure 200 by referring to the identification symbol 206, but also because of the vernier structure The first linear layer 202 and the second linear layer 204 of 200 are very thin and dense, and can also be used to obtain critical dimensions (CD) in the X and Y directions.

Please refer to Figure 1A and Figure 2 again. Since the first linear layer 106/202 and the second linear layer 108/204 in the vernier structure 102/200 are close to each other, in order to clearly distinguish which identification symbol 104/206 corresponds to For one line, the length of the center line CL in the first linear layer 106/202 will be greater than the length of the remaining first linear layers 106/202, and the length of the center line CL in the second linear layer 108/204 will also be greater than that of the remaining first linear layers. The length of the two-line layer 108/204. Although the above description is based on the line width w1 of each first linear layer 106/202 being the same as the line width w2 of each second linear layer 108/204, and the spacing s1 between the first linear layers 106/202 The same as the spacing s2 between the second linear layers 108/204 as an example, but the present invention is not limited to this.

On the whole, the length and width of the vernier used in the semiconductor manufacturing process of this embodiment is about 1 micron. Therefore, compared with the existing alignment mark (length and width), which is often tens of micrometers, the area is roughly reduced by hundreds of times. The vernier structure 102/200 (together with the identification symbols 104/206) of the embodiment can not only be placed on the cutting lane of the semiconductor substrate 100, but also can be placed directly under the bonding pads of the chip area of the semiconductor substrate 100. Because there are usually no lines under the solder pads and the area of the solder pads is large, the vernier structure 102/200 with a small size can be designed in the semiconductor substrate 100 directly under the solder pads.

1C is a schematic cross-sectional view of another vernier used in the semiconductor process on the line II of FIG. 1A. The same component symbols as in FIG. 1B are used to represent the same or similar components, and some technical descriptions omitted, such as the positions of various layers or regions , Size, etc. can refer to the content of FIG. 1B, so it will not be described in detail below.

In FIG. 1C, the vernier for semiconductor manufacturing is composed of a vernier structure 102 and an identification code 104 formed on a semiconductor substrate 100, and the first linear layer (not shown) and the second linear layer 108 are polysilicon wires. That is to say, the first line-type layer (not shown) and the second line-type layer 108 can be fabricated together with the polysilicon gate in the device region, so the line width w2 can be small.

FIG. 3 is a diagram of the inspection steps of a lithography process according to the second embodiment of the present invention.

3, the second embodiment of the lithographic process inspection method needs to provide the vernier for the semiconductor process of the previous embodiment (step S300), which includes the semiconductor substrate shown in FIGS. 1A to 2, the vernier structure, and The identification symbols and the technical descriptions of the various components of the vernier used in the semiconductor manufacturing process, such as the position and size of the linear layer, and the style of the identification symbols, can refer to the content of the first embodiment, and therefore will not be repeated hereafter.

Then, a lithography process (step S302) is performed to simultaneously form at least one device pattern on the semiconductor substrate and a control pattern (110 in FIG. 1A) on the vernier structure (102 in FIG. 1A). The lithography process can be a lithography process for etching or a lithography process for implantation, so the control pattern can be a patterned photoresist after development, a patterned dielectric layer after etching, or a patterned metal after etching Floor. As for the device pattern, it is the pattern of the doped area or circuit actually formed in the device area. Therefore, the size of the control pattern may be 10 times or less the size of the aforementioned element pattern. For example, if the vernier structure is an STI directly formed in the semiconductor substrate, a photoresist can be coated on the surface of the semiconductor substrate, and then step S302 is performed to make the photoresist a patterned photoresist (ie a control pattern); if The vernier structure is an STI directly formed in the semiconductor substrate. Alternatively, before step S302, a dielectric layer covering the STI can be formed on the semiconductor substrate, and then a photoresist is coated on the surface of the dielectric layer, and then step S302 is performed to make The photoresist becomes a patterned photoresist (ie, a control pattern). Similarly, if the vernier structure is a polysilicon line formed on a semiconductor substrate, before step S302, a dielectric layer is formed on the semiconductor substrate to cover the polysilicon line and then a photoresist is applied, and then step S302 is performed to make the above The photoresist becomes a patterned photoresist (ie, a control pattern). In addition, after the patterned photoresist is formed, an etching process can also be performed first to etch the above-mentioned dielectric layer into a patterned dielectric layer (ie, a control pattern). It can also be implemented if the above dielectric layer is replaced with a metal layer, so it will not be repeated.

The control pattern is generally square or rectangular, so it has a first pair of sides in the X direction and a second pair of sides in the Y direction. Then, obtain the first shortest distances X1 and X2 from the first pair of sides to the two sides of the vernier structure in the X direction, and obtain the second distances from the second pair of sides to the other two sides of the vernier structure in the Y direction. The shortest distances Y1 and Y2 (step S304). In one embodiment, the method of obtaining X1 and X2 and Y1 and Y2 includes: using an optical microscope (OM) to observe the positions of the first and second opposite sides of the control pattern relative to the vernier structure to identify The symbol determines the first shortest distances X1 and X2 and the second shortest distances Y1 and Y2. In another embodiment, the method of obtaining X1 and X2 and Y1 and Y2 includes: using a scanning electron microscope (SEM) to take images to obtain images, and to observe the images to obtain the first pair of sides and the contrast pattern The position of the second opposite side relative to the vernier structure, and the first shortest distance X1 and X2 and the second shortest distance Y1 and Y2 are determined according to the identification symbols.

Next, the difference between the first shortest distance X1 and X2 (X1-X2) and the difference between the second shortest distance Y1 and Y2 (Y1-Y2) are used as the overlap (OL) shift value (shift value) to determine Whether it exceeds the OL offset allowable amount (step S306). In one embodiment, in step S304, if X1, X2, Y1, and Y2 are directly obtained by using a SEM tool (SEM tool), it can be determined whether the OL offset tolerance is exceeded (step S306) and the detection result is fed back to step S302 The machine of the photolithography process. After the machine performing the lithography process in step S302 receives the above detection result, it can also adjust the lithography process in step S302 to reduce the OL offset value. Moreover, the directional deviation can be judged based on whether the above difference is positive or negative. For example, if the difference (X1-X2) is negative, it means shifting to the right, and so on.

At the same time, according to the length X _{V of the} vernier structure in the X direction, subtract the sum of the first shortest distance X1 and X2 (= X _V -(X1+X2)) to obtain the critical dimension (CD) of the control pattern in the X direction The offset value is used to determine whether the CD offset allowable amount in the X direction is exceeded (step S308). _{According to the length Y V of the} vernier structure in the Y direction, subtract the sum of the second shortest distance Y1 and Y2 (= Y _V- (Y1+Y2)) to obtain the critical dimension (CD) offset of the control pattern in the Y direction Value to determine whether the CD offset tolerance in the Y direction is exceeded (step S310).

If the determination result of steps S306, S308, and S310 is "No", the detection is completed.

If the OL offset tolerance is exceeded, you can choose to perform overlap check (step S312) or perform rework (step S314).

If the CD offset tolerance in the X direction is exceeded, it may also include performing SEM Check (step S316) or performing rework (step S314).

If the CD offset tolerance in the Y direction is exceeded, you can choose to perform SEM inspection (step S316) or perform rework (step S314).

When the lithography process originally has three inspection stations, such as an overlapping inspection station in the X and Y directions using OM, a CD inspection station using SEM tool, and a visual inspection (Visual Check) station, the inspection method of this embodiment can be used To achieve the following effects.

First, if the OM is used for visual inspection and X1, X2, Y1, and Y2 are obtained at the same time, the degree of OL shift can be determined, so the above-mentioned overlapping detection station is omitted. Or, if you use SEM tool to perform CD inspection and obtain X1, X2, Y1, and Y2 at the same time, you can also determine the degree of OL shift when obtaining the CD value, and omit the above-mentioned overlapping inspection station. On the other hand, if the OM is used for visual inspection and the CD values in the X direction and the Y direction are simultaneously measured by the method of the present invention, the CD sampling rate can also be improved.

In summary, the present invention can obtain the OL offset and CD value in the X direction and Y direction at the same time through a detection step by using a vernier placed under the cutting bead or the solder pad, thus reducing the amount of inspection in the lithography process. Time, even directly omit the OL inspection site among the original three inspection sites to increase the sampling rate. In addition, since the size of the vernier is close to the actual component size, more accurate detection results can be obtained. The vernier can be formed on or in the semiconductor substrate, so in addition to the detection of the lithography process (etching or implantation) of the component (cell), it can also lithography of the circuits on it (such as M1, M2...) Process (etching) for inspection.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100: semiconductor substrate 102, 200: vernier structure 104, 206: identification symbols 106, 202: first linear layer 108, 204: second linear layer 110: control pattern CL: center line s1, s2: spacing S300, S302 , S304, S306, S308, S310, S312, S314, S316: Steps X1, X2: the first shortest distance X _V , Y _V : length Y1, Y2: the second shortest distance ∆X: X-direction offset ∆Y: Y direction offset w1, w2: line width

FIG. 1A is a schematic top view of a vernier for semiconductor manufacturing according to the first embodiment of the present invention. FIG. 1B is a schematic cross-sectional view of a vernier used in a semiconductor process on the line I-I in FIG. 1A. FIG. 1C is a schematic cross-sectional view of another vernier used in the semiconductor manufacturing process along the line I-I in FIG. 1A. FIG. 2 is a schematic top view of another vernier used in the semiconductor process of the first embodiment. FIG. 3 is a diagram of the inspection steps of a lithography process according to the second embodiment of the present invention.

102: Vernier structure

104: identification symbol

106: The first linear layer

108: The second linear layer

110: Contrast pattern

CL: midline

s1, s2: spacing

X1, X2: the first shortest distance

X _V , Y _V : length

Y1, Y2: second shortest distance

△X: X direction offset

△Y: Y direction offset

w1, w2: line width

Claims (12)

A method for detecting a lithography process includes: providing a vernier for a semiconductor process, which includes a semiconductor substrate, at least one vernier structure, and a plurality of identification symbols; and performing a lithography process to simultaneously form at least one vernier on the semiconductor substrate. The element pattern forms a contrast pattern on the vernier structure, the contrast pattern having a first pair of edges in the X direction and a second pair of edges in the Y direction; obtaining the first pair of edges in the X direction to The first shortest distances X1 and X2 on both sides of the vernier structure and the second shortest distances Y1 and Y2 from the second pair of sides to the other two sides of the vernier structure in the Y direction; The difference between the distances X1 and X2 and the difference between the second shortest distance Y1 and Y2 are used as overlap (OL) shift values, and it is determined whether the OL shift tolerance is exceeded; according to the vernier structure _{The length X V} in the X direction minus the sum of the first shortest distance X1 and X2 (X1+X2), obtain the critical dimension (CD) offset value of the comparison pattern in the X direction to determine whether it exceeds the X direction And subtract the sum of the second shortest distance Y1 and Y2 (Y1+Y2) according to _{the length Y V of the} vernier structure in the Y direction to obtain the criticality of the comparison pattern in the Y direction The size (CD) offset value to determine whether the CD offset tolerance in the Y direction is exceeded. The lithography process inspection method according to claim 1, wherein if the OL offset tolerance is exceeded, it further includes: performing overlap check or performing rework. The lithography process inspection method according to claim 1, wherein if the CD offset tolerance in the X direction is exceeded, it further includes: performing SEM inspection (SEM Check) or performing rework. The lithography process inspection method according to claim 1, wherein if the CD offset tolerance in the Y direction is exceeded, it further includes: performing SEM inspection or performing rework. The lithography process inspection method according to claim 1, wherein the method of obtaining the first shortest distances X1 and X2 and obtaining the second shortest distances Y1 and Y2 includes: observing the first distance using an optical microscope (OM) The positions of the opposite side and the second opposite side relative to the vernier structure are used to determine the first shortest distances X1 and X2 and the second shortest distances Y1 and Y2 according to the identification symbols. The lithography process inspection method according to claim 1, wherein the method of obtaining the first shortest distance X1 and X2 and obtaining the second shortest distance Y1 and Y2 includes: using a scanning electron microscope (SEM) to photograph Image, and observe the image to obtain the positions of the first pair of sides and the second pair of sides relative to the vernier structure, and determine the first shortest distances X1 and X2 and the The second shortest distance Y1 and Y2. The lithography process detection method according to claim 1, wherein the method of obtaining the first shortest distances X1 and X2, obtaining the second shortest distances Y1 and Y2, and determining whether the OL offset tolerance is exceeded includes: Use SEM tool (SEM tool) The first shortest distances X1 and X2 and the second shortest distances Y1 and Y2 are obtained, and the detection results are fed back to the machine performing the lithography process. The lithography process detection method according to claim 7, wherein after the lithography process machine receives the detection result, it further includes: adjusting the lithography process. The lithography process inspection method according to claim 1, wherein the lithography process includes a lithography process for etching or a lithography process for implantation. The lithography process inspection method according to claim 1, wherein the control pattern includes a patterned photoresist, a patterned dielectric layer, or a patterned metal layer. The lithography process inspection method according to claim 1, wherein before the lithography process is performed, it further comprises forming a dielectric layer on the semiconductor substrate to cover the vernier structure, so that the control pattern and the The vernier structure is separated by the dielectric layer. The lithography process inspection method according to claim 1, wherein the size of the control pattern is less than 10 times the size of the device pattern.

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