TWI742828B - Gallium nitride epitaxial wafer capable of reducing stress - Google Patents

Abstract

A gallium nitride (GaN) epitaxial wafer capable of reducing stress, including a substrate, a nucleation layer on the substrate, multiple aluminum gallium nitride (Al_xGa_(1-x)N) buffer layers on the nucleation layer, multiple inter-superlattice structure layers, wherein some inter-superlattice structure layers are intermediate between two of the aluminum gallium nitride buffer layers, a high resistive layer on the topmost aluminum gallium nitride buffer layer, an intrinsic gallium nitride layer on the high resistive layer, an electron donor layer on the intrinsic gallium nitride layer and a capping layer on the electron donor layer.

Description

Gallium nitride epitaxy wafer capable of reducing stress

The present invention is generally related to a gallium nitride epitaxial wafer, and more specifically, it relates to a gallium nitride grown on a silicon-on-insulator (SOI) wafer that can reduce growth stress. Epi wafer.

In recent years, gallium nitride (GaN) materials have received many attentions and applications in the industry, such as the future 5G market, electric vehicles, radar satellite communications, radio transmission, and medical technology. Because gallium nitride material has the characteristics of high energy band, high breakdown electric field, high thermal conductivity, high saturated electron velocity and small component size, these characteristics make gallium nitride regarded as equivalent in the application of high power and high speed electrical transistors. Ideal material, especially in the application of high-frequency components is quite extensive.

Silicon substrates have competitive advantages in terms of price and cost. Therefore, circuit design schemes for growing gallium nitride on silicon substrates are being researched and developed vigorously. However, the inherent lattice constants and thermal expansion coefficients of gallium nitride and silicon substrates are too different in nature, so the heteroepitaxial method of directly growing gallium nitride on silicon substrates will cause excessive lattice mismatch (about 17 %) and thermal expansion coefficient mismatch (approximately 54%). During the growth period, a large tensile stress will be generated, forming a high-density spiral dislocation, which will cause the wafer to warp or even crack, which will lead to the formation of electrical Gallium nitride devices increase leakage current and reduce carrier mobility and operating efficiency.

At present, the industry has proposed several methods to solve the above-mentioned problem of the mismatch between gallium nitride and silicon substrates. Question, one of the methods is to grow gallium nitride on a silicon-on-insulator (SOI) wafer.

In view of the above-mentioned conventional problems in the growth of gallium nitride, the present invention proposes an improved gallium nitride epitaxial wafer with high quality and low loss characteristics based on the existing solutions proposed in the industry. Overlay a silicon-on-insulator (SOI) on the insulating layer, and match the graded layer and the change of the inter super lattices structure (inter-SLS) to buffer the growth of gallium nitride The stress caused by the overall epitaxial structure can exceed 10um, and the breakdown voltage can exceed 1000 volts. This improves the efficiency of gallium nitride devices. It is particularly suitable for making gallium nitride-based high electron mobility transistors. (high electron mobility transistors, HEMTs).

The purpose of the present invention is to provide a gallium nitride epitaxial wafer capable of reducing stress, comprising a substrate, a nucleation layer on the substrate, a plurality of aluminum gallium nitride buffer layers on the nucleation layer, and a plurality of intermediate layers. Superlattice structure layer, in which part of the intermediate superlattice structure layer is located between the two aluminum gallium nitride buffer layers, a high resistance layer, is located on the uppermost aluminum gallium nitride buffer layer, and The essential gallium nitride layer is located on the high resistance layer, an electron supply layer is located on the essential gallium nitride layer, and a covering layer is located on the electron supply layer.

Such objects and other objects of the present invention should become more apparent after readers have read the detailed description of the preferred embodiments described below with various illustrations and drawings.

100: Support wafer

101: insulating oxide layer

103: Component Wafer

110: Substrate (silicon wafer over insulating layer)

120: Nucleation layer

121: low temperature aluminum nitride layer

122: high temperature aluminum nitride layer

130: Intermediate superlattice structure layer

130a, 130b, 130c: superlattice group

140: Superlattice Pair

140a: the first superlattice layer

140b: second superlattice layer

150: buffer layer

151: (first) aluminum gallium nitride buffer layer

152: (Second) Aluminum Gallium Nitride buffer layer

153: (third) aluminum gallium nitride buffer layer

154: (fourth) aluminum gallium nitride buffer layer

155: (fifth) aluminum gallium nitride buffer layer

160: high resistance layer

170: Intrinsic GaN layer

180: electronic provision layer

190: Overlay

This specification contains drawings and constitutes a part of this specification in the text, so that readers can have a further understanding of the embodiments of the present invention. These diagrams depict some embodiments of the invention and are described herein together The principle is explained together. In these figures: Figure 1 illustrates the manufacturing process of a silicon-on-insulator (SOI) wafer according to an embodiment of the present invention; Figure 2 illustrates an implementation according to the present invention In the example, the step of forming a nucleation layer on a silicon wafer over an insulating layer; Fig. 3 illustrates the detailed structure of an intermediate superlattice structure layer in a preferred embodiment of the present invention; Fig. 4 illustrates a step according to The type of buffer layer formed on the nucleation layer in an embodiment of the present invention; FIG. 5 illustrates the type of buffer layer formed on the nucleation layer in another embodiment of the present invention; FIG. 6 illustrates According to another embodiment of the present invention, the buffer layer is formed on the nucleation layer; Fig. 7 shows the buffer layer formed on the nucleation layer in another embodiment of the present invention; Fig. 8 is Figure 9 illustrates the form of the buffer layer formed on the nucleation layer according to another embodiment of the present invention; Figure 9 depicts the form of the buffer layer formed on the nucleation layer according to another embodiment of the present invention; and Figure 10 illustrates the detailed structure of a gallium nitride epitaxial wafer according to a preferred embodiment of the present invention.

It should be noted that all the illustrations in this manual are illustrations in nature. For clarity and convenience of illustration, the parts in the illustrations may be exaggerated or reduced in size and proportion. Generally speaking, the figures The same reference symbols will be used to indicate corresponding or similar element features in modified or different embodiments.

Now, exemplary embodiments of the present invention will be described in detail below, which will illustrate the described features with reference to the accompanying drawings so that readers can understand and achieve technical effects. Readers will understand that the description in the text is only done by way of example, and is not intended to limit the case. The various embodiments of this case and various features in the embodiments that do not conflict with each other can be combined or re-arranged in various ways. Without departing from the spirit and scope of the present invention, modifications, equivalents or improvements to this case are for those skilled in the art It is understandable and intended to be included in the scope of this case.

Readers should be able to easily understand that the meanings of "on", "on" and "on" in this case should be interpreted in a broad way, so that "on" not only means "directly on" "Something is "on", but also includes "on" something with the meaning of intervening features or layers in between, and "on" or "on" not only means "on" something "on" Or "above", and it can also include the meaning of "above" or "above" something without intervening features or layers (that is, directly on something).

In addition, for the convenience of description, space-related terms such as "below", "below", "lower", "above", "upper" and other space-related terms can be used herein to describe an element or feature The relationship with another element or features is as shown in the drawings.

In the following description, the terms "substrate" and "wafer" are interchangeable, and can include any semiconductor structure with circuits formed inside or on the surface. These structures can include silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped or undoped semiconductors, silicon epitaxial layers supported by semiconductor substrates, or other semiconductor structures, etc. . The semiconductor does not have to be silicon, it can also be silicon germanium, germanium, or gallium arsenide. When the substrate is mentioned in the following, there may have been processing steps in or on the semiconductor substrate to form a layer, region, or junction structure.

As used herein, the term "layer" refers to a portion of material that includes regions of thickness. The layer may extend over the entirety of the lower or upper structure, or may have a range smaller than the range of the lower or upper structure. In addition, the layer may be a region of a homogeneous or non-homogeneous continuous structure whose thickness is less than that of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal faces at the top and bottom surfaces. The layers can extend horizontally, vertically, and/or along inclined surfaces. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers on, above, and/or below it.

The description in the text will use names such as "N" and "P", generally with "N-type" and "P-type" It refers to the donor and acceptor dopants that promote electrons and holes as the main carriers. A dopant type suffixed with a "++" symbol indicates that its doping concentration is higher than that of those dopants suffixed with a "+" symbol. Conversely, the dopant type with the suffix "-" means that the dopant concentration of the dopant is lower than the dopant concentration of the dopants without the suffix symbol.

Firstly, please refer to FIG. 1, which illustrates the manufacturing process of a silicon-on-insulator (SOI) wafer according to an embodiment of the present invention. First, a handle wafer 100 is provided, which is preferably a heavily doped silicon wafer, but also a harder silicon carbide wafer or sapphire wafer, with a thickness of about 300-800um. Then, a high-temperature oxidation process is performed on the supporting wafer 100, so that an insulating oxide layer 101 is grown on both sides of the supporting wafer 100. The temperature during the high-temperature oxidation process can range from 1000 to 1100°C, and the thickness of the grown insulating oxide layer 101 is between 0.05 to 5um. The material can be silicon oxide (SiO ₂ ) or silicon oxide (SiO 2) depending on the source of the supporting wafer 100 Alumina (Al ₂ O ₃ ). Next, a piece of device wafer 103 is bonded to the insulating oxide layer 101 on one side of the support wafer 100 and an annealing process is performed to convert the weak bond between the two to a strong covalent bond. Finally, the bonded device wafer 103 is thinned to the required thickness, between about 1 and 10um, using a process such as chemical mechanical polishing (CMP) or backside polishing. In this way, a silicon-on-insulating wafer is completed. 110.

The silicon-on-insulating wafer 110 formed in the above embodiments will be used as the base of the gallium nitride epitaxial wafer of the present invention in subsequent embodiments. Among them, the insulating oxide layer 101 in the silicon wafer 110 over the insulating layer that is connected to the device wafer 103 can be used as an insulator material between the silicon transistors, which can greatly reduce the parasitic capacitance therebetween. The insulating oxide layer 101 on the other side It can be used as a fixed layer to compensate the stress generated during the subsequent epitaxial process and avoid the conventional warpage problem of the wafer.

After completing the preparation of the silicon-on-insulation wafer 110, the next step is to proceed with the preparation of the gallium nitride epitaxial wafer of the present invention. In order to grow heteroepitaxial crystals on the silicon-on-insulating wafer 110, it is necessary to form a nucleation layer and a buffer layer on the silicon-on-insulating wafer 110 to ensure the quality of the grown epitaxial crystals. The preferred embodiment of the present invention adopts a double-layer nucleation layer with different properties. First, an organometallic chemical vapor deposition is used Firstly, a low-temperature aluminum nitride layer (LT-AlN) 121 is grown on the silicon-on-insulating wafer 110 by MOCVD method. The growth temperature is 900-1000° C., and the thickness is 30-80 nm. After that, a high temperature aluminum nitride layer (HT-AlN) 122 is grown on the low temperature aluminum nitride layer 121, the growth temperature of which is between 1000 and 1300° C., and the thickness is between 30 and 200 nm. By growing an aluminum nitride nucleation layer with two different properties of low temperature and high temperature before the growth of the gallium nitride epitaxial layer, the subsequent growth of the gallium nitride epitaxial layer will tend to be a two-dimensional growth pattern, which will be relatively flat. The surface and the better crystal quality. In the following embodiments, the nucleation layer 120 will be collectively referred to as the low temperature aluminum nitride layer 121 and the high temperature aluminum nitride layer 122.

After the production of the nucleation layer 120 is completed, the production of the buffer layer is next. A major feature of the present invention is that the buffer layer is composed of multiple graded layers and one or more inter-superlattice structure (inter-SLS) layers interspersed therebetween. Wherein, in the embodiment of the present invention, the plurality of graded layers may be aluminum gallium nitride (Al _x Ga _(1-x) N) buffer layers, and the proportions of aluminum atoms in the aluminum gallium nitride buffer layers are different from each other, Moreover, the proportion of aluminum atoms in each single aluminum gallium nitride buffer layer is also gradual rather than fixed. On the other hand, the intermediate superlattice structure layer of the present invention is a periodic alternating laminated structure composed of two or more materials. The arrangement of the intermediate superlattice structure layer between the graded buffer layers will help to connect the crystal lattices on both sides to the At the same time, there is no interface misfit and dislocation, so that the crystal lattice is completely in a state of elastic strain.

Please refer now to FIG. 3, which illustrates the detailed structure of an intermediate superlattice structure layer 130 in an embodiment of the present invention. In the present invention, each intermediate superlattice structure layer 130 is composed of a plurality of superlattice groups in a stacked manner, and the plurality of superlattice groups have the same material composition but different thickness distributions. In the embodiment of the present invention, the superlattice groups in the intermediate superlattice structure layer 130 are preferably three groups, which are represented by 130a, 130b, and 130c in the figure. Furthermore, each superlattice group 130a, 130b, 130c further includes a plurality of superlattice pairs. For example, in a preferred embodiment, each superlattice group 130a, 130b, 130c has 40 superlattice pairs. In the figure, 140 represents a superlattice pair. There are more than one superlattice pair in the same superlattice group. Each superlattice pair 140 may have exactly the same structure and material composition. Furthermore, each superlattice pair 140 further includes a first superlattice layer 140a and a second superlattice layer 140b located on the first superlattice layer 140a. First The superlattice layer 140a and the second superlattice layer 140b have the same material composition, but have different atomic ratios and thickness distributions.

The detailed characteristics of the intermediate superlattice structure layer 130, the superlattice groups 130a, 130b, 130c, the superlattice pair 140, the first superlattice layer 140a, and the second superlattice layer 140b will now be explained with actual data. In a preferred embodiment of the present invention, an intermediate superlattice structure layer 130 is divided into three superlattice groups 130a, 130b, 130c, and each superlattice group 130a, 130b, 130c is further divided into 40 superlattice groups. Lattice pair 140, so an intermediate superlattice structure layer 130 has a total of 120 superlattice pairs 140, of which pairs 1-40 are the first group, pairs 41-80 are the second group, and pairs 81-120 are the first group. Three groups. Among them, the composition of the superlattice pair 140 in the three superlattice groups 130a, 130b, 130c is the same, and each superlattice pair 140 is composed of a first superlattice layer 140a and a second superlattice layer 140a. The grid layer 140b is composed. The material of the first superlattice layer 140a and the second superlattice layer 140b can be aluminum gallium nitride, but they have different aluminum atomic ratios. For example, the first superlattice layer 140a is Al _x Ga _{(1- x)} N and the second superlattice layer 140b is Al _y Ga _(1-y) N, where x is not equal to y. Furthermore, the first superlattice layer 140a and the second superlattice layer 140b of the superlattice pair 140 in the different superlattice groups 130a, 130b, and 130c may have different thicknesses. For example, the thickness distribution ranges of the first superlattice layer 140a and the second superlattice layer 140b of the superlattice pair 140 (pairs 1-40) in the first superlattice group 130a are 21-25 nm/1. ~6nm, the thickness distribution range of the first superlattice layer 140a and the second superlattice layer 140b of the superlattice pair 140 (pairs 41-80) in the second superlattice group 130b is 11~15nm, respectively /11~15nm, the thickness distribution ranges of the first superlattice layer 140a and the second superlattice layer 140b of the superlattice pair 140 (pairs 81-120) in the third superlattice group 130c are 1 ~6nm/21~25nm, it can be seen that the farther from the substrate 110 (that is, the upper layer) the thickness of the first superlattice layer 140a in the superlattice group will be smaller, and the farther the superlattice is from the substrate 110 The thickness of the second superlattice layer 140b in the group is greater. The above-mentioned superlattice layer can be grown and formed by MOCVD, and its growth temperature is between 950 and 1150°C. In addition, the ratio of aluminum atoms in the first superlattice layer 140a and the second superlattice layer 140b will be the same as the ratio of aluminum atoms in the layer structure connected up and down by the intermediate superlattice structure layer 130, which will be described in subsequent embodiments. There is further explanation.

The above-mentioned intermediate superlattice structure layer 130 of the present invention can be interspersed between the various layer structures of the buffer layer in various forms to achieve the desired effect, which will be described in different embodiments as follows:

[Example 1]

Please refer to FIG. 4, which illustrates a type of a buffer layer 150 formed on the nucleation layer 120 according to an embodiment of the present invention. In this embodiment, the buffer layer 150 includes a total of five aluminum gallium nitride buffer layers (graded layers) 151-155 and an intermediate superlattice structure layer 130, wherein the intermediate superlattice structure layer 130 is disposed on the nucleation layer 120 and the lowermost aluminum gallium nitride buffer layer 151. In terms of structural composition, although the composition of the five aluminum gallium nitride buffer layers 151-155 are all aluminum gallium nitride (Al _z Ga _(1-2) N), the proportion of aluminum atoms is different. For example, in an embodiment, the z of the first aluminum gallium nitride buffer layer 151 is between 0.7 and 0.95, the z of the second aluminum gallium nitride buffer layer 152 is between 0.5 and 0.65, and the third aluminum gallium nitride buffer layer has z between 0.5 and 0.65. The z of the buffer layer 153 is between 0.3-0.45, the z of the fourth aluminum gallium nitride buffer layer 154 is between 0.15-0.25, and the z of the fifth aluminum gallium nitride buffer layer 155 is between 0.05-0.15 . It can be seen that in the embodiment of the present invention, the farther away from the substrate 110 and the closer to the upper aluminum gallium nitride buffer layer 151-155, the lower the proportion of aluminum atoms is set. In this way, the design of the aluminum gallium nitride buffer layer with the lower the atomic ratio of aluminum in the upper layer can effectively buffer the stress from the aluminum nitride nucleation layer 120 to the gallium nitride epitaxial layer to be subsequently grown. On the other hand, in the embodiment of the present invention, the proportion of aluminum atoms in a single aluminum gallium nitride buffer layer may also be in a gradual state. For example, taking the first aluminum gallium nitride buffer layer 151 as an example, the Al _z Ga _{(1 -z)} The z value (aluminum atomic ratio) in the N component is between 0.7 and 0.95, which may be that the z value in the first aluminum gallium nitride buffer layer 151 moves from 0.95 on the side close to the substrate 110 to far away from the substrate 110 The 0.7 on one side gradually becomes smaller. The gradient design of the aluminum atom ratio in the aluminum gallium nitride buffer layer also helps to gradually buffer the stress. The above-mentioned aluminum gallium nitride buffer layers 151-155 can be grown and formed by MOCVD, and the growth temperature is between 1000 and 1200°C.

In addition to the change in the aluminum atomic ratio, in the embodiment of the present invention, the thickness of each aluminum gallium nitride buffer layer 151-155 is also different. Basically, the aluminum gallium nitride buffer layer 151-155 farther away from the substrate 110 The greater the thickness. For example, in the embodiment of the present invention, the thickness of the first aluminum gallium nitride buffer layer 151 is between 50 and 200 nm, the thickness of the second aluminum gallium nitride buffer layer 152 is between 150 and 220 nm, and the third nitrogen The thickness of the aluminum gallium nitride buffer layer 153 is between 350 and 600 nm, the thickness of the fourth aluminum gallium nitride buffer layer 151 is between 800 and 1500 nm, and the thickness of the fifth aluminum gallium nitride buffer layer 155 is between 1600 nm. Between 2300nm. In this way, the higher the thickness of the aluminum gallium nitride buffer layer is, the thicker the design can also effectively alleviate the stress effect during the subsequent growth of gallium nitride.

Furthermore, in the embodiment of the present invention, the aluminum gallium nitride buffer layer 151-155 may also be doped with impurities, such as doped with dopants of carbon, iron, magnesium, zinc, etc. or a combination thereof, so that the aluminum gallium nitride buffer layer Layers 151-155 become doped aluminum gallium nitride layers. Wherein, the dopant concentration doped will also be different for each aluminum gallium nitride buffer layer 151-155. For example, in the embodiment of the present invention, the dopant concentration of the first aluminum gallium nitride buffer layer 151 is greater than 1×10 ¹⁷ ions/cm ^ 3, and the dopant concentration of the second aluminum gallium nitride buffer layer 152 is greater than 3×10 ¹⁷ ions/cm ^ 3 doping concentration, a third aluminum gallium nitride buffer layer 153 is greater than 5x10 ¹⁷ ions / cm ^, the fourth dopant concentration of aluminum gallium nitride buffer layer 154 is greater than 7x10 ¹⁷ ions / cm ^, aluminum gallium nitride buffer fifth The dopant concentration of layer 155 is greater than 1×10 ¹⁸ ions/cm ^ 3. It can be seen that the higher the aluminum gallium nitride buffer layer is, the greater its dopant concentration. The gradual design of the dopant concentration also contributes to the improvement of electrical properties.

Regarding the intermediate superlattice structure layer 130 disposed between the nucleation layer 120 and the first aluminum gallium nitride buffer layer 151 in this embodiment, the first part of the intermediate superlattice structure layer 130 was mentioned above. The ratio of aluminum atoms of the superlattice layer 140a and the second superlattice layer 140b will be the same as the ratio of aluminum atoms in the layer structure connected up and down by the intermediate superlattice structure layer 130. Taking this embodiment as an example, the first superlattice layer 140a of the middle superlattice structure layer 130 will be connected to the nucleation layer 120 below. The material of the nucleation layer 120 is aluminum nitride. The aluminum atom ratio x in the first superlattice layer 140a made of aluminum gallium (Al _x Ga _{(1-x) N) is preferably close to or equal to one.} The second superlattice layer 140b of the middle superlattice structure layer 130 will be connected to the first aluminum gallium nitride buffer layer 151 above. The material of the aforementioned first aluminum gallium nitride buffer layer 151 is based on aluminum gallium nitride Upper (Al _z Ga _(1-z) N, the z value is between 0.7 and 0.95), the second superlattice layer 140b is also made of _{aluminum gallium nitride (Al x} Ga _{(1-x) N)} Preferably, the ratio x of aluminum atoms is also between 0.7 and 0.95. With this arrangement, the intermediate superlattice structure layer 130 intersecting in the buffer layer structure can be arranged alternately and stacked by its multiple ultra-thin superlattice pairs 140 having the same composition as the upper and lower junctions. Achieve the effect of connecting the crystal lattices on both sides together without causing interface mismatch and dislocation.

[Example 2]

共15種的插入組合。以圖中為例，成核層120與第一氮化鋁鎵緩衝層151之間以及第一氮化鋁鎵緩衝層151與第二氮化鋁鎵緩衝層152之間插入有中間超晶格結構層130。其他關於緩衝層150中的氮化鋁鎵緩衝層151-155以及中間超晶格結構層130的成分、鋁原子比例、厚度、摻質濃度以及成長方式等規則與實施例1相同。 Please refer to FIG. 5, which illustrates a type of the buffer layer 150 formed on the nucleation layer 120 according to another embodiment of the present invention. In this embodiment, two intermediate superlattice structure layers 130 are inserted between arbitrary aluminum gallium nitride buffer layers 151-155 (including the lowest nucleation layer 120), so that there may be

A total of 15 insert combinations. Taking the figure as an example, an intermediate superlattice is inserted between the nucleation layer 120 and the first aluminum gallium nitride buffer layer 151, and between the first aluminum gallium nitride buffer layer 151 and the second aluminum gallium nitride buffer layer 152. Structural layer 130. Other rules regarding the composition, aluminum atomic ratio, thickness, dopant concentration, and growth mode of the aluminum gallium nitride buffer layers 151-155 in the buffer layer 150 and the intermediate superlattice structure layer 130 are the same as those in the first embodiment.

[Example 3]

共20種的插入組合。以圖中為例，成核層120與第一氮化鋁鎵緩衝層151之間、第一氮化鋁鎵緩衝層151與第二氮化鋁鎵緩衝層152之間、以及第二氮化鋁鎵緩衝層152與第三氮化鋁鎵緩衝層153之間插入有中間超晶格結構層130。其他關於緩衝層150中的氮化鋁鎵緩衝層151-155以及中間超晶格結構層130的成分、鋁原子比例、厚度、摻質濃度以及成長方式等規則與實施例1相同。 Please refer to FIG. 6, which depicts a pattern of the buffer layer 150 formed on the nucleation layer 120 according to another embodiment of the present invention. In this embodiment, three intermediate superlattice structure layers 130 are inserted between arbitrary aluminum gallium nitride buffer layers 151-155 (including the lowest nucleation layer 120), so that there may be

A total of 20 insert combinations. Taking the figure as an example, between the nucleation layer 120 and the first aluminum gallium nitride buffer layer 151, between the first aluminum gallium nitride buffer layer 151 and the second aluminum gallium nitride buffer layer 152, and the second nitride An intermediate superlattice structure layer 130 is inserted between the aluminum gallium buffer layer 152 and the third aluminum gallium nitride buffer layer 153. Other rules regarding the composition, aluminum atomic ratio, thickness, dopant concentration, and growth mode of the aluminum gallium nitride buffer layers 151-155 in the buffer layer 150 and the intermediate superlattice structure layer 130 are the same as those in the first embodiment.

[Example 4]

共15種的插入組合。以圖中為例，成核層120與第一氮化鋁鎵緩衝層151之間、第一氮化鋁鎵緩衝層151與第二氮化鋁鎵緩衝層152之間、第二氮化鋁鎵緩衝層152與第三氮化鋁鎵緩衝層153之間、以及第三氮化鋁鎵緩衝層153與第四氮化鋁鎵緩衝層154之間插入有中間超晶格結構層130。其他關於緩衝層150中的氮化鋁鎵緩衝層151-155以及中間超晶格結構層130的成分、鋁原子比例、厚度、摻質濃度以及成長方式等規則與實施例1相同。 Please refer to FIG. 7, which illustrates the type of the buffer layer 150 formed on the nucleation layer 120 according to another embodiment of the present invention. In this embodiment, four intermediate superlattice structure layers 130 are inserted between arbitrary aluminum gallium nitride buffer layers 151-155 (including the lowest nucleation layer 120).

A total of 15 insert combinations. Taking the figure as an example, between the nucleation layer 120 and the first aluminum gallium nitride buffer layer 151, between the first aluminum gallium nitride buffer layer 151 and the second aluminum gallium nitride buffer layer 152, and the second aluminum nitride An intermediate superlattice structure layer 130 is inserted between the gallium buffer layer 152 and the third aluminum gallium nitride buffer layer 153 and between the third aluminum gallium nitride buffer layer 153 and the fourth aluminum gallium nitride buffer layer 154. Other rules regarding the composition, aluminum atomic ratio, thickness, dopant concentration, and growth mode of the aluminum gallium nitride buffer layers 151-155 in the buffer layer 150 and the intermediate superlattice structure layer 130 are the same as those in the first embodiment.

[Example 5]

共6種的插入組合。以圖中為例，成核層120與第一氮化鋁鎵緩衝層151之間、第一氮化鋁鎵緩衝層151與第二氮化鋁鎵緩衝層152之間、第二氮化鋁鎵緩衝層152與第三氮化鋁鎵緩衝層153之間、第三氮化鋁鎵緩衝層153與第四氮化鋁鎵緩衝層154之間、以及第四氮化鋁鎵緩衝層154與第五氮化鋁鎵緩衝層155之間插入有中間超晶格結構層130。其他關於緩衝層150中的氮化鋁鎵緩衝層151-155以及中間超晶格結構層130的成分、鋁原子比例、厚度、摻質濃度以及成長方式等規則與實施例1相同。 Please refer to FIG. 8, which illustrates the type of the buffer layer 150 formed on the nucleation layer 120 according to another embodiment of the present invention. In this embodiment, five intermediate superlattice structure layers 130 are inserted between arbitrary aluminum gallium nitride buffer layers 151-155 (including the lowest nucleation layer 120), so that there may be

A total of 6 kinds of insert combinations. Taking the figure as an example, between the nucleation layer 120 and the first aluminum gallium nitride buffer layer 151, between the first aluminum gallium nitride buffer layer 151 and the second aluminum gallium nitride buffer layer 152, and the second aluminum nitride Between the gallium buffer layer 152 and the third aluminum gallium nitride buffer layer 153, between the third aluminum gallium nitride buffer layer 153 and the fourth aluminum gallium nitride buffer layer 154, and between the fourth aluminum gallium nitride buffer layer 154 and An intermediate superlattice structure layer 130 is inserted between the fifth aluminum gallium nitride buffer layer 155. Other rules regarding the composition, aluminum atomic ratio, thickness, dopant concentration, and growth mode of the aluminum gallium nitride buffer layers 151-155 in the buffer layer 150 and the intermediate superlattice structure layer 130 are the same as those in the first embodiment.

[Example 6]

共1種的插入組合。以圖中為例，成核層120與第一氮化鋁鎵緩衝層151之間、第一氮化鋁鎵緩衝層151與第二氮化鋁鎵緩衝層152之間、第二氮化鋁鎵緩衝層152與第三氮化鋁鎵緩衝層153之間、第三氮化鋁鎵緩衝層153與第四氮化鋁鎵緩衝層154之間、第四氮化鋁鎵緩衝層154與第五氮化鋁鎵緩衝層155之間插入有中間超晶格結構層130，以及一中間超晶格結構層130位於第五氮化鋁鎵緩衝層155之上。其他關於緩衝層150中的氮化鋁鎵緩衝層151-155以及中間超晶格結構層130的成分、鋁原子比例、厚度、摻質濃度以及成長方式等規則與實施例1相同。 Please refer to FIG. 9, which illustrates the type of the buffer layer 150 formed on the nucleation layer 120 according to another embodiment of the present invention. In this embodiment, six intermediate superlattice structure layers 130 are inserted between arbitrary aluminum gallium nitride buffer layers 151-155 (including the lowest nucleation layer 120).

A total of 1 insert combination. Taking the figure as an example, between the nucleation layer 120 and the first aluminum gallium nitride buffer layer 151, between the first aluminum gallium nitride buffer layer 151 and the second aluminum gallium nitride buffer layer 152, and the second aluminum nitride Between the gallium buffer layer 152 and the third aluminum gallium nitride buffer layer 153, between the third aluminum gallium nitride buffer layer 153 and the fourth aluminum gallium nitride buffer layer 154, and the fourth aluminum gallium nitride buffer layer 154 and the fourth aluminum gallium nitride buffer layer 154 An intermediate superlattice structure layer 130 is inserted between the five aluminum gallium nitride buffer layers 155, and an intermediate superlattice structure layer 130 is located on the fifth aluminum gallium nitride buffer layer 155. Other rules regarding the composition, aluminum atomic ratio, thickness, dopant concentration, and growth mode of the aluminum gallium nitride buffer layers 151-155 in the buffer layer 150 and the intermediate superlattice structure layer 130 are the same as those in the first embodiment.

After completing the aforementioned buffer layer 150 composed of a plurality of aluminum gallium nitride buffer (graded) layers 151-155 and a plurality of intermediate superlattice structure layers 130, the subsequent growth of the gallium nitride epitaxial layer is next. . Referring to FIG. 10, first, a high resistance layer 160 is formed on the buffer layer 150, the composition of which can be gallium nitride, and the thickness is between 0.5-5um. The high-resistance layer 160 can be formed by MOCVD at a growth temperature of 1000 to 1200°C, and doped with carbon, iron, magnesium, zinc, etc. or a combination of dopants, and the dopant concentration is 1x10 ¹⁷ Ions/cm3. In the example of Embodiment 6, the uppermost middle superlattice structure layer 130 is between the fifth aluminum gallium nitride buffer layer 155 and the high resistance layer 160. The high-resistivity GaN high-resistance layer 160 can reduce the leakage current of GaN-based high electron mobility transistors (HEMTs) components, maintain the two-dimensional characteristics of the electron gas, increase the operating frequency of the components, suppress the current collapse effect, and Improve the breakdown voltage of HEMT components.

Referring again to Fig. 10, after the high resistance layer 160 is formed, an essential gallium nitride layer 170, that is, an undoped gallium nitride layer, is grown on the high resistance layer 160, with a thickness of 0.2~ Between 1um, it can be formed by MOCVD in an environment where the growth temperature is between 1000~1200℃. The intrinsic gallium nitride layer 170 can be used as the electron channel layer of the HEMT device. An electron supply layer 180 is formed on the intrinsic gallium nitride layer 170, and its composition can be undoped aluminum gallium nitride (Al _h Ga _1-h N), where 0.1<h<0.3, the thickness is medium At 10~40nm, the growth temperature is between 1000~1200°C, and it can be formed in an environment with a growth temperature of 1000~1200°C by MOCVD method. The heterogeneous junction between the electron supply layer of aluminum gallium nitride and the intrinsic gallium nitride layer 170 will form a low-resistance two-dimensional electron gas (2DEG) under the junction. The two-dimensional electron gas can make the device have a high Electron mobility can be used as a channel to conduct current.

Referring again to FIG. 10, after the electron supply layer 180 is formed, a cover layer 190 is finally formed on the electron supply layer 180, the composition of which can be doped gallium nitride or doped aluminum gallium nitride (Al _i Ga _{1 -i} N), where 0.1<i<0.3. When the material of the cover layer 190 is doped gallium nitride, its thickness ranges from about 1 to 20 nm, and dopants such as carbon, iron, magnesium, zinc, etc. or a combination thereof can be used. When the material of the covering layer 190 is doped aluminum gallium nitride, magnesium is selected as the doping element, and the magnesium doping concentration is about 1×10 ¹⁹ ions/cm ^ 3, and the thickness is between 10 nm and 150 nm. The covering layer 190 can be formed by MOCVD in an environment with a growth temperature of 1000 to 1200°C. The cover layer 190 mainly doped with gallium nitride or aluminum gallium nitride can help reduce the gate leakage current in the HEMT device and make it have a higher breakdown voltage. After the cover layer 190 is formed, the gate, source, and drain of the HEMT device will be fabricated on the cover layer 190 in the subsequent process. Since these parts are not the focus of this case, their description and illustrations will be omitted in the text and figures.

Looking at the above-mentioned embodiments of the present invention, the present invention proposes an improved gallium nitride epitaxial wafer with high quality and low loss characteristics, which is achieved by growing gallium nitride on a silicon-on-insulating wafer with multi-layer gradation. The changes in the superlattice structure of the layer and the multi-layer intermediate layer greatly buffer the stress brought by the growth of gallium nitride. The insulating oxide layer formed on the insulating layer on the back of the silicon wafer can also be used as a fixed layer to further compensate for the subsequent The stress generated during the epitaxy process avoids the conventional warpage problem of the wafer. In addition, the multilayer buffer structure allows the thickness of the entire epitaxial wafer to exceed 10um, and the breakdown voltage can exceed 1000 volts, which improves the efficiency of gallium nitride devices and is particularly suitable for making gallium nitride-based HEMT devices.

The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

110: Substrate (silicon wafer over insulating layer)

120: Nucleation layer

150: buffer layer

160: high resistance layer

170: Intrinsic GaN layer

180: electronic provision layer

190: Overlay

Claims (18)

A gallium nitride epitaxial wafer capable of reducing stress, comprising: a substrate; a nucleation layer located on the substrate; multiple aluminum gallium nitride buffer layers located on the nucleation layer; multiple intermediate superlattices Structure layer, part of the intermediate superlattice structure layer is located between the two aluminum gallium nitride buffer layers; a high resistance layer is located on the uppermost aluminum gallium nitride buffer layer; an intrinsic nitride A gallium layer located on the high resistance layer; an electron supply layer located on the intrinsic gallium nitride layer, wherein the intrinsic gallium nitride layer is located between the high resistance layer and the electron supply layer; and a The covering layer is located on the electron supply layer. According to the stress-reducing gallium nitride epitaxial wafer described in item 1 of the scope of patent application, one of the intermediate superlattice structure layers is located between the nucleation layer and the lowermost aluminum gallium nitride buffer layer. According to the stress-reducing gallium nitride epitaxy wafer described in item 1 of the scope of patent application, one of the intermediate superlattice structure layers is located between the high resistance layer and the uppermost aluminum gallium nitride buffer layer. The stress-reducing gallium nitride epitaxial wafer according to the first item of the scope of patent application, wherein the substrate is a silicon-on-insulating wafer, including a support wafer, an insulating oxide layer on both sides of the support wafer, and a The device wafer is located on one of the insulating oxide layers. According to the 4th item of the scope of patent application, the stress-reducing gallium nitride epitaxy wafer, in which The material of the support wafer and the device wafer is silicon wafer, silicon carbide wafer or sapphire wafer. The stress-reducing gallium nitride epitaxy wafer according to the first item of the patent application, wherein the nucleation layer includes a low-temperature aluminum nitride layer on the substrate and a high-temperature aluminum nitride layer on the low-temperature aluminum nitride layer superior. According to the stress-reducing gallium nitride epitaxy wafer described in item 1 of the scope of patent application, the aluminum atomic ratio of each aluminum gallium nitride buffer layer is different, and the farther away from the substrate, the aluminum of the aluminum gallium nitride buffer layer The smaller the atomic ratio. According to the stress-reducing gallium nitride epitaxy wafer described in item 7 of the scope of patent application, each of the aluminum gallium nitride buffer layers is a graded layer and the aluminum atom ratio is smaller the farther away from the substrate. According to the stress-reducing gallium nitride epitaxy wafer described in item 1 of the scope of patent application, the thickness of each aluminum gallium nitride buffer layer is different, and the thickness of the aluminum gallium nitride buffer layer farther from the substrate is greater . The stress-reducing gallium nitride epitaxial wafer according to the first item of the patent application, wherein the plurality of aluminum gallium nitride buffer layers are doped aluminum gallium nitride layers with dopants, and the dopants are selected from the following groups Group or combination: carbon, iron, magnesium and zinc. According to the stress-reducing gallium nitride epitaxy wafer described in item 10 of the scope of patent application, the concentration of the dopant in each of the aluminum gallium nitride buffer layers is different, and the aluminum gallium nitride buffer layer farther from the substrate The greater the concentration of this dopant. According to the stress-reducing gallium nitride epitaxial wafer described in the first item of the patent application, each of the intermediate superlattice structure layers includes a plurality of superlattice groups, and each of the superlattice groups includes a plurality of supercrystals Lattice pairs, each of the superlattice pairs includes a first superlattice layer and a second superlattice layer located on the first superlattice layer. The stress-reducing gallium nitride epitaxial wafer according to item 12 of the scope of patent application, wherein the material of the first superlattice layer and the second superlattice layer is aluminum gallium nitride, and the first superlattice The aluminum atom concentration of the layer is different from the aluminum atom ratio of the second superlattice layer. According to the stress-reducing gallium nitride epitaxial wafer described in item 13 of the scope of patent application, the aluminum atom ratio of the first superlattice layer is the same as the aluminum atom ratio of the closest aluminum gallium nitride buffer layer below, The proportion of aluminum atoms of the second superlattice layer is the same as the proportion of aluminum atoms of the aluminum gallium nitride buffer layer closest above. According to the stress-reducing gallium nitride epitaxial wafer described in item 12 of the scope of patent application, the thickness of the first superlattice layer in each superlattice group is different, and the farther the superlattice is from the substrate The smaller the thickness of the first superlattice layer in the group, the greater the thickness of the second superlattice layer in the superlattice group that is farther from the substrate. According to the stress-reducing gallium nitride epitaxial wafer described in item 1 of the scope of patent application, the material of the high resistance layer is doped gallium nitride. According to the stress-reducing gallium nitride epitaxy wafer described in item 1 of the scope of patent application, the material of the electron supply layer is aluminum gallium nitride. According to the stress-reducing gallium nitride epitaxy wafer described in item 1 of the scope of patent application, the material of the cover layer is doped gallium nitride or doped aluminum gallium nitride.

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