TWI740986B - Printed circuit boards including drive circuits, and related semiconductor devices - Google Patents

Abstract

Printed circuit boards including drive circuits and related semiconductor devices are disclosed. Semiconductor devices are provided, the semiconductor device includes a base substrate, a timing controller chip on the base substrate, first and second drive circuits on the base substrate, and a plurality of signal lines on the base substrate that connect the timing controller chip to the first and second drive circuits. The plurality of signal lines are each at the same vertical level and are horizontally spaced apart from each other. Related printed circuit boards are also provided.

Description

Printed circuit board containing drive circuit and related semiconductor device Set

The present disclosure relates to printed circuit boards and semiconductor devices containing them, which can be used with display devices, for example.

[Cross reference of related applications]

This disclosure claims the rights and interests of U.S. Provisional Patent Application No. 62/366,357 filed on July 25, 2016, and claims the priority of Korean Patent Application No. 10-2016-0134491 filed on October 17, 2016, so The entire contents of the US provisional patent application and the Korean patent application are hereby incorporated by reference.

The display system may include a display device for displaying images and a host for outputting multiple control signals and image data of each frame. The display device includes a display panel for displaying images, a gate driving unit and a data driving unit for driving the display panel. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the gate lines and the data lines. The gate line receives the gate signal from the gate driving unit. The data line receives the data signal from the data driving unit. Respond to With the gate signal provided through the gate line, the pixel receives the data signal through the data line. The pixel displays the gray scale corresponding to the data voltage. Then the image is displayed.

The display system can use semiconductor devices, and semiconductor devices can be beneficial in the electronics industry because of their small size, multi-function, and/or low manufacturing cost. Semiconductor devices can be classified into semiconductor memory devices that store logic data, semiconductor logic devices that process operations of logic data, and hybrid semiconductor devices that have both memory devices and logic devices. With the advanced development of the electronics industry, semiconductor devices have been increasingly used for high integration. For example, semiconductor devices have been increasingly requested to have high reliability, high speed, and/or multi-functions. Semiconductor devices can be complex and highly integrated to meet these requested characteristics.

Various embodiments of the inventive concept provide a printed circuit board having a single wiring layer and a semiconductor device including the printed circuit board.

According to various embodiments herein, a semiconductor device may include a base substrate. The semiconductor device may include a timing controller chip on the base substrate. The semiconductor device may include a first driving circuit chip and a second driving circuit chip on the base substrate. In addition, the semiconductor device may include a plurality of signal lines on the base substrate. The multiple signal lines may be positioned at the same vertical horizontal height and may be horizontally spaced apart from each other. The plurality of signal lines may include a first data signal line and a first control signal line electrically connecting the timing controller chip and the first driving circuit chip. The plurality of signal lines may also include a second data signal line and a second control signal line electrically connecting the timing controller chip and the second driving circuit chip.

According to various embodiments herein, a printed circuit board may include a base substrate including: a first area including a timing controller chip, a second area including a first driver circuit chip, and a second driver circuit chip The third district. The printed circuit board may include a first data signal pad, a second data signal pad, a first control signal pad, and a second control signal pad located on the first area. The printed circuit board may include data signal pads and control signal pads on the second area. The printed circuit board may include data signal pads and control signal pads on the third area. The printed circuit board may include: a first data signal line connecting the first data signal pad in the first area to the data signal pad in the second area. The printed circuit board may include: a first control signal line that connects the first control signal pad of the first area to the control signal pad of the second area. The printed circuit board may include: a second data signal line connecting the second data signal pad in the first area to the data signal pad in the third area. In addition, the printed circuit board may include: a second control signal line that connects the second control signal pad of the first area to the control signal pad of the third area. The first data signal line and the second data signal line and the first control signal line and the second control signal line may be located at the same vertical horizontal height and may be horizontally spaced apart from each other.

According to various embodiments herein, a semiconductor device may include a controller. The semiconductor device may include a first driving circuit and a second driving circuit. The first driving circuit and the second driving circuit are configured to drive a display panel and are respectively connected by a plurality of first signal lines and a plurality of second driving circuits. The signal line is connected to the controller. In addition, the semiconductor device may include a thin film including the plurality of first signal lines and the plurality of second signal lines, the controller, and the first driving circuit and the second driving circuit thereon . Each of the plurality of first signal lines and the plurality of second signals Each of the number lines may be in a single layer of non-overlapping signal lines on the film, so that the plurality of first signal lines and the plurality of second signal lines are non-overlapping on the film.

110: display panel

112: display substrate

114: display device layer

116: Sealing layer

120: printed circuit board

120a: first surface

120b: second surface

130: Main drive substrate

140: first substrate

143: The first action area

150: second substrate

153: The second area of action

BA: non-display area

BP: Bonding pad

BS: base substrate

CPa, CPb, CPc: control signal pad

CPa1: The first control signal pad

CPa2: The second control signal pad

CPb1: The first control signal pad

CPb2: The second control signal pad

CPc1: The first control signal pad

CPc2: The first control signal pad

CR1: first intersection

CR2: second intersection

CSL1: The first control signal line

CSL2: The second control signal line

CSLa, CSLb: control signal line

D1: First direction

D2: second direction

DA1: the first display area

DA2: second display area

DI1: The first driver circuit chip

DI2: The second drive circuit chip

DPa1: The first data signal pad

DPa2: The second data signal pad

DPa, DPb, DPc: Data signal pad

DSL1: The first data signal line

DSL2: The second data signal line

DSLa, DSLb: data signal line

IL1: first insulating layer

IL2: second insulating layer

IM: Interconnecting member

IML1: the first wiring layer

IML2: second wiring layer

IP1: the first input pad

IP2: second input pad

IP3: third input pad

IP4: Fourth input pad

LINE1, LINE2, LINE3, LINE4, LINE5: conductive thread

M: section

MA: installation area

OP1: The first output pad

OP2: The second output pad

OP3: Third output pad

OP4: Fourth output pad

OP5: Fifth output pad

OP6: The sixth output pad

OP7: seventh output pad

OP8: Eighth output pad

OP9: Ninth output pad

PAD1, PAD2, PAD3, PAD4, PAD5: pad

PD1: the first pad area

PD2: The second pad area

PX: pixel

RC1: The first chip area

RC2: Second chip area

RC3: The third chip area

RG1: District 1

RG2: District 2

RG3: District 3

RG4: District 4

RG5: District 5

SL1: the first signal line

SL2: second signal line

SL3: The third signal line

SL4: The fourth signal line

SL5: Fifth signal line

SL6: The sixth signal line

SL7: seventh signal line

SL8: Eighth signal line

SL9: Ninth signal line

SL10: Tenth signal line

SL11: The eleventh signal line

SP: sub pixel

SPa1: signal pad

SPb1, SPc1: the first signal pad

SPb2, SPc2: second signal pad

SPb3, SPc3: third signal pad

SPb4, SPc4: the fourth signal pad

TC: timing controller chip

FIG. 1 is a plan view illustrating a display device according to an example embodiment of the inventive concept.

Fig. 2 is a cross-sectional view taken along line II' of Fig. 1.

3 is a plan view illustrating a timing controller chip, a first driving circuit chip, and a second driving circuit chip mounted on a flexible printed circuit board according to an exemplary embodiment of the inventive concept.

FIG. 4 is a cross-sectional view taken along the line II-II' of FIG. 3. FIG.

Fig. 5 is a cross-sectional view taken along line III-III' of Fig. 3.

FIG. 6 is an enlarged plan view illustrating a section M of FIG. 3 according to an example embodiment of the inventive concept.

7 is a plan view illustrating a timing controller chip, a first driving circuit chip, and a second driving circuit chip mounted on a flexible printed circuit board according to a comparative embodiment.

8 is a plan view illustrating a timing controller chip, a first driving circuit chip, and a second driving circuit chip mounted on a flexible printed circuit board according to an exemplary embodiment of the inventive concept.

FIG. 1 is a plan view illustrating a display device according to an example embodiment of the inventive concept, and FIG. 2 is a cross-sectional view taken along the line II′ of FIG. 1.

1 and 2, the display panel 110, the flexible printed circuit board 120, and the main driving substrate 130 may be included in a display device according to example embodiments of the inventive concept. The flexible printed circuit board 120 may be disposed between the display panel 110 and the main driving substrate 130 and may be electrically connected to the display panel 110 and the main driving substrate 130.

When the driving signal is applied to the plurality of pixels PX, the display panel 110 can display an image. Each of the pixels PX may include a sub-pixel SP. For example, three sub-pixels SP may constitute one pixel PX. In other examples, one pixel PX may include two, four, or more than four sub-pixels SP.

The sub-pixels SP may be arranged in a matrix form along the first direction D1 and the second direction D2 that cross each other. The sub-pixel SP may display at least one of primary colors such as red, green, and blue. The colors displayed by the sub-pixels SP are not limited to red, green, and blue. In fact, in addition to or instead of red, green, and blue, the sub-pixel SP can also display various colors, for example, secondary primary colors such as white, yellow, cyan, and magenta.

According to the type (ie, type) of the pixel PX, the display panel 110 can be classified into a liquid crystal display panel, an organic light emitting display panel, an electrowetting display panel, and the like. For example, in some embodiments, the display panel 110 may be an organic light emitting display panel.

The display panel 110 may include a first display area DA1 where a plurality of pixels PX are disposed, and a second display area DA2 where another plurality of pixels PX are disposed. The first display area DA1 and the second display area DA2 may be linearly arranged in the second direction D2. The display panel 110 may further include a non-display area BA surrounding the first display area DA1 and the second display area DA2 and a mounting coupled to the flexible printed circuit board 120 Regional MA. In some embodiments, the non-display area BA may be omitted. Furthermore, in some embodiments, the mounting area MA may be part of the non-display area BA.

As shown in FIG. 2, the display panel 110 may include a display substrate 112, a display device layer 114 on the display substrate 112, and a sealing layer 116 on the display device layer 114. The display device layer 114 may include an insulating layer, a functional layer, and a conductive layer on the substrate. The conductive layer may include gate lines, data lines, and other signal lines.

The display device layer 114 may include an insulating layer, a functional layer, and a conductive layer constituting a plurality of pixels PX. The functional layer of the display device layer 114 may include an organic light-emitting layer. The sealing layer 116 may be disposed on the display device layer 114 and protect the display device layer. In some embodiments, the sealing layer 116 may also cover the sides of the display device layer 114 as appropriate.

The non-display area BA may include a black matrix that blocks light thereon. The non-display area BA may include a gate driving circuit for supplying gate signals to the plurality of pixels PX thereon. The mounting area MA may include a pad area thereon for receiving signals provided from the flexible printed circuit board 120.

The flexible printed circuit board 120 may have two facing (ie, opposite) sides extending in the first direction D1 and two other facing/opposing sides extending in the second direction D2. The flexible printed circuit board 120 may include a first surface 120a and a second surface 120b facing the first surface 120a/opposite the first surface 120a. The flexible printed circuit board 120 may include a first pad area PD1 and a second pad area PD2. The first pad area PD1 may be connected to the pad area of the mounting area MA, and the second pad area PD2 may be connected to the pad area of the main driving substrate 130.

The timing controller chip TC, the first driving circuit chip DI1 and the second driving circuit chip DI2 can be mounted on the first surface 120a of the flexible printed circuit board 120 superior. In some embodiments, the chip-on-film structure may be formed/provided by the flexible printed circuit board 120 and the timing controller chip TC attached thereto, the first driving circuit chip DI1, and the second driving circuit chip DI2. The timing controller chip TC, the first driving circuit chip DI1, and the second driving circuit chip DI2 may be electrically connected to each other via signal lines at the upper portion of the flexible printed circuit board 120.

Each of the first driving circuit chip DI1 and the second driving circuit chip DI2 may include a data driving circuit. The first driving circuit chip DI1 can convert the driving signal output from the timing controller chip TC into a data voltage, and the pixels PX in the first display area DA1 can receive the data voltage from the first driving circuit chip DI1. The second driving circuit chip DI2 can convert the driving signal output from the timing controller chip TC into a data voltage, and the pixels PX in the second display area DA2 can receive the data voltage from the second driving circuit chip DI2.

The main driving substrate 130 may include a pad area connected to the second pad area PD2 of the flexible printed circuit board 120. The main driving substrate 130 can provide image data, control signals, power supply voltage, etc. to the display panel 110 or the flexible printed circuit board 120. The main driving substrate 130 may include active components and passive components.

3 is a plan view illustrating a timing controller chip, a first driving circuit chip, and a second driving circuit chip mounted on a flexible printed circuit board according to an exemplary embodiment of the inventive concept. FIG. 4 is a cross-sectional view taken along the line II-II' of FIG. 3. FIG. Fig. 5 is a cross-sectional view taken along line III-III' of Fig. 3.

3, 4, and 5, the timing controller chip TC, the first driving circuit chip DI1, and the second driving circuit chip DI2 can be mounted on the first surface 120a of the flexible printed circuit board 120. In some embodiments, the first driving circuit chip DI1 and the second driving circuit chip DI2 may be the same chip. First drive circuit Each of the chip DI1 and the second driving circuit chip DI2 may be spaced apart from the timing controller chip TC in the first direction D1. The first driving circuit die DI1 and the second driving circuit die DI2 may be spaced apart from each other in the second direction D2. The first driving circuit chip DI1 and the second driving circuit chip DI2 may be adjacent to the first pad area PD1, and the timing controller chip TC may be adjacent to the second pad area PD2.

The flexible printed circuit board 120 may include a first chip area RC1 where the timing controller chip TC is positioned, a second chip area RC2 where the first driving circuit chip DI1 is positioned, and a third chip where the second driving circuit chip DI2 is positioned. District RC3. The flexible printed circuit board 120 may further include a first area RG1 to a fifth area RG5. The first to fifth regions RG1 to RG5 and the first to third wafer regions RC1 to RC3 may not overlap.

The second region RG2 may extend from the second pad region PD2 toward the second chip region RC2. The third region RG3 may extend from the second pad region PD2 toward the first chip region RC1. The third region RG3 can be inserted between the second region RG2 and the fourth region RG4. The fourth region RG4 may extend from the second pad region PD2 toward the third chip region RC3. The fifth area RG5 may be inserted between the first chip area RC1 to the third chip area RC3. That is, the fifth area RG5 may extend between the first chip area RC1 to the third chip area RC3 and in the first direction D1 and the second direction D2. In addition, the fifth area RG5 may be inserted between the second area RG2 and the fourth area RG4. The first area RG1 may be the remaining area outside the second area RG2 to the fifth area RG5.

The first input pad IP1 to the fourth input pad IP4 may be disposed on the first surface 120a of the first pad region PD1. The first output pad OP1 to the ninth output pad OP9 may be disposed on the first surface 120a of the second pad region PD2. The first output pad OP1 to the ninth output pad OP9 can receive output from the main driving substrate 130 discussed with reference to FIGS. 1 and 2 The first to fourth input pads IP1 to IP4 can input signals to the display panel 110 discussed with reference to FIGS. 1 and 2.

The first area RG1 may include the first input pad IP1 to the fourth input pad IP4 and the first output pad OP1 and the ninth output pad OP9 thereon. The second region RG2 may include the second output pad OP2 to the fourth output pad OP4 thereon. The third area RG3 may include a fifth output pad OP5 thereon. The fourth region RG4 may include the sixth output pad OP6 to the eighth output pad OP8 thereon.

The first surface 120a of the first chip region RC1 may include a first control signal pad CPa1, a second control signal pad CPa2, a first data signal pad DPa1, a second data signal pad DPa2, and a signal pad SPa1 thereon. The first control signal pad CPa1 and the second control signal pad CPa2 and the first data signal pad DPa1 and the second data signal pad DPa2 may be arranged in the second direction D2. The first data signal pad DPa1 and the second data signal pad DPa2 can be positioned between the first control signal pad CPa1 and the second control signal pad CPa2.

The first surface 120a of the second chip area RC2 may include a first control signal pad CPb1, a second control signal pad CPb2, a data signal pad DPb, and first to fourth signal pads SPb1 to SPb4 thereon. The first control signal pad CPb1 and the second control signal pad CPb2, the data signal pad DPb, and the first to third signal pads SPb1 to SPb3 may be arranged in the second direction D2. The second signal pad SPb2 and the data signal pad DPb may be positioned between the first control signal pad CPb1 and the second control signal pad CPb2. The second wafer region RC2 may have a first side and a second side facing each other (ie, opposite to each other) and extending in the first direction D1. The first signal pad SPb1 may be adjacent to the first side, and the third signal pad SPb3 may be adjacent to the second side.

The first surface 120a of the third chip region RC3 may include a first control surface thereon. The signal pad CPc1, the second control signal pad CPc2, the data signal pad DPc, and the first signal pad SPc1 to the fourth signal pad SPc4 are controlled. The first control signal pad CPc1 and the second control signal pad CPc2 of the third chip area RC3, the data signal pad DPc, and the first signal pads SPc1 to the fourth signal pad SPc4 can be the same as the first control signal pad CPb1 of the second chip area RC2 It is the same as the second control signal pad CPb2, the data signal pad DPb, and the first signal pad SPb1 to the fourth signal pad SPb4. In more detail, the positions of the first control signal pad CPc1 and the second control signal pad CPc2, the data signal pad DPc, and the first signal pad SPc1 to the fourth signal pad SPc4 of the third chip area RC3 may be the same as those of the second chip area RC2. The first control signal pad CPb1 and the second control signal pad CPb2, the data signal pad DPb, and the first signal pad SPb1 to the fourth signal pad SPb4 are the same. This can be because the first driving circuit chip DI1 mounted on the second chip area RC2 is the same as the second driving circuit chip DI2 mounted on the third chip area RC3 (ie, it is a duplicate).

The first surface 120a of the first region RG1 may include a first signal line SL1, a fifth signal line SL5, a seventh signal line SL7, and an eleventh signal line SL11 thereon. The first signal line SL1 can connect the first output pad OP1 and the first input pad IP1. The fifth signal line SL5 can connect the second input pad IP2 and the fourth signal pad SPb4 of the second chip area RC2. The seventh signal line SL7 can connect the third input pad IP3 and the fourth signal pad SPc4 of the third chip area RC3. The eleventh signal line SL11 can connect the ninth output pad OP9 and the fourth input pad IP4.

The first surface 120a of the second region RG2 may include the second signal line SL2, the third signal line SL3, and the fourth signal line SL4 thereon. The second signal line SL2 can connect the second output pad OP2 and the first signal pad SPb1 of the second chip area RC2. The third signal line SL3 can connect the third output pad OP3 and the third signal pad SPb3 of the second chip area RC2. The fourth signal line SL4 can connect the fourth output pad OP4 and the second chip area The second signal pad SPb2 of RC2. Each of the third signal line SL3 and the fourth signal line SL4 may include a portion extending in the second direction D2 on the second chip region RC2. Therefore, the third signal line SL3 may be connected to the third signal pad SPb3 adjacent to the fifth region RG5 via the extended portion thereof. Similarly, the fourth signal line SL4 may be connected to the second signal pad SPb2 adjacent to the fifth region RG5 via its extended portion.

The first surface 120a of the third region RG3 may include the sixth signal line SL6 thereon. The sixth signal line SL6 can connect the fifth output pad OP5 and the signal pad SPa1 of the first chip area RC1.

The first surface 120a of the fourth region RG4 may include an eighth signal line SL8, a ninth signal line SL9, and a tenth signal line SL10 thereon. The eighth signal line SL8 can connect the sixth output pad OP6 and the second signal pad SPc2 of the third chip area RC3. The ninth signal line SL9 can connect the seventh output pad OP7 and the first signal pad SPc1 of the third chip area RC3. The tenth signal line SL10 can connect the eighth output pad OP8 and the third signal pad SPc3 of the third chip area RC3.

The signal applied to the eighth signal line SL8 and the signal applied to the fourth signal line SL4 may be the same or the same kind/type. The signal applied to the ninth signal line SL9 and the signal applied to the second signal line SL2 may be the same or the same kind/type. The signal applied to the tenth signal line SL10 and the signal applied to the third signal line SL3 may be the same or the same kind/type. In other words, the signals applied to the first signal pads SPb1 and SPc1 may be the same or the same type/type, and the signals applied to the second signal pads SPb2 and SPc2 may be the same or the same type/type, and are applied to the third signal pad SPb3 The signals of SPc3 and SPc3 can be the same or the same kind/type. Therefore, the same (ie, the same/duplicate) first driving circuit chip DI1 and the second driving circuit chip DI2 can be mounted on the second chip area RC2 and the third chip area RC3, respectively.

Various kinds/types of signals may be transmitted via the first signal line SL1 to the eleventh signal line SL11. The type/type of the transmitted signal is not particularly limited. In detail, the first signal line SL1 to the fourth signal line SL4, the sixth signal line SL6, and the eighth signal line SL8 to the eleventh signal line SL11 can be provided from the main driving substrate 130 discussed with reference to FIGS. 1 and 2. The output system signal. The fifth signal line SL5 and the seventh signal line SL7 can be provided with signals output from the first driving circuit chip DI1 and the second driving circuit chip DI2, respectively.

The first surface 120a of the fifth region RG5 may include a first control signal line CSL1, a second control signal line CSL2, a first data signal line DSL1, and a second data signal line DSL2 thereon. The first control signal line CSL1 can connect the first control signal pad CPa1 of the first chip area RC1 and the first control signal pad CPb1 of the second chip area RC2. The first data signal line DSL1 can connect the first data signal pad DPa1 of the first chip area RC1 and the data signal pad DPb of the second chip area RC2. The second data signal line DSL2 can connect the second data signal pad DPa2 of the first chip area RC1 and the data signal pad DPc of the third chip area RC3. The second control signal line CSL2 can connect the second control signal pad CPa2 of the first chip area RC1 and the second control signal pad CPc2 of the third chip area RC3. In contrast, the second control signal pad CPb2 of the second chip area RC2 and the first control signal pad CPc1 of the third chip area RC3 may not be connected to (that is, may not be tethered to or otherwise not included). Any signal lines outside the first driving circuit chip DI1 and the second driving circuit chip DI2.

The first control signal line CSL1 can transmit the data control signal output from the timing controller chip TC to the first driving circuit chip DI1. The first data signal line DSL1 can transmit the image data signal output from the timing controller chip TC to the first driving circuit chip DI1. The second control signal line CSL2 can connect from the timing controller The data control signal output by the chip TC is transmitted to the second driving circuit chip DI2. The second data signal line DSL2 can transmit the image data signal output from the timing controller chip TC to the second driving circuit chip DI2.

For example, the data control signal transmitted through the first control signal line CSL1 and the second control signal line CSL2 may be a configurable setting value or a DFT setting value. In this situation, transistor-transistor logic (TTL) signal transmission can be used to transmit data control signals via the first control signal line CSL1 and the second control signal line CSL2. High speed differential signal transmission can be used to transmit image data signals via the first data signal line DSL1 and the second data signal line DSL2.

As shown in FIGS. 4 and 5, the flexible printed circuit board 120 may include a base substrate BS, a first insulating layer IL1 on the top surface of the base substrate BS, and a second insulating layer IL2 on the bottom surface of the base substrate BS . The top surface of the base substrate BS may be adjacent to the first surface 120 a of the flexible printed circuit board 120, and the bottom surface of the base substrate BS may be adjacent to the second surface 120 b of the flexible printed circuit board 120. For example, the base substrate BS may be a flexible film substrate, and each of the first insulating layer IL1 and the second insulating layer IL2 may be a solder resist.

The top surface of the base substrate BS may include thereon the plurality of signal lines SL1 to SL11, CSL1, CSL2, DSL1, and DSL2 discussed above. The signal lines SL1 to SL11, CSL1, CSL2, DSL1, and DSL2 may constitute/provide a single wiring layer on the base substrate BS. In other words, the signal lines SL1 to SL11, CSL1, CSL2, DSL1, and DSL2 can be positioned at the same vertical level (see FIG. 4 and FIG. 5) and spaced apart from each other horizontally (see FIG. 3). In this configuration, even if positioned at the same vertical horizontal height, the signal lines SL1 to SL11, CSL1, CSL2, and DSL1 And DSL2 may not cross each other. For example, the signal lines SL1 to SL11, CSL1, CSL2, DSL1, and DSL2 can be formed by printing a conductive layer on the top surface of the base substrate BS. The first insulating layer IL1 may cover the signal lines SL1 to SL11, CSL1, CSL2, DSL1, and DSL2.

Each of the following can be placed on the correspondingly connected signal lines SL2 to SL10, CSL1, CSL2, DSL1, and DSL2: signal pads SPa1, CPa1, CPa2, DPa1, and DPa2 of the first chip area RC1; signal pads of the second chip area RC2 SPb1 to SPb4, CPb1, CPb2, and DPb; and the signal pads SPc1 to SPc4, CPc1, CPc2, and DPc of the third chip area RC3. The signal pad may protrude above the first insulating layer IL1.

As shown in FIG. 4, the timing controller chip TC on the first chip area RC1 may include a first substrate 140 having a first active area 143, a first wiring layer IML1 on the first active area 143, and a first wiring layer Bonding pad BP on IML1. The first active area 143 may include a plurality of transistors formed on the first substrate 140 (which may be a semiconductor substrate). The first wiring layer IML1 may include an interlayer dielectric layer, a metal line formed in each of the interlayer dielectric layers, and a via hole formed in each of the interlayer dielectric layers. The bonding pad BP may be electrically connected to the first active region 143 via the first wiring layer IML1.

The bonding pad BP of the timing controller chip TC may vertically overlap the signal pads SPa1, CPa1, CPa2, DPa1, and DPa2 of the first chip area RC1. The interconnection member IM can be inserted between the bonding pad BP of the timing controller chip TC and the signal pads SPa1, CPa1, CPa2, DPa1, and DPa2 of the first chip area RC1, and connects the bonding pad BP of the timing controller chip TC and the first chip area RC1. The signal pads SPa1, CPa1, CPa2, DPa1, and DPa2 of a chip area RC1. For example, in the interconnection component IM Each of may include bumps (e.g., solder bumps).

The first wiring layer IML1 may electrically connect the bonding pad BP (which overlaps with the first control signal pad CPa1) and the bonding pad BP (which overlaps with the second control signal pad CPa2). That is, the first wiring layer IML1 can electrically connect the first control signal pad CPa1 and the second control signal pad CPa2 (which are signal pads of the same type/type) to each other. Therefore, there is no need to further arrange a signal line for connecting the first control signal line CSL1 and the second control signal line CSL2 on the flexible printed circuit board 120. The first wiring layer IML1 can electrically connect the bonding pad BP (which overlaps with the first data signal pad DPa1) and the bonding pad BP (which overlaps with the second data signal pad DPa2). That is, the first wiring layer IML1 can electrically connect the first data signal pad DPa1 and the second data signal pad DPa2 (which are signal pads of the same type/type) to each other. Therefore, it is not necessary to further arrange a signal line for connecting the first data signal line DSL1 and the second data signal line DSL2 on the flexible printed circuit board 120.

As shown in FIG. 5, the first driver circuit die DI1 on the second die region RC2 may include a second substrate 150 having a second active region 153, a second wiring layer IML2 on the second active region 153, and a second wiring layer IML2 on the second active region 153. The bonding pad BP on the second wiring layer IML2. The second active area 153 may include a plurality of transistors formed on the second substrate 150 (which is a semiconductor substrate). The second wiring layer IML2 may include an interlayer dielectric layer, a metal line formed in each of the interlayer dielectric layers, and a via hole formed in each of the interlayer dielectric layers. The bonding pad BP may be electrically connected to the second active region 153 via the second wiring layer IML2.

The bonding pad BP of the first driving circuit chip DI1 may vertically overlap the signal pads SPb1 to SPb4, CPb1, CPb2, and DPb of the second chip area RC2. The interconnection member IM can be inserted into the bonding pad BP of the first driving circuit chip DI1 and the second chip The signal pads SPb1 to SPb4, CPb1, CPb2, and DPb of the region RC2 are connected to the bonding pads BP of the first driving circuit chip DI1 and the signal pads SPb1 to SPb4, CPb1, CPb2, and DPb of the second chip region RC2.

The second wiring layer IML2 may electrically connect the bonding pad BP (which overlaps with the first control signal pad CPb1) and the bonding pad BP (which overlaps with the second control signal pad CPb2). Therefore, although the first control signal line CSL1 is directly connected to only one of the first control signal pad CPb1 and the second control signal pad CPb2, the first driving circuit chip DI1 can operate normally. In some embodiments, the first control signal line CSL1 can transmit a signal to the first driving circuit chip DI1 via the first control signal pad CPb1. The second control signal pad CPb2 may not be connected to (for example, may not be bolted to or otherwise not included) any signal line outside the first driving circuit chip DI1.

The second driving circuit die DI2 on the third die area RC3 may be the same as the first driving circuit die DI1 discussed above (for example, a duplicate thereof). Therefore, a detailed description of the second driving circuit chip DI2 may be omitted. Even if the second control signal line CSL2 is directly connected to only one of the first control signal pad CPc1 and the second control signal pad CPc2, the second driving circuit chip DI2 can also operate normally. Different from the first control signal line CSL1 connected to the first driving circuit chip DI1 discussed above, the second control signal line CSL2 can transmit signals to the second driving circuit chip DI2 via the second control signal pad CPc2. The first control signal pad CPc1 may not be connected to (for example, may not be included) any signal line outside the second driving circuit chip DI2.

According to example embodiments of the inventive concept, each of the second chip area RC2 and the third chip area RC3 may include two control signal pads and one data signal pad thereon. Alternatively, in some embodiments, each of the second chip area RC2 and the third chip area RC3 may include one control signal pad and two data signals thereon. No. pad. In this situation, one data signal line can be connected to the first data signal pad of the second chip area RC2, and another data signal line can be connected to the second data signal pad of the third chip area RC3.

FIG. 6 is an enlarged plan view illustrating a section M of FIG. 3 according to an example embodiment of the inventive concept.

3 and 6, each of the signal lines SL1 to SL11, CSL1, CSL2, DSL1, and DSL2 may be composed of a single conductive line or a conductive line group including a plurality of conductive lines. For example, the second control signal line CSL2 may include a plurality of conductive lines LINE1 to LINE5. In this situation, the conductive lines LINE1 to LINE5 can be arranged adjacently to form a single group (that is, the second control signal line CSL2).

Each of the signal pads SPa1, CPa1, CPa2, DPa1, DPa2, SPb1 to SPb4, CPb1, CPb2, DPb, SPc1 to SPc4, CPc1, CPc2, and DPc may be composed of a single pad or a pad group including a plurality of pads. Each of the signal pads SPa1, CPa1, CPa2, DPa1, DPa2, SPb1 to SPb4, CPb1, CPb2, DPb, SPc1 to SPc4, CPc1, CPc2, and DPc may include a conductive line corresponding to the signal line to which it is connected. For example, the second control signal pad CPc2 connected to the second control signal line CSL2 may include a plurality of pads PAD1 to PAD5 corresponding to the conductive lines LINE1 to LINE5, respectively.

Therefore, example embodiments of the inventive concept are not limited to the number (ie, the number) of signal lines and signal pads shown in FIG. 3, and the illustrated signal lines and signal pads are shown for the purpose of example.

7 is a plan view illustrating a timing controller chip, a first driving circuit chip, and a second driving circuit chip mounted on a flexible printed circuit board according to a comparative embodiment. In the following comparative examples, the discussion with reference to Fig. 3 to Fig. 5 will be omitted. The content described repeats the detailed description of the technical features, and the differences can be discussed in detail.

Referring to FIG. 7, the first surface 120a of the first chip region RC1 may include a control signal pad CPa, a data signal pad DPa, and a signal pad SPa1 thereon. Unlike the first chip area RC1 shown in FIGS. 3, 4, and 5 above, the second control signal pad CPa2 and the second data signal pad DPa2 can be omitted.

The first surface 120a of the second chip area RC2 may include a control signal pad CPb, a data signal pad DPb, and first to fourth signal pads SPb1 to SPb4 thereon. Unlike the second chip area RC2 shown in FIGS. 3, 4, and 5 above, the second control signal pad CPb2 may be omitted. The first surface 120a of the third chip area RC3 may include a control signal pad CPc, a data signal pad DPc, and first to fourth signal pads SPc1 to SPc4 thereon. Unlike the third chip area RC3 shown in FIGS. 3, 4, and 5 above, the second control signal pad CPc2 can be omitted.

The first surface 120a of the fifth region RG5 may include control signal lines CSLa/CSLb and data signal lines DSLa/DSLb thereon. The control signal lines CSLa/CSLb can respectively connect the control signal pads CPa of the first chip area RC1 and the control signal pads CPb and CPc of the second chip area RC2 and the third chip area RC3. The control signal line CSLa/CSLb may include a first section of the control signal line CSLa and a second section of the control signal line CSLb. The control signal line CSLa of the first section and the control signal line CSLb of the second section can extend in the first direction D1, so that the control signal line CSLa of the first section can be connected to the control signal pad of the second chip region RC2 CPb, and the control signal line CSLb of the second section can be connected to the control signal pad CPc of the third chip area RC3.

The data signal lines DSLa/DSLb can respectively connect the data signal pads DPa of the first chip area RC1 and the data signal pads DPb and DPc of the second chip area RC2 and the third chip area RC3. The data signal line DSLa/DSLb can contain the data of the first section The signal line DSLa and the data signal line DSLb of the second section. The data signal line DSLa of the first section and the data signal line DSLb of the second section can extend in the first direction D1, so that the data signal line DSLa of the first section can be connected to the data signal pad of the second chip area RC2 DPb, and the data signal line DSLb of the second section can be connected to the data signal pad DPc of the third chip area RC3.

The control signal line CSLa/CSLb may cross the data signal line DSLa/DSLb. In detail, the control signal line CSLa/CSLb and the data signal line DSLa/DSLb may cross at the first cross point CR1 and the second cross point CR2.

If the signal lines SL1 to SL11, CSL1, CSL2, DSL1, and DSL2 form a single wiring layer on the base substrate BS as discussed above with reference to FIGS. 4 and 5, an electrical short circuit can be between the control signal lines CSLa/CSLb and the data signal lines. Between DSLa and DSLb, the timing controller chip TC and the first driving circuit chip DI1 and the second driving circuit chip DI2 cannot operate normally. According to the comparative embodiment, the signal lines SL1 to SL11, CSL1, CSL2, DSL1, and DSL2 can be arranged in a plurality of wiring layers. For example, it is necessary to arrange the control signal line CSLa/CSLb at a vertical level different from that of the data signal line DSLa/DSLb. However, in this situation, there may be a problem that the manufacturing process becomes complicated and the manufacturing cost increases.

According to the example embodiments of the inventive concept discussed above with respect to FIGS. 3, 4, and 5, two control signal pads may be disposed on each of the second wafer region RC2 and the third wafer region RC3. The wiring layer of each of the first driver circuit die DI1 and the second driver circuit die DI2 can electrically connect the two control signal pads to each other. Therefore, even if the control signal line is connected to only one (for example, either) of the two control signal pads, the entire device can be operated normally, and thereby the degree of freedom of wiring can be increased. this In addition, the first chip area RC1 may include thereon a first control signal pad CPa1 and a second control signal pad CPa2 electrically connected to each other via the first wiring layer IML1 of the timing controller chip TC, and a second control signal pad CPa2 via the timing controller chip TC. The first data signal pad DPa1 and the second data signal pad DPa2 are electrically connected to each other on the first wiring layer IML1. The signal lines CSL1, CSL2, DSL1, and DSL2 respectively connected to the signal pads CPa1, CPa2, DPa1, and DPa2 can be connected to the first driving circuit chip DI1 and the second driving circuit chip DI2, while being positioned at the same vertical level without crossing each other .

8 is a plan view illustrating a timing controller chip, a first driving circuit chip, and a second driving circuit chip mounted on a flexible printed circuit board according to an exemplary embodiment of the inventive concept. In the following examples, detailed descriptions of the technical features repeated with respect to the content discussed with reference to FIGS. 3 to 5 will be omitted, and differences may be discussed in detail.

Referring to FIG. 8, the first surface 120a of the first chip region RC1 may include a first control signal pad CPa1 and a second control signal pad CPa2, and a first data signal pad DPa1 and a second data signal pad DPa2 thereon. The pad may be arranged in the second direction D2. Unlike the first chip area RC1 shown in FIGS. 3, 4, and 5 above, one of the first data signal pad DPa1 and the second data signal pad DPa2 can be positioned on the first control signal pad CPa1 and Between the second control signal pads CPa2, and one of the first control signal pad CPa1 and the second control signal pad CPa2 can be positioned between the first data signal pad DPa1 and the second data signal pad DPa2. That is, the first control signal pad CPa1 and the second control signal pad CPa2 and the first data signal pad DPa1 and the second data signal pad DPa2 can be alternately arranged. In detail, the first data signal pad DPa1 can be positioned between the first control signal pad CPa1 and the second control signal pad CPa2, and the second control signal pad CPa2 can be positioned on the first data signal pad Between DPa1 and the second data signal pad DPa2.

The first surface 120a of the second chip area RC2 may include a control signal pad CPb, a data signal pad DPb, and first to fourth signal pads SPb1 to SPb4 thereon. Unlike the second chip area RC2 shown in FIGS. 3, 4, and 5 above, the second control signal pad CPb2 may be omitted. The first surface 120a of the third chip area RC3 may include a control signal pad CPc, a data signal pad DPc, and first to fourth signal pads SPc1 to SPc4 thereon. Unlike the third chip area RC3 shown in FIGS. 3, 4, and 5 above, the second control signal pad CPc2 can be omitted.

On the fifth area RG5, the first control signal line CSL1 can connect the first control signal pad CPa1 of the first chip area RC1 and the control signal pad CPb of the second chip area RC2. The first data signal line DSL1 can connect the first data signal pad DPa1 of the first chip area RC1 and the data signal pad DPb of the second chip area RC2. The second control signal line CSL2 can connect the second control signal pad CPa2 of the first chip area RC1 and the control signal pad CPc of the third chip area RC3. The second data signal line DSL2 can connect the second data signal pad DPa2 of the first chip area RC1 and the data signal pad DPc of the third chip area RC3.

In some embodiments, unlike the second chip area RC2 and the third chip area RC3 discussed above with reference to FIGS. 3, 4, and 5, each of the second chip area RC2 and the third chip area RC3 It may include only one control signal pad and only one data signal pad. However, on the first chip area RC1, the first control signal pads CPa1 and the second control signal pads CPa2, the first data signal pads DPa1 and the second data signal pads DPa2 can be arranged alternately, so that the signal lines CSL1, CSL2, DSL1 And DSL2 can connect the timing controller chip TC and the first driving circuit chip DI1 and the second driving circuit chip DI2 without crossing each other.

As used herein, the terms "controller" and "timing controller" can refer to the timing controller chip TC. In addition, the term "drive circuit" can refer to drive circuit chips DI1 and DI2, and the drive circuit chips can be the same display driver integrated circuit (DDI) spaced apart from each other on the same flexible film substrate. The controller may include a timing controller configured to provide color information to the driving circuit chips DI1 and DI2. In addition, because the signal lines CSL1, CSL2, DSL1, and DSL2 do not cross each other and are in only one layer, the signal lines may be referred to herein as a "single layer of non-overlapping signal lines". The respective uppermost surfaces of the signal lines CSL1, CSL2, DSL1, and DSL2 (the surface furthest away from the first surface 120a of the flexible printed circuit board 120) can therefore be coplanar.

To help limit the signal lines extending between the controller and the DDI to a single layer of non-overlapping signal lines, the DDI may include embedded wiring lines. For example, the first pad connected to the signal line CSL1 (for example, the pad CPb1 of the driving circuit chip DI1) can be connected to the second pad spaced apart from the signal line CSL1 by the embedded wiring line in the driving circuit chip DI1 (For example, drive the pad CPb2 of the circuit chip DI1).

In the semiconductor device according to various embodiments of the inventive concept, the printed circuit board may include a signal line connecting the timing controller chip with the first driving circuit chip and the second driving circuit chip thereon. In this configuration, the signal lines can be positioned at the same vertical horizontal height without crossing each other.

The subject matter disclosed above should be regarded as illustrative rather than restrictive, and the scope of the attached patent application is intended to cover all such modifications, enhancements, and other embodiments that belong to the true spirit and scope. Therefore, to the maximum extent permitted by law, the scope should be determined by the broadest permitted interpretation of the following patent scope and its equivalent content, and should not be limited or restricted by the foregoing detailed description.

110: display panel

120: printed circuit board

130: Main drive substrate

BA: non-display area

D1: First direction

D2: second direction

DA1: the first display area

DA2: second display area

DI1: The first driver circuit chip

DI2: The second drive circuit chip

MA: installation area

PD1: the first pad area

PD2: The second pad area

PX: pixel

SP: sub pixel

TC: timing controller chip

Claims (20)

A semiconductor device includes: a base substrate; a timing controller chip on the base substrate; a first drive circuit chip and a second drive circuit chip on the base substrate; and a plurality of signal lines on the base substrate On the substrate, the plurality of signal lines are positioned at the same vertical horizontal height and are horizontally spaced apart from each other, wherein the plurality of signal lines include: a first data signal line and a first control signal line, and are electrically connected to the timing controller A chip and the first driving circuit chip; and a second data signal line and a second control signal line are electrically connected to the timing controller chip and the second driving circuit chip. The semiconductor device according to claim 1, wherein: the first data signal line is configured to transmit a first data signal between the timing controller chip and the first driving circuit chip, the The first control signal line is configured to transmit a first control signal between the timing controller chip and the first driver circuit chip, and the second data signal line is configured to transmit a first control signal between the timing controller chip and the first drive circuit chip. A second data signal is transmitted between the second driving circuit chip, and the second control signal line is configured to transmit a second control signal between the timing controller chip and the second driving circuit chip. The semiconductor device according to claim 1, wherein the first driving circuit chip includes the same display driver as the second driving circuit chip Wafer. The semiconductor device described in claim 1 further includes a first data signal pad, a second data signal pad, a first control signal pad, and a second data signal pad between the base substrate and the timing controller chip. Control signal pad, wherein the first data signal pad, the second data signal pad, the first control signal pad, and the second control signal pad are respectively connected to the first data signal line and the first data signal line Two data signal lines, the first control signal line, and the second control signal line. The semiconductor device according to claim 4, wherein the timing controller chip includes a substrate and a wiring layer on the substrate, and wherein the wiring layer connects the first data signal pad to the first data signal pad. The two data signal pads are connected to each other, and the first control signal pad and the second control signal pad are also connected to each other. The semiconductor device according to claim 4, wherein one of the first data signal pad and the second data signal pad is positioned on the first control signal pad and the second control signal pad And wherein one of the first control signal pad and the second control signal pad is positioned between the first data signal pad and the second data signal pad. The semiconductor device described in claim 1 further includes: a first control signal pad and a second control signal pad, which are located on the first chip area including the first driving circuit chip; and a third control signal pad And the fourth control signal pad, located on the second chip area including the second driving circuit chip, wherein: The position of the first control signal pad relative to the first wafer area is the same as the position of the third control signal pad relative to the second wafer area, and the second control signal pad is relative to the first wafer area. The position of the wafer area is the same as the position of the fourth control signal pad relative to the second wafer area, the first control signal line is electrically connected to the first control signal pad, and the second control signal line It is electrically connected to the fourth control signal pad. The semiconductor device according to claim 7, wherein: the first driver circuit chip includes a first substrate and a first wiring layer on the first substrate, and the second driver circuit chip includes a second A substrate and a second wiring layer on the second substrate, the first wiring layer connects the first control signal pad and the second control signal pad to each other, and the second wiring layer connects the The third control signal pad and the fourth control signal pad are connected to each other. The semiconductor device described in the first item of the patent application, wherein the base substrate is a flexible substrate. The semiconductor device according to claim 1, wherein the first data signal line and the second data signal line, and each of the first control signal line and the second control signal line At least one conductive thread is included. A printed circuit board includes: a base substrate, including a first area including a timing controller chip, a second area including a first driver circuit chip, and a third area including a second driver circuit chip; located on the first area The first data signal pad, the second data signal pad, the first A control signal pad and a second control signal pad; a data signal pad and a control signal pad located on the second area; a data signal pad and a control signal pad located on the third area; a first data signal line The first data signal pad in the first area is connected to the data signal pad in the second area; a first control signal line connects the first control signal pad in the first area to all The control signal pad in the second area; a second data signal line connecting the second data signal pad in the first area to the data signal pad in the third area; and a second control signal Line connecting the second control signal pad of the first area to the control signal pad of the third area, wherein the first data signal line and the second data signal line and the first A control signal line and the second control signal line are located at the same vertical horizontal height and are horizontally spaced apart from each other. The printed circuit board according to claim 11, wherein: the control signal pad in the second area includes a first pad and a second pad, and the control signal pad in the third area includes a first pad. Pad and a second pad, the first control signal line is connected to the first pad in the second area, the second control signal line is connected to the second pad in the third area, the The second pad in the second area does not contain any signal lines outside the first driver circuit chip, and the first pad in the third area does not include any signal lines outside the second driver circuit chip. Signal line. The printed circuit board as described in item 11 of the scope of patent application, in which: On the first area, one of the first data signal pad and the second data signal pad is located between the first control signal pad and the second control signal pad, and is located between the first control signal pad and the second control signal pad. On the first area, one of the first control signal pad and the second control signal pad is located between the first data signal pad and the second data signal pad. The printed circuit board according to item 11 of the scope of patent application, wherein: the position of the data signal pad of the second area relative to the second area is relative to the position of the data signal pad of the third area The position of the third area is the same, and the position of the control signal pad of the second area relative to the second area is the same as the position of the control signal pad of the third area relative to the third area. The location is the same. The printed circuit board as described in item 11 of the scope of patent application, wherein the base substrate is a flexible substrate. A semiconductor device includes: a controller; a first drive circuit and a second drive circuit, the first drive circuit and the second drive circuit are configured to drive a display panel and are respectively connected by a plurality of first signal lines and a plurality of A second signal line is connected to the controller; and a film, which includes the plurality of first signal lines and the plurality of second signal lines, the controller, the first driving circuit, and the The second driving circuit, wherein each of the plurality of first signal lines and each of the plurality of second signal lines are located in a single layer of non-overlapping signal lines on the film, such that The plurality of first signal lines and the plurality of second signal lines do not overlap on the film. Such as the semiconductor device described in item 16 of the scope of patent application, Wherein the controller includes a timing controller configured to provide color information to the timing controllers of the first driving circuit and the second driving circuit, and wherein on the film, the The uppermost surface of each of the plurality of first signal lines is coplanar with the uppermost surface of each of the plurality of second signal lines. The semiconductor device according to claim 17, wherein the thin film includes a flexible substrate, wherein the timing controller includes a timing controller chip on the flexible substrate, and wherein the first The driving circuit and the second driving circuit include a first display driver integrated circuit and a second display driver integrated circuit respectively located on the flexible substrate. The semiconductor device according to claim 18, wherein the plurality of first signal lines include a first data signal line and a first data signal line connecting the timing controller chip to the first display driver integrated circuit Control signal lines, wherein the plurality of second signal lines include a second data signal line and a second control signal line connecting the timing controller chip to the second display driver integrated circuit, and wherein the first A display driver integrated circuit includes an embedded wiring line that connects the first pad of the first display driver integrated circuit connected to the first control signal line to the first control signal line The signal line is spaced apart from the second pad of the first display driver integrated circuit. The semiconductor device described in item 17 of the scope of the patent application, wherein the The first driving circuit is the same as the second driving circuit, and is spaced apart from the second driving circuit on the film.

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