TWI736248B - Semiconductor storing apparatus and flash memory operation method - Google Patents

Abstract

A semiconductor storing apparatus and a flash memory operation method shortening a recovery time from a deep power-down mode without a special command for the deep power-down mode are provided. A flash memory includes: a standard command I/F circuit and a DPD controller operating through an external power voltage; a voltage supply node supplying electrical power through a first current path; a voltage supply node supplying electrical power through a second current path; an internal circuit group connecting to the voltage supply node; and a charge pump circuit connecting to the voltage supply node. Enabling the internal circuit group after enabling the charge pump circuit in a releasing DPD mode.

Description

Semiconductor storage device and operating method of flash memory

The present invention relates to a semiconductor storage device such as a flash memory and a method thereof, in particular to operation in a standby mode or a deep power saving mode.

NAND (Not and, NAND) flash memory can be read or programmed in units of pages, and erased in units of blocks. The flash memory shown in Patent Document 1 discloses a technique of supplying different power supply voltages to the page buffer/readout circuit in a standby mode (stand-by mode) and a normal operation mode, thereby Reduce power consumption in standby mode. [Prior Art Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 2006-252748

[The problem to be solved by the invention]

The flash memory has an active mode and a standby mode. The active mode performs reading, programming, erasing, etc. in response to commands from the user, and the standby mode can accept commands from the user. In the standby mode, the operation of the internal circuit is restricted so that the power consumption becomes less than a certain level, but when a command is input from the user, the command must be responded to immediately. Therefore, even in standby mode, off-leak current is generated in volatile circuits such as logic circuits or registers. The off-leak current increases with the reduction of component size, and it is in use. In the case of internal power supply voltage, the internal power supply voltage detection circuit must be operated, which consumes a certain amount of power. That is, it is difficult to reduce the current consumption in the standby mode.

In order to further reduce the power consumption in standby mode, depending on the flash memory, a deep power-down mode (deep power-down mode, hereinafter referred to as DPD mode) is equipped. In the DPD mode, the internal power supply to a part of the active internal circuit used in the standby mode is shut down to reduce the power leakage current. The DPD mode is entered into the mode by, for example, a DPD start command, and is restored from the mode by a DPD release command. Regarding the recovery from the DPD mode, a certain amount of time is required for the shut down circuit to operate normally, but on the other hand, it has the advantage of drastically reducing power consumption.

Figure 1A shows an example of operating waveforms when a NAND-type flash memory equipped with a serial peripheral interface (Serial Peripheral interface, SPI) function transitions to DPD mode. In the standby mode, select the flash memory by setting the chip select signal /CS to low level, and input the DPDDPD command (B9h) from the data registration terminal DI in synchronization with the clock signal during this period. _{The flash memory transitions to the DPD mode at time T DPD} when a certain period of tDP has elapsed since the input of the DPD command, and blocks the internal supply of voltage to a specific internal circuit. In the period before the time T _DPD , the current in the standby mode is consumed, _{and in the period after the time T DPD} , the current in the DPD mode is consumed.

In addition, FIG. 1B shows an example of the operating waveform when recovering from the DPD mode. In the standby mode, the flash memory is selected by setting the chip select signal /CS to low level. During this period, the DPD release command (ABh) to release the DPD mode is input from the data registration terminal DI in synchronization with the clock signal. After the DPD release command is input, the flash memory supplies power to the shut down internal circuit during the period of tRES, and returns to a state in which the internal circuit is operating normally _{at time T ST.} Before the time T _ST , the current in the DPD mode is consumed, and after the time T _ST , the current in the standby mode is consumed.

Figure 2 is an internal block diagram of a NAND-type flash memory that supports the DPD mode. The flash memory 10 includes a DPD controller 20, a memory cell array 30, a row decoder 40, a page buffer/readout circuit 50, a peripheral circuit 60, a high voltage circuit 70, and so on. An external power supply voltage (for example, 3.3V) VCC is supplied to the flash memory 10, and the DPD controller 20 directly uses the external power supply voltage VCC to operate. A P-channel Metal Oxide Semiconductor (PMOS) transistor P is connected between the external power supply voltage VCC and the internal circuit, and a DPD enable signal DPDEN is applied to the gate of the transistor P. In the active mode and the standby mode, the DPD controller 20 generates an L-level DPD enable signal DPDEN to turn on the transistor P. As a result, the internal voltage VDD is supplied to each internal circuit via the voltage supply node INTVDD. In the DPD mode, the DPD controller 20 generates an H-level DPD enable signal DPDEN, and sets the transistor P to be non-conductive. As a result, the supply of the external power supply voltage VCC is shut down, and the operation of the internal circuit is stopped.

In the case of releasing the DPD mode, as shown in FIG. 1B, the user inputs a DPD release command (ABh) from the outside. The DPD controller 20 responds to the input of the DPD release command, causes the DPD enable signal DPDEN to transition to the L level, turns on the transistor P, and starts to supply power from the external power supply voltage VCC to the internal circuit. As a result, the internal circuit is restored to an operable state after the period tRES.

In this way, for the existing flash memory, in order to use the DPD mode, the user must not only input the DPD command, but also the DPD release command. For flash memory controllers that do not support the DPD command and the DPD release command , Cannot use DPD mode. Furthermore, when the DPD mode is released and the power from the external power supply voltage VCC is supplied to the voltage supply node INTVDD, if the load capacitance of the internal circuit is large, the time tRES until the voltage supply node INTVDD reaches the voltage at which the internal circuit can operate becomes longer.

The present invention solves such existing problems, and its object is to provide a semiconductor storage device that does not require a dedicated command for releasing the deep power saving mode and can shorten the recovery time from the deep power saving mode. [Technical means to solve the problem]

The operating method of the flash memory of the present invention includes the step of jumping to a deep power saving mode, which blocks the power supply from the power supply source to the internal circuit; when the input includes reading, programming or erasing When removing the standard command, the step of canceling the deep power saving mode; and after canceling the deep power saving mode, the step of executing the standard command, the step of canceling from the power supply source to the internal At least the first circuit part and the second circuit part of the circuit are each supplied with electric power.

In an embodiment of the flash memory of the present invention, the step of releasing further supplies a first enable signal for making the first circuit part operable to the first circuit part, and then supplies the first enable signal to the first circuit part. After an enable signal, a second enable signal for making the second circuit part operable is supplied to the second circuit part. In an embodiment of the flash memory of the present invention, the step of executing uses the first circuit part in a first processing sequence, and uses the first circuit part in a second processing sequence after the first processing sequence. Two circuit parts. In one embodiment of the flash memory of the present invention, the first recovery time until the first enable signal is supplied and the second recovery time until the second enable signal is supplied are longer than those used for the The recovery time for the entire internal circuit to become operable is shorter. In an embodiment of the flash memory of the present invention, the load capacitance of the first circuit part is smaller than the load capacitance of the second circuit part. In an embodiment of the flash memory of the present invention, the first circuit part includes a charge pump circuit, and the second circuit part includes a peripheral circuit of the memory cell array, and the charge pump generates a boosted voltage. The time is shorter than the difference between the second recovery time and the first recovery time. In an embodiment of the flash memory of the present invention, the deep power saving mode jumps from the standby mode when the standby mode continues for a certain period of time.

The semiconductor memory device of the present invention includes: an internal circuit including at least a first circuit part and a second circuit part; a jump component, which jumps to a deep power saving mode, which will transfer a power supply source to the first circuit The power supply of the part and the second circuit part is blocked; the release part, when a standard command including read, program, or erase is input, releases the deep power saving mode; and the execution part releases the deep power saving After the mode, the standard command is executed, and the release means includes: a first current path for supplying power from the power supply source to the first circuit part; and a second current path for supplying power from the power supply source to all The second circuit part supplies power.

In one embodiment of the semiconductor memory device of the present invention, the release means includes: a first supply means that supplies a first enable signal for making the first circuit part operable to the first circuit part; and The second supply part supplies a second enable signal for making the second circuit operable to the second circuit part after supplying the first enable signal. In one embodiment of the semiconductor memory device of the present invention, the execution unit uses the first circuit part in a first processing sequence, and uses the second circuit in a second processing sequence after the first processing sequence. part. In one embodiment of the semiconductor memory device of the present invention, the first recovery time until the first enable signal is supplied and the second recovery time until the second enable signal is supplied are longer than those for the first circuit The recovery time for the part and the second circuit part to become operable is shorter. In an embodiment of the semiconductor memory device of the present invention, the load capacitance of the first circuit part is smaller than the load capacitance of the second circuit part. In one embodiment of the semiconductor memory device of the present invention, the first circuit part includes a charge pump circuit, the second circuit part includes a peripheral circuit of the memory cell array, and the charge pump generates a boosted voltage required for The time is shorter than the difference between the second recovery time and the first recovery time. In one embodiment of the semiconductor memory device of the present invention, the release unit includes a first transistor and a second transistor in the first current path and the second current path, and the release unit controls the first transistor. Conduction or non-conduction of the transistor and the second transistor. In an embodiment of the semiconductor storage device of the present invention, the semiconductor storage device is a flash memory. [Effects of the invention]

According to the present invention, there is no need for a dedicated command for releasing the deep power saving mode, and the deep power saving mode can be released in response to the input of a standard command. Furthermore, when the deep power saving mode is released, power is supplied from the power supply source to the first circuit part and the second circuit part. Therefore, compared with the case where power is supplied to the first circuit part and the second circuit part together, it can be shortened. The time for the first circuit part or the second circuit part to become operable, as a result, the recovery time from the deep power saving mode can be minimized.

The semiconductor storage device of the present invention is not particularly limited, and is implemented in, for example, a NAND type or NOR (Not OR, NOR) type flash memory. [Example]

Next, the embodiments of the present invention will be described in detail with reference to the drawings. FIG. 3 is a diagram showing a schematic internal structure of a NAND flash memory according to an embodiment of the present invention. The flash memory 100 includes: a standard command interface (interface, I/F) circuit 110 that receives standard commands, a DPD controller 120 that controls the jump to the DPD mode and the release of the DPD mode, etc., a memory cell array 130, and row decoding Internal circuits such as the processor 140, the page buffer/readout circuit 150, the peripheral circuit 160, the high voltage circuit 170, and the charge pump circuit 180.

The flash memory 100 of this embodiment can operate in multiple power consumption modes. The active mode does not limit power consumption and executes standard commands (such as read, program, erase) with full specifications. In the standby mode, when it is not in the active mode, the internal circuit is operated in accordance with the prescribed power consumption requirements, and the operation is executed in a manner that can respond to the input of standard commands and the like. In the standby mode, for example, the charge pump of the high-voltage circuit is stopped, or the internal supply voltage is reduced. In the DPD mode, in order to further reduce the power consumption in the standby mode, the power supply to a specific circuit is blocked in the standby mode.

The standard command I/F circuit 110 and the DPD controller 120 directly use the external power supply voltage VCC (for example, 3.3V) to operate, that is, they can operate in the standby mode and the DPD mode. The standard command I/F circuit 110 is an interface circuit for externally receiving standard commands prepared in advance for standard operation of the flash memory. The standard commands are, for example, commands for reading, programming, erasing, and the like. The standard command I/F circuit 110 includes a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) logic device for decoding the input standard command, and the decoded result DEC is provided to the DPD controller 120 and the peripheral circuit 160 (including A controller or state machine used to control the operation of standard commands).

The DPD controller 120 controls the transition from the standby mode to the DPD mode and the release of the DPD mode. The PMOS transistor P1 is connected to the first current path between the external power supply voltage VCC and the voltage supply node INTVDD, and the PMOS transistor P2 is connected to the second current path between the external power supply voltage VCC and the voltage supply node INTVDDCP. The voltage supply node INTVDD is connected to the row decoder 140, the page buffer/read circuit 150, the peripheral circuit 160, and the high voltage circuit 170, and the voltage supply node INTVDDCP is connected to the charge pump circuit 180.

The DPD enable signal DPDEN from the DPD controller 120 is commonly applied to the gates of the transistor P1 and the transistor P2. In the active mode and standby mode, the DPD controller 120 generates an L-level DPD enable signal DPDEN to turn on the transistor P1 and the transistor P2, thereby from the external power supply voltage VCC to the voltage supply node INTVDD via the first current path Power is supplied, and power is also supplied to the voltage supply node INTVDDCP via the second current path. In addition, when the DPD controller 120 is in the DPD mode, the DPD enable signal DPDEN is transitioned to H level, the transistor P1 and the transistor P2 of the first current path and the second current path are set to be non-conducting, blocking the voltage The power supply from the external power supply voltage VCC is supplied to the node INTVDD and the voltage supply node INTVDDCP.

The method of jumping from the standby mode to the DPD mode is not particularly limited. In a certain form, the DPD controller 120 does not input a command for jumping to the DPD mode from the user, but responds from the peripheral circuit 160 (including the control flash The signal of the memory operation controller, etc.) automatically jumps to the DPD mode. For example, if a signal indicating the transition to the standby mode is provided from the peripheral circuit 160 to the DPD controller 120, the DPD controller 120 measures the time from the point in time indicating the transition to the standby mode, and the transition occurs when the duration of the standby mode exceeds a certain time. To DPD mode, make the DPD enable signal DPDEN transition to H level, blocking the power supply from the external power supply voltage VCC. In addition, in another form, the DPD controller 120 may also jump to the DPD mode in response to the input of a command for jumping to the DPD mode from the user.

Regarding the method of releasing the DPD mode, in the existing flash memory, a dedicated command for releasing the DPD mode needs to be input from the outside. However, in this embodiment, there is a function of automatically releasing the DPD mode without inputting such a dedicated command. If in the DPD mode, the standard command I/F circuit 110 inputs a standard command, the DPD controller 120 responds to the input of the standard command to release the DPD mode. The entered standard command is executed seamlessly after the time required to recover from the DPD mode has elapsed.

When the DPD controller 120 also releases the DPD mode, that is, when power is supplied from the external power supply voltage VCC to the voltage supply node INTVDD and the voltage supply node INTVDDCP via the first current path and the second current path, respectively, it generates the subsequent use A pump enable signal PUMPEN for the charge pump circuit 180 to be operable, and a CPU enable signal CPUEN for enabling a central processing unit (CPU) included in the controller of the peripheral circuit 160 to be operable. The pump enable signal PUMPEN is supplied to the charge pump circuit 180, and the CPU enable signal CPUEN is supplied to the peripheral circuit 160. The details of these operations will be described later, but the DPD controller 120 makes the pump enable signal PUMPEN transition to H level when the voltage supply node INTVDDCP reaches the target voltage from the time when the DPD mode is released, so that the charge pump circuit 180 can be enabled. Then, when the voltage supply node INTVDD reaches the target voltage, the CPU enable signal CPUEN transitions to the H level, so that the controller of the peripheral circuit 160 can be operated.

The DPD controller 120 of this embodiment can be constructed using hardware and/or software, for example, it can include a microcomputer, a state machine, a logic device, and so on.

The memory cell array 130 includes a plurality of blocks, and each block includes a plurality of NAND strings. The NAND string can be formed two-dimensionally on the substrate, or three-dimensionally formed in the vertical direction from the main surface of the substrate. In addition, the memory unit can store binary data or multi-value data.

The peripheral circuit 160 includes, for example, the following parts: a controller or a state machine that controls the operation of the flash memory 100 based on standard commands received by the standard command I/F circuit 110; or error checking and correction (Error Checking and Correction). Correction, ECC) circuit, column selection circuit, error detection and correction of data. The high voltage circuit 170 receives the voltage boosted by the charge pump circuit 180, and generates high voltages (for example, program pulse voltage, erase pulse voltage, read path voltage, etc.) required for read, program, and erase operations. In addition, the flash memory 100 can be equipped with SPI (Serial Peripheral Interface). In SPI, instead of control signals (allowing address latching, allowing command latching, etc.), it recognizes the input commands and bits in synchronization with the serial clock signal. Address and information.

Next, the release operation of the DPD mode of the flash memory of this embodiment will be described. Fig. 4 is a diagram showing operation waveforms of each part when the DPD mode is cancelled. When the flash memory 100 is in the DPD mode, the DPD enable signal DPDEN is at H level, the power supply from the external power supply voltage VCC is blocked, and the voltage supply node INTVDD and the voltage supply node INTVDDCP are grounded (Ground, GND). flat. In the DPD mode, the standard command I/F circuit 110 and the DPD controller 120 are in a state in which they can be operated by electric power from the external power supply voltage VCC.

If a standard command is input to the standard command I/F circuit 110, the standard command I/F circuit 110 provides the DPD controller 120 and the peripheral circuit 160 with the decoded result DEC of the standard command. However, at this point in time, the peripheral circuit 160 is not in an operable state.

If the DPD controller 120 receives the decoding result DEC from the standard command I/F command 110 in the DPD mode, it automatically releases the DPD mode. That is, the DPD controller 120 makes the DPD enable signal DPDEN transition from the H level to the L level at the time t1, and sets the transistor P1 and the transistor P2 to the on state. Thus, to the voltage supply node INTVDD, power is supplied from the external power supply voltage VCC via the first current path, and to the voltage supply node INTVDDCP, power is supplied from the external power supply voltage VCC via the second current path. That is, the voltage supply node INTVDD and the voltage supply node INTVDCP are each charged by the electric power from the external power supply voltage VCC.

The voltage supply node INTVDD is connected to the row decoder 140, the page buffer/read circuit 150, the peripheral circuit 160, and the high voltage circuit 170, and the voltage supply node INTVDDCP is connected to the charge pump circuit 180. Compared with the charge pump circuit 180 connected to the voltage supply node INTVDDCP, the peripheral circuit groups 140 to 170 connected to the voltage supply node INTVDD have a larger number of transistors and larger wiring capacitance (larger load capacitance), so the voltage supply node INTVDD The speed of rising to the target voltage is slower than the voltage supply node INTVDDCP. Therefore, the charging time of the voltage supply node INTVDDCP to the target voltage is faster than that of the voltage supply node INTVDD. As shown in FIG. 4, the voltage supply node INTVDDCP reaches the target voltage from time t1 at time t2 after tRESCP, but the voltage supply node INTVDD The target voltage is reached at time t3 after tRESVDD from time t1 (tRESCP<tRESVDD). In addition, the target voltage of the voltage supply node INTVDDCP is the voltage at which the charge pump circuit 180 becomes operable, and the target voltage of the voltage supply node INTVDD is the voltage at which the CPU of the peripheral circuit 160 becomes operable.

The DPD controller 120 causes the pump enable signal PUMPEN to transition from the L level to the H level at a time t2 when the charge pump circuit 180 becomes an operable state. The charge pump circuit 180 starts pump operation at time t2 in response to the pump enable signal PUMPEN, and generates the desired pump voltage VWWPUMP at time t2A after tPUMP from time t2. In this embodiment, the charge pump circuit 180 can operate after the voltage supply node INTVDDCP reaches the target voltage, and there is no need to wait for the voltage supply node INTVDD to reach the target voltage.

In addition, the DPD controller 120 causes the CPU enable signal CPUEN to transition from the L level to the H level at a time t3 when the peripheral circuit 160 becomes an operable state. The controller (CPU) of the peripheral circuit 160 responds to the CPU enable signal CPUEN to start the operation of the standard command at time t3. At time t3 when the two voltage supply nodes INTVDD and INTVDDCP reach the target voltages, the recovery time tRES for recovering from the DPD mode ends. If the relationship is tPUMP<tRESVDD-tRESCP, the pump voltage VWWPUMP is already generated at the time when the operation of the standard command is started, so the high voltage generating circuit 170 can immediately supply the high voltage required for operation to the page buffer/readout circuit 150 or line decoder 140 and so on. Conversely, even if the relationship is tPUMP>tRESVDD-tRESCP, the supply pump voltage VWWPUMP can be accelerated compared to the case where the operation of the charge pump circuit 180 is not advanced.

The control method using the time t2 and time t3 of the DPD controller 120 is not particularly limited. For example, the DPD controller 120 can also use a built-in timer to measure the time from time t1, and when it reaches tRESCP and tRESVDD, let The enable signal PUMPEN and the enable signal CPUEN transition to H level. In another form, a detection circuit that detects the voltage of the voltage supply node INTVDDCP and the voltage supply node INTVDD may be provided. When the target voltage of each voltage supply node is detected by the detection circuit, the DPD controller 120 enables The signal PUMPEN and the enable signal CPUEN transition to H level.

As a specific operation example, if a read, program, or erase command is input to the standard command I/F circuit 110 in the DPD mode, the DPD controller 120 causes the DPD enable signal DPDEN to transition to the L level, so that the transistor P1 and transistor P2 are turned on to start supplying power from the external power supply voltage VCC, and the DPD mode is released. During the period until the voltages of the voltage supply node INTVDD and the voltage supply node INTVDDCP are restored, the DPD controller 120 operates the charge pump circuit 180 from time t1 at time t2 after tRESCP, and from time t1 to time after tRESVDD During the period up to t3, the pump voltage VWWPUMP is generated by the charge pump circuit 180, and the controller of the peripheral circuit 160 starts to execute the command at time t3. The boost voltage required for reading, programming or erasing can be used immediately after executing the command.

In this way, according to this embodiment, the DPD mode is automatically released in response to the input of the standard command, so there is no need to input a dedicated command to release the DPD mode. Even the flash memory that does not support the release command of the DPD mode can release the DPD mode. .

Furthermore, when the shut down internal circuit is restored from the DPD mode, the power is not supplied to the voltage supply node INTVDD connected to the entire internal circuit as shown in FIG. 2 but is connected to the peripheral circuit group 140 The voltage supply node INTVDD of ～170 and the voltage supply node INTVDDCP connected to the charge pump circuit 180 separately supply power, and the operation of the charge pump circuit 180 is advanced. Therefore, compared with the past, the internal circuit can be shortened and restored to be operable. State time tRES (Figure 1B).

In addition, in the above-mentioned embodiment, the internal circuit that blocks the power supply in the DPD mode is divided into the peripheral circuit groups 140 to 170 and the charge pump circuit 180 to recover from the DPD mode. However, the present invention is not necessarily limited to this form. Segmentation. When recovering from the DPD mode, the internal circuit that advances the operation does not necessarily include a charge pump circuit, but may be another circuit. Furthermore, the circuit restored from the internal circuit may be divided into three or more circuit parts, and power may be supplied to each circuit part via different current paths.

In a certain aspect, when the first circuit part and the second circuit part are restored from the DPD mode, the selection of the first circuit part and the second circuit part may correspond to the processing sequence when the standard command is executed. That is, when the standard command is executed, the first processing sequence uses the first circuit portion, and the second processing sequence uses the second circuit portion, so that the first circuit portion becomes operable before the second circuit portion. When the load capacitance of the first circuit part is smaller than the load capacitance of the second circuit part, the first circuit part starts to operate during the restoration of the second circuit part, and the restoration time is more effectively shortened. For example, when the programming operation includes programming verification and programming, and the programming verification runs first, only the part of the circuit related to the verification connected to the voltage supply node INTVDDx can be run first, and during the verification operation , The voltage supply node INTVDDy connected to the circuit part for programming reaches the target voltage.

In addition, in the described embodiment, read, program, and erase are exemplified as standard commands, but in addition to these, standard commands may also include status read (Status Read) or identifier (ID) read. Status read is to read whether the flash memory is in a ready state, whether it is in write-protected mode, whether it is a command in program/erase operation, and ID read is a command to read out manufacturer or product identification.

In addition, in the above-mentioned embodiment, an example in which power is supplied from the external power supply voltage VCC to the voltage supply node INTVDD and the voltage supply node INTVDDCP is shown, but this is an example, and the voltage supply node INTVDD and the voltage supply node INTVDDCP may be supplied from other internal sources. The power supply voltage supplies power without being directly supplied from the external power supply voltage VCC.

The preferred embodiments of the present invention have been described in detail, but the present invention is not limited to specific embodiments, and various modifications and changes can be made within the scope of the gist of the invention described in the claims.

10.100: Flash memory 20, 120: DPD controller 30, 130: Memory cell array 40: Row decoder 50: Page buffer/readout circuit 60: Peripheral circuit 70: High voltage circuit 110: Standard command I/F circuit 140: Row decoder (peripheral circuit) 150: Page buffer/readout circuit (peripheral circuit) 160: Peripheral circuit (peripheral circuit) 170: High-voltage circuit (peripheral circuit) 180: Charge pump circuit ABh: DPD release command B9h: DPDDPD command CPUEN: CPU enable signal DEC: decoding result DI: data registration terminal DPDEN: DPD enable signal INTVDD, INTVDDCP: voltage supply node P: PMOS transistor P1, P2: transistor PUMPEN: pump enable Power signal T _DPD , T _ST : time t1, t2, t2A, t3: time tDP: a certain period of time tRES: period, time, recovery time VCC: external power supply voltage VWWPUMP: pump voltage/CS: chip selection signal

FIG. 1A is a diagram showing an example of operating waveforms when a conventional flash memory jumps to the DPD mode. FIG. 1B is a diagram showing an example of operating waveforms when the DPD mode of the conventional flash memory is released. Fig. 2 is a diagram showing the internal structure of a conventional flash memory. Fig. 3 is a diagram showing the internal structure of a flash memory according to an embodiment of the present invention. Fig. 4 is a diagram showing operation waveforms of various parts when the DPD mode of the embodiment of the present invention is cancelled.

100: Flash memory

110: Standard command I/F circuit

120: DPD controller

130: Memory cell array

140: Line decoder (peripheral circuit)

150: Page buffer/readout circuit (peripheral circuit)

160: Peripheral circuit

170: High voltage circuit (peripheral circuit)

180: charge pump circuit

CPUEN: CPU enable signal

DEC: Decoding result

DPDEN: DPD enable signal

INTVDD, INTVDDCP: voltage supply node

P1, P2: Transistor

PUMPEN: Pump enable signal

VWWPUMP: Pump voltage

VCC: External power supply voltage

Claims (15)

A method for operating a flash memory includes the step of jumping to a deep power saving mode that blocks the power supply from the power supply source to the internal circuit; when the input includes reading, programming or erasing The step of releasing the deep power saving mode according to the decoding result of the standard command; and after releasing the deep power saving mode, the step of executing the standard command, the step of releasing is from the The power supply source supplies power to at least the first circuit part and the second circuit part of the internal circuit, respectively. The method for operating a flash memory according to claim 1, wherein the step of releasing further supplies the first circuit part with a first enable signal for enabling the first circuit part to operate, and After the first enable signal is supplied, a second enable signal for enabling the second circuit part to operate is supplied to the second circuit part. The flash memory operating method according to claim 2, wherein the step of executing uses the first circuit part in a first processing sequence, and in a second processing sequence after the first processing sequence Use the second circuit part. The operating method of the flash memory according to claim 2 or 3, wherein the first recovery time until the first enable signal is supplied and the second recovery time until the second enable signal is supplied It is shorter than the recovery time for bringing the entire internal circuit into an operable state. The method for operating a flash memory according to any one of claims 1 to 3, wherein the load capacitance of the first circuit part is smaller than the load capacitance of the second circuit part. The method for operating a flash memory according to claim 4, wherein the first circuit part includes a charge pump circuit, the second circuit part includes a peripheral circuit of the memory cell array, and the charge pump generates a boost The time required for the voltage is shorter than the difference between the second recovery time and the first recovery time. The method for operating a flash memory according to claim 1, wherein the deep power saving mode jumps from the standby mode when the standby mode continues for a certain period of time. A semiconductor storage device includes: an internal circuit including at least a first circuit part and a second circuit part; a jump component, which jumps to a deep power saving mode, the deep power saving mode blocking power supply to the first circuit Power supply for the second circuit part and the second circuit part; a release part, when a standard command including read, program, or erase is input, the deep power saving mode is released according to the decoded result of the standard command; and an execution part, in After the deep power saving mode is released, the standard command is executed, and the release means includes: a first current path for supplying power from the power supply source to the first circuit part; and a second current path for supplying power from the power supply source to the first circuit section The power supply source supplies power to the second circuit part. The semiconductor storage device according to claim 8, wherein the release means includes: a first supply means for supplying the first circuit part with a first enable signal for enabling the operation of the first circuit part; And a second supply component, after supplying the first enable signal, supplies the second circuit part with a second enable signal for enabling the second circuit to operate. The semiconductor storage device according to claim 8, wherein the execution unit uses the first circuit part in a first processing sequence, and uses the second circuit part in a second processing sequence after the first processing sequence. Circuit part. The semiconductor storage device according to claim 9, wherein the first recovery time until the supply of the first enable signal and the second recovery time until the supply of the second enable signal are greater than those used for making the first enable signal The recovery time for the circuit part and the second circuit part to become operable is shorter. The semiconductor storage device according to any one of claims 8 to 10, wherein the load capacitance of the first circuit part is smaller than the load capacitance of the second circuit part. The semiconductor storage device according to claim 11, wherein the first circuit part includes a charge pump circuit, and the second circuit part includes a peripheral circuit of a memory cell array, and the charge pump generates a boosted voltage. The time is shorter than the difference between the second recovery time and the first recovery time. The semiconductor storage device according to claim 8, wherein The release component includes a first transistor and a second transistor in the first current path and the second current path, and the release component controls the conduction or conduction of the first transistor and the second transistor. Non-conductive. The semiconductor storage device according to any one of claims 8 to 10, wherein the semiconductor storage device is a flash memory.

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