TWI735275B - Methods of fabricating semiconductor structure - Google Patents

Abstract

A method for fabricating semiconductor structure includes the steps of providing a substrate having a device region and a peripheral region surrounding the device region, forming a first dielectric layer on the device region and the peripheral region of the substrate, forming a mask layer on the first dielectric layer on the device region, forming a second dielectric layer on the device region and the peripheral region of the substrate, performing a lift-off process to remove the mask layer and the second dielectric layer on the mask layer such that the first dielectric layer on the device region is exposed, and performing a polishing process to the first dielectric layer and the second dielectric layer on the first dielectric layer thereby obtaining a polished surface.

Description

Manufacturing method of semiconductor structure

The present invention relates to a manufacturing method of a semiconductor structure, in particular to a planarization method of a semiconductor structure.

3D IC packaging and 3D IC integration are important technologies for advanced semiconductor manufacturing processes to achieve smaller package sizes and more functional integration. The basic method is to use bonding technology to stack the chips. Bonding, and forming an electrical connection structure (such as through silicon via, TSV) between the wafers to transmit signals between the wafers. Such technology can effectively use space and increase the number of components that can be accommodated per unit area. In addition, because the stacked structure can effectively shorten the distance of current signal transmission, the signal delay can be reduced.

Wafer level bonding is a technology in which two wafers are bonded first, and then diced to obtain a three-dimensional stacked chip. Fusion Bonding is one of the wafer bonding technologies widely used in the field, which forms a wafer bond by forming a bond between the surfaces of two wafers. The process of fusion bonding usually involves first aligning and contacting two wafers at room temperature to form a weak bond between the surfaces of the two wafers (this step is also called pre-bonding), and then thermal annealing ( Thermal anneal) to transform the weak bond into a covalent bond (covalent bond) to form a strong and strong bond.

Since fusion bonding involves the contact of the wafer surface, the flatness of the wafer surface is related to the quality of the bonding. The chemical mechanical polishing (CMP) process is often used to planarize the wafer surface, but it is still difficult to avoid edge roll off in the peripheral area of the wafer. When the degree of roll-off is severe or the roll-off range is expanded, it will lead to poor joints in adjacent areas.

The main purpose of the present invention is to provide a method for manufacturing a semiconductor structure. By forming a second dielectric layer as a polishing buffer layer on the first dielectric layer in the peripheral area of the wafer, the rolling of the first dielectric layer in the peripheral area can be reduced. The degree of reduction, thereby improving the yield of wafer-level bonding.

According to an embodiment of the present invention, a method for manufacturing a semiconductor structure includes the following steps. First, a substrate is provided, including a device area and a peripheral area surrounding the device area. Next, a first dielectric layer is formed on the device region and the peripheral region, and then a mask layer is formed on the first dielectric layer of the device region. Then, a second dielectric layer is formed on the device area and the peripheral area, and then a lift-off process is performed to simultaneously remove the mask layer and the second dielectric layer on the mask layer, and expose The first dielectric layer in the device area is exited. Subsequently, a polishing process is performed on the first dielectric layer and the second dielectric layer on the first dielectric layer to obtain a polished surface.

10: Base

10a: Edge

10b: Main surface

12: component area

14: Surrounding area

18: Integrated circuit structure

18a: Edge

20: The first dielectric layer

22: Mask layer

22a: Edge

24: second dielectric layer

26: opening

30: Base

100: method

102: Step

104: Step

106: step

108: Step

110: Step

112: Step

24A: Dielectric layer convex ring

24a: side wall

AA': Tangent

B1: Junction area

B2: Junction area

C: Center

D1: distance

D2: distance

D2’: Distance

D3: distance

D4: Slope

P1: etching process

P2: Lift off the process

P3: Grinding process

R: radius

R1: radius

S: Grinding surface

S1: flat zone

S2: Roll-off zone

T0: thickness

T1: thickness

T2: thickness

T3: thickness

T4: target thickness

W: width

X: direction

Y: direction

Z: direction

In order to make the above and other objectives, features, advantages and embodiments of the present invention more obvious and understandable, the detailed description of the accompanying drawings is as follows:

FIG. 1 shows a step flow of a method of fabricating a semiconductor structure according to an embodiment of the present invention picture.

FIG. 2 is a schematic plan view of a semiconductor structure according to an embodiment of the invention.

Figures 3 to 10 are schematic cross-sectional views taken along the line AA' in Figure 2 to illustrate the steps of the manufacturing method of the semiconductor structure in Figure 1, where: Figure 3 shows the substrate The integrated circuit structure and the first dielectric layer are formed; Figure 4 shows the formation of a mask layer on the first dielectric layer; Figure 5 shows the formation of a second dielectric layer on the first dielectric layer and the mask layer Dielectric layer; Figure 6 shows the etching process for the second dielectric layer; Figure 7 shows a lift-off process on the semiconductor structure; Figure 8 shows the plane of the semiconductor structure after the lift-off process Schematic diagram; Figure 9 shows a polishing process for the semiconductor structure; and Figure 10 shows a schematic cross-sectional view of the semiconductor structure after the polishing process.

FIG. 11 is a schematic cross-sectional view of a bonded semiconductor structure according to an embodiment of the present invention.

In order to enable those who are familiar with the technical field of the present invention to understand the present invention further, the following specifically enumerates the preferred embodiments of the present invention, together with the accompanying drawings, to explain in detail the content of the present invention and the effects to be achieved. . It should be understood that the following embodiments can replace, recombine, and mix the features of several different embodiments without departing from the spirit of the present disclosure to complete other embodiments.

In order to enable readers to easily understand and simplify the drawings, the multiple drawings in this disclosure only depict a part of the display device, and the specific elements in the drawings are not drawn according to actual scale. In addition, the number and size of each element in the figure are only for illustration, and are not used to limit the scope of the disclosure. In the scheme, the same Or similar elements can be represented by the same reference numerals. As for the relationship between the top and bottom of the relative elements in the figure described in the text, anyone in the art should understand that it refers to the relative position of the object, and therefore all can be flipped to present the same components, which should be the same as disclosed in this specification. The scope.

In this specification, when an element or film layer is referred to as "on another element or film layer" or "connected to another element or film layer", it can be directly on another element or film layer, or directly It is connected to another element or film layer, or there may be other elements or film layers in between. In contrast, when an element is said to be "directly on another element or film" or "directly connected to another element or film", there is no intervening element or film between the two.

In this specification, "wafer", "base" or "substrate" means any structure that includes an exposed surface on which materials can be deposited according to the embodiments of the present invention to make an integrated circuit structure, such as wiring Floor. It should be understood that the "substrate" includes semiconductor wafers, but is not limited to this. "Substrate" in the manufacturing process also means a semiconductor structure including a material layer fabricated thereon.

In this article, the "spacing" or "distance" between components, or the "width" or "length" of the component, is the projection of the component on the XY plane, YZ plane or XZ plane along the X direction and Y direction Or Z direction to define. The same "parallel" or "non-parallel" means that the projection of the extension line of the component on the XY plane, YZ plane or XZ plane is "parallel" or "non-parallel".

Please refer to Figure 1 to Figure 10. FIG. 1 is a flowchart of steps of a method of fabricating a semiconductor structure according to an embodiment of the present invention. FIG. 2 is a schematic plan view of a plane (XY plane) defined in the X direction and the Y direction of a semiconductor structure according to an embodiment of the present invention. Figure 3, Figure 4, Figure 5, Figure 6, Section Figures 7, 8, 9, and 10 are schematic cross-sectional views of a plane (XZ plane) defined in the X direction and the Z direction of the semiconductor structure along the AA' tangent line. Figure 8 is a schematic plan view of the semiconductor structure on the XY plane.

The manufacturing method 100 of the semiconductor structure of this embodiment first proceeds to step 102 to provide a substrate, which includes a device region and a peripheral region surrounding the device region. Please refer to Figure 2, the substrate 10 may be made of semiconductor materials, such as silicon substrates, epitaxial silicon substrates, silicon carbide substrates, three-five group substrates, silicon-on-insulator (SOI), but not limited to this . In some embodiments, the substrate may also be made of a non-semiconductor material, such as a glass, plastic, or sapphire substrate. In some embodiments, the substrate 10 is, for example, a wafer, and the distance from the center C of the substrate 10 to the edge 10a of the substrate 10 is a radius R. The substrate 10 includes a main surface 10 b parallel to the XY plane, and includes an element area 12 and a peripheral area 14. The peripheral area 14 is interposed between the element areas 12 of the edge 10 a of the substrate 10 and surrounds the element areas 12. The element area 12 of the substrate 10 may include multiple wafer areas (not shown), and the wafer area may include integrated circuit elements and/or circuit structures, such as transistors, diodes, resistors, capacitors, inductors, and decoders. , Drivers, amplifiers, timers, buffers, internal wiring structure, etc., but not limited to this. The element area 12 and the peripheral area 14 include a boundary area B1.

In some embodiments, the peripheral region 14 has a width W, and the element region 12 is substantially a region centered on the center C and surrounded by a radius R1, wherein the radius R1 is substantially equal to the radius R minus the width W. For example, the substrate 10 is a 12-inch wafer, the radius R of which is about 150 millimeters (mm), the width W of the peripheral region 14 is about 2 mm, and the radius R1 of the device region 12 is about 148 mm. It should be understood that the above dimensions are only examples, and the width W of the peripheral area 14 and the radius R1 of the element area 12 can be adjusted according to actual conditions.

In some embodiments, as shown in FIG. 3, an integrated circuit structure 18 may be formed on the main surface 10a of the element region 12 of the substrate 10, and the integrated circuit structure 18 may include integrated circuit elements and/or circuit structures. Structures, such as transistors, diodes, resistors, capacitors, inductors, decoders, drivers, amplifiers, timers, buffers, interconnect structures, etc., but not limited to these. A distance D1 is included between the edge 18a of the integrated circuit structure 18 and the edge 10a of the substrate 10. According to an embodiment of the present invention, the distance D1 is greater than or equal to the width W of the peripheral region 14, for example, greater than or equal to 2 mm. In other words, the edge 18a of the integrated circuit structure 18 may be substantially aligned with the boundary area B1 of the element area 12 and the peripheral area 14 or be located in the element area 12.

Next, proceed to step 104 to form a first dielectric layer on the device area and the peripheral area of the substrate. Please refer to FIG. 3, the first dielectric layer 20 is fully formed on the substrate 10, completely covering the element area 12 of the substrate 10 and the integrated circuit structure 18 disposed on the element area 12, and covering at least part of the peripheral area 14. The first dielectric layer 20 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low-k dielectric material, or a combination of the above, but is not limited to this. According to an embodiment of the present invention, the first dielectric layer 20 includes a dielectric material that can be used for wafer bonding, such as silicon oxide. The first dielectric layer 20 at this time may have a predetermined thickness T0. According to some embodiments of the present invention, the thickness T0 is preferably between about 5000 angstroms (Å) and 15000 angstroms (Å). In one embodiment, the thickness T0 is approximately 10000±1000 Angstroms (Å). The first dielectric layer 20 may be formed by a chemical vapor deposition (CVD) process.

Next, proceed to step 106 to form a mask layer on the first dielectric layer in the device region. Referring to FIG. 4, the mask layer 22 is formed on the first dielectric layer 20 of the device region 12, and the first dielectric layer 20 of the peripheral region 14 is exposed. The mask layer 22 is preferably selected from a material having an etching selectivity with respect to the first dielectric layer 20. According to an embodiment of the present invention, the mask layer 22 is, for example, a photoresist layer. The method of forming the mask layer 22, for example, is to coat a photoresist material on the substrate 10 in an all-round way, and then use a photoresist edge bead removal (EBR) process or a wafer edge exposure (WEE) process to remove it. The photoresist material covering the peripheral area 14 exposes the first dielectric layer 20 of the peripheral area 14. In other embodiments, a patterning process such as a lithography and etching process may be used to remove the mask layer 22 on the peripheral region 14.

As shown in FIG. 4, the mask layer 22 may have a thickness T1. According to some embodiments of the present invention, the thickness T1 is preferably greater than or equal to 5 times the thickness T2 of the second dielectric layer 24 (refer to FIG. 5), for example, greater than or equal to 10 micrometers (μm). A distance D2 is included between the edge 22a of the mask layer 22 and the edge 10a of the substrate 10. According to an embodiment of the present invention, the distance D2 is greater than or equal to the distance D1. In other words, the width W, the distance D1, and the distance D2 satisfy the relationship W≦D1≦D2.

Then, step 108 is performed to form a second dielectric layer on the device area and the peripheral area. Please refer to FIG. 5, the second dielectric layer 24 is fully formed on the device area 12 and the peripheral area 14 of the substrate 10, covering the mask layer 22 and the first dielectric layer 20 exposed from the mask layer 22 s surface. The second dielectric layer 24 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, low-k dielectric material, or any of the above Combination, but not limited to this. According to an embodiment of the present invention, the second dielectric layer 24 and the first dielectric layer 20 may include the same material, such as silicon oxide.

It is worth noting that the second dielectric layer 24 is preferably formed by a low step coverage process, so that the deposition rate of the second dielectric layer 24 on the sidewall 22a of the mask layer 22 is slower than that of the second dielectric layer 24 on the sidewall 22a of the mask layer 22. The deposition rate of the second dielectric layer 24 on the exposed surface of the first dielectric layer 20. Therefore, the thickness T3 of the portion of the second dielectric layer 24 covering the sidewall 22 a of the mask layer 22 is smaller than the thickness T2 of the portion covering the first dielectric layer 20. According to some embodiments of the present invention, the thickness T2 is preferably between 1.5 micrometers (μm) and 2.5 micrometers (μm), and the thickness T3 is preferably less than or equal to 500 angstroms (Å). For example, in one embodiment, the thickness T2 is about 1.9±0.2 micrometers (μm), and the thickness T3 is about 500±50 angstroms (Å). The second dielectric layer 24 can be formed by a sputtering process. In some examples, when the step coverage of the second dielectric layer 24 is sufficiently low, the sidewall 22 a of the mask layer 22 may not be completely covered by the second dielectric layer 24.

Next, referring to FIG. 6, an etching process P1 may be selectively performed on the second dielectric layer 24 to remove a part of the second dielectric layer 24 until a part of the sidewall of the mask layer 22 is from the second dielectric layer 24 The opening 26 is revealed. According to an embodiment of the present invention, the etching process P1 may include a wet etching process.

Then, step 110 is performed to perform a lift-off process to simultaneously remove the mask layer and the second dielectric layer on the mask layer, and expose the first dielectric layer in the device area. Referring to FIG. 7, according to an embodiment of the present invention, the lift-off process P2 includes performing a solvent treatment on the mask layer 22 through the opening 26 to lift the mask layer 22 from the first dielectric layer 20 (lift- off), the first dielectric layer 20 of the device region 12 is exposed. The solvent treatment preferably uses a solvent that has a high etching rate for the mask layer 22 and a low etching rate for the first dielectric layer 20, or is not etchable for the first dielectric layer 20, so as to reduce the first medium during the solvent treatment. Loss of electrical layer 20. In one embodiment, when the mask layer 22 is a photoresist layer, the lift-off process P2 can use the solvent used in the photoresist edge rinsing process. In other embodiments, depending on the material of the mask layer 22, a suitable gas or liquid etchant may be used to lift the mask layer 22 away.

It is worth noting that the second dielectric layer 24 deposited on the mask layer 22 will be removed at the same time when the mask layer 22 is lifted off. Therefore, only the first dielectric layer 20 deposited on the first dielectric layer 20 is left after the lift off process P2. On the second dielectric layer 24. According to an embodiment of the present invention, as shown in FIG. 8, the remaining second dielectric layer 24 forms a dielectric layer convex ring 24A (dot marking area), which straddles the boundary between the device area 12 and the peripheral area 14 The area B1 surrounds the element area 12. A distance D2' may be included between the sidewall 24a of the second dielectric layer 24 and the edge 10a of the substrate 10. According to an embodiment of the present invention, the distance D2' may be substantially equal to the distance D2.

Then, step 112 is performed to perform a polishing process on the first dielectric layer and the second dielectric layer on the first dielectric layer to obtain a polished surface. Please refer to Figures 9 and 10, and then the first dielectric layer 20 and the remaining second dielectric layer 24 (dielectric layer convex ring 24A) are subjected to a polishing process P3 to connect the integrated circuit The first dielectric layer 20 on the structure 18 is ground from the thickness T3 to the target thickness T4, and a ground surface S is obtained. According to an embodiment of the present invention, in the polishing process P3, the first dielectric layer 20 and the second dielectric layer 24 may have substantially the same removal rate. In other embodiments, the removal rate of the second dielectric layer 24 may be slightly greater than the removal rate of the first dielectric layer 20. In the embodiment shown in FIG. 9, the second dielectric layer 24 can be completely removed in the polishing process P3, that is, the polishing surface S is completely composed of the first dielectric layer 20. In other embodiments, after the polishing process P3, a part of the second dielectric layer 24 can be left on the first dielectric layer 20 in the peripheral region 14. At this time, the polishing surface S can be formed by the first dielectric layer 20 and the second dielectric layer. 24 together constitute.

As shown in FIG. 10, the polishing surface S includes a flat area S1 and a roll-off area S2, and there is a boundary area B2 therebetween. The flat area S1 is substantially parallel to the main surface 10b of the substrate 10, and the roll-off area S2 rolls off from the boundary area B2 to the main surface 10b of the substrate 10, deviating from the extension surface of the flat area S1. The flat area S1 substantially corresponds to the element area 12, and the roll-off area S2 substantially corresponds to the peripheral area 14. According to an embodiment of the present invention, the boundary area B2 of the flat area S1 and the roll-off area S2 includes a distance D3 from the edge 10a of the substrate 10, and the roll-off area S2 includes a slope D4.

The present invention uses the dielectric layer convex ring 24A as the polishing buffer layer of the first dielectric layer 20 in the polishing process P3, which can reduce the roll-off degree of the roll-off area S2 after the polishing process P3, for example, make the flat area S1 The boundary area B2 with the roll-off zone S2 is closer to the edge 10a of the substrate 10 (ie, the distance D3 is reduced), and/or the slope D4 of the roll-off zone S2 is reduced. According to an embodiment of the present invention, the distance D3 is less than the distance D1, or less than or equal to the width W of the peripheral area 14, to ensure that the flat area S1 can completely cover the range where the integrated circuit structure 18 is provided, or can completely cover the component area 12 The range also extends to cover part of the peripheral area 14 to increase the margin of the dicing process after wafer bonding.

For example, the substrate 10 is a 12-inch wafer, and the width W of the peripheral area 14 is about 2 mm. The distance D1 is greater than or equal to 2 mm. With the method provided by the present invention, the distance D3 can be less than 2 mm. In one embodiment, the distance between the roll-off zone S2 and the center C of the substrate 10 by 148.5 mm and the extension surface of the flat zone S1 in the vertical direction may be less than 5 micrometers (μm).

Please refer to FIG. 11, which is a schematic cross-sectional view of a bonded semiconductor structure according to an embodiment of the present invention. Subsequently, the ground surface S of the first dielectric layer 20 can be used as a bonding surface to bond another substrate 30. The substrate 30 may be another wafer, for example. The surface of the substrate 30 facing the substrate 10 may include materials used to form a bond with the first dielectric layer 20, such as silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and low dielectric constant (low-dielectric constant). k) Dielectric material, or a combination of the above, but not limited to this. Before bonding with the substrate 30, the polished surface S of the first dielectric layer 20 may be subjected to surface treatment (such as plasma activation) to promote the formation of the bond between the first dielectric layer 20 and the substrate 30.

In summary, the present invention uses the second dielectric layer (dielectric layer convex ring) as the polishing buffer layer of the first dielectric layer in the polishing process, which can reduce the degree of roll-off of the first dielectric layer in the peripheral area and improve the polishing surface The flatness is conducive to subsequent bonding with another substrate. In addition, in an embodiment of the present invention, photoresist is used as the mask layer, and the photoresist edge washing (EBR) process or the crystal edge exposure (WEE) process can be conveniently used to adjust the coverage of the mask layer to control the second dielectric layer. The (dielectric layer convex ring) covers the area of the first dielectric layer, and a photoresist cleaning solvent can be used for the lift-off process. In addition, an embodiment of the present invention uses a sputtering process to form the second dielectric layer, which can reduce the thickness of the second dielectric layer covering the sidewall of the mask layer, and facilitate the removal of the solvent or etchant during the process to etch from the sidewall of the mask layer . It should be understood that the manufacturing method of the semiconductor structure of the present invention is not limited to be applied to the planarization of the surface of the wafer-level bonding, and can also be applied to other planarization steps of the semiconductor structure, for example, for a faster polishing removal rate and/or surface shape The recessed area forms a polishing buffer layer to improve the planarization effect of the polishing process.

The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: Base

10a: Edge

10b: Main surface

12: component area

14: Surrounding area

18: Integrated circuit structure

18a: Edge

20: The first dielectric layer

22: Mask layer

24: second dielectric layer

24A: Dielectric layer convex ring

24a: side wall

C: Center

D2’: Distance

P2: Lift off the process

X: direction

Z: direction

Claims (13)

A method for manufacturing a semiconductor structure includes: providing a substrate including a device area and a peripheral area surrounding the device area; forming an integrated circuit structure in the device area of the substrate; on the device area and the peripheral area Forming a first dielectric layer and covering the integrated circuit structure; forming a mask layer on the first dielectric layer in the device area; forming a second dielectric layer on the device area and the peripheral area; Perform a lift-off process to simultaneously remove the mask layer and the second dielectric layer on the mask layer, and expose the first dielectric layer of the device region; and the first dielectric layer And the second dielectric layer on the first dielectric layer is subjected to a polishing process to obtain a polished surface. According to the manufacturing method of the semiconductor structure described in claim 1, wherein before the lift-off process, the second dielectric layer is etched to form an opening to expose the sidewall of the mask layer. According to the manufacturing method of the semiconductor structure described in claim 1, wherein the lift-off process includes performing a solvent treatment on the mask layer through the opening. According to the manufacturing method of the semiconductor structure described in the first item of the patent application, the mask layer includes a photoresist layer. According to the manufacturing method of the semiconductor structure described in the first item of the patent application, the materials of the first dielectric layer and the second dielectric layer respectively include silicon oxide. According to the manufacturing method of the semiconductor structure described in the first item of the scope of the patent application, the second dielectric layer is formed by a sputtering process. The method for fabricating a semiconductor structure as described in claim 1, wherein the thickness of the second dielectric layer on the sidewall of the mask layer is smaller than that of the second dielectric layer on the first dielectric layer thickness of. According to the manufacturing method of the semiconductor structure described in claim 1, wherein the distance from the integrated circuit structure to an edge of the substrate is smaller than the distance from the mask layer to the edge of the substrate. According to the method for fabricating a semiconductor structure described in claim 1, wherein the polishing surface includes a flat area and a roll-off area adjacent to the flat area, wherein the flat area is a boundary area with the roll-off area to the The distance from an edge of the substrate is smaller than the distance from the semiconductor structure to the edge of the substrate. As for the manufacturing method of the semiconductor structure described in claim 1, wherein after the lift-off process, the second dielectric layer on the first dielectric layer overlaps a boundary area between the device area and the peripheral area Directly above. According to the manufacturing method of the semiconductor structure described in claim 1, wherein the second dielectric layer on the first dielectric layer is completely removed in the polishing process. The manufacturing method of the semiconductor structure as described in the first item of the patent application, wherein before forming the second dielectric layer, it further includes performing an edge removal (EBR) process on the mask layer to remove the surrounding area The mask layer. According to the manufacturing method of the semiconductor structure described in claim 1, wherein after the polishing process, the polishing process further includes using the polishing surface as a bonding surface to bond another substrate.

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