TWI727761B - Memory device and method of fabricating the same - Google Patents

Abstract

A memory device includes: a first bit line on a dielectric layer and a second bit line over the first bit line; a first word line and a second word line between the first bit line and the second bit line; a source line between the first word line and the second word line; a channel pillar through the first word line and the source line, and the second word line, and is connected to the first bit line, the source line, and the second bit line; a first charge storage structure surrounding a top surface and a bottom surface of the first word line and between a sidewall of the first word line and a lower portion of the sidewall of the channel pillar; and a second charge storage structure surrounding a top surface and a bottom surface of the second word line and between a sidewall of the second word line and an upper portion of a sidewall of the channel pillar.

Description

Memory element and manufacturing method thereof

The invention relates to a memory element and a manufacturing method thereof.

As technology changes with each passing day, advances in electronic components have increased the need for greater storage capacity. In order to meet the demand for high storage density, the size of memory components has become smaller and more integrated. Therefore, the type of memory device has evolved from a two-dimensional memory device (2D memory device) with a planar gate structure to a three-dimensional memory device (3D memory device) with a vertical channel (VC) structure. device). However, a three-dimensional memory device with a vertical channel structure still needs to face many challenges.

The present invention provides a memory element and a manufacturing method thereof, which can have a plurality of memory cells stacked vertically in a unit area, so as to effectively utilize the area of the substrate, and is compatible with existing manufacturing processes.

An embodiment of the present invention provides a memory device, including: at least one semiconductor layer located above a dielectric layer; a first bit line and a second bit line, wherein the first bit line is located on the dielectric layer, The second bit line is located above the first bit line; the first word line and the second word line are located between the first bit line and the second bit line; the source line, Located between the first character line and the second character line; the channel pillar penetrates the first character line, the source line and the second character line, and is connected to the first character line A bit line, the source line and the second bit line are connected; A first charge storage structure surrounding the top and bottom surfaces of the first word line and between the sidewall of the first word line and the lower part of the sidewall of the channel pillar; and a second charge storage structure , Surrounding the top surface and the bottom surface of the second character line, and between the side wall of the second character line and the upper part of the side wall of the channel column. The first word line, the first charge storage structure and the channel pillar form a first memory cell; the second word line, the second charge storage structure and the channel pillar form a second memory unit.

An embodiment of the present invention also provides a method for manufacturing a memory device, including: forming a first bit line on a dielectric layer; and at least one cycle process. The at least one cycle process includes the following steps. A first stacked structure, a conductive layer, and a second stacked structure are formed on the first bit line and the dielectric layer, wherein the first stacked structure and the second stacked structure each include bottom-up The first insulating layer, the sacrificial layer, and the second insulating layer of, the conductor layer is used as a source line; a hole is formed through the second stacked structure, the conductor layer, and the first stacked structure; A channel pillar is formed in the hole, and the conductive pillar is connected to the first bit line; a recess is formed in the second stacked structure, the conductor layer, and at least a portion of the first stacked structure; removed The second stack structure and the sacrificial layer of the first stack structure exposed by the recesses to form a first character line trench and a second character line trench, the first character line trench The sidewalls of the channel pillars are exposed with the second character line trench; a first charge storage structure is formed to cover the top and bottom surfaces of the first character line trench and the sidewalls of the channel layer, and form a second charge A storage structure to cover the top and bottom surfaces of the second character line trench and the sidewalls of the channel layer; a first character line is formed in the first character line trench, and a first character line is formed in the second character line trench A second character line is formed in the character line trench; an insulating material is filled in the recess; and a second bit line is formed above the second stack structure, the second bit line and the channel The column is electrically connected. The first word line, the first charge storage structure and the channel pillar form a first memory cell; the second word line, the second charge storage structure and the channel pillar form a second memory unit.

The three-dimensional memory element of the present invention may include a plurality of memory cells stacked vertically in a unit area, and the area of the substrate can be effectively used. Moreover, the manufacturing process of the three-dimensional memory device of the present invention is compatible with existing manufacturing processes.

1A, the memory device 10 of the embodiment of the present invention is a three-dimensional NOR flash memory device, which is disposed on a substrate 100. The substrate 100 includes a plurality of blocks BLK separated by a plurality of insulating walls St. In FIG. 1A, multiple blocks (Block) BLK are represented by two blocks BLK0 and BLK1, but not limited to this. Block BLK0 and block BLK1 are separated by insulating walls (or insulating seams) St0, St1, and St2. The memory element 10 includes a plurality of memory cell groups MCt located in the first region R1 of each block BLK. The first area R1 can also be referred to as a memory cell area. The multiple memory cell groups MCt in each block BLK can be respectively arranged in an array formed by multiple rows and multiple columns. The memory cell groups MCt of two adjacent rows can be aligned or staggered. For example, the memory cell group MCt0 in the block BLK0 is arranged in an array formed by multiple rows and multiple columns, and the memory cell groups MCt0 of two adjacent columns can be staggered with each other (as shown in FIG. 1A), or aligned with each other (Not shown). The memory cell group MCt1 in the block BLK1 is also arranged in an array formed by multiple rows and multiple columns, and the memory cell groups MCt1 of two adjacent columns can be staggered with each other (as shown in FIG. 1A) or aligned with each other (not shown) Out). In addition, the memory cell group MCt0 of the odd row in the block BLK0 and the memory cell group MCt1 of the odd row in the block BLK1 are aligned with each other in the first direction d1. The even row memory cell group MCt0 in the block BLK0 and the even row memory cell group MCt1 in the block BLK1 are aligned with each other in the first direction d1.

1B, each memory cell group MCt includes two superimposed first memory cells M_B and second memory cells M_T in the third direction d3. For example, in FIG. 2, the block BLK0 has first memory cells M0 ₁₁ _B, M0 ₁₂ _B, M0 ₁₃ _B, and second memory cells M0 ₁₁ _T, M0 ₁₂ _T, and M0 ₁₃ _T. The second memory units M0 ₁₁ _T, M0 ₁₂ _T, and M0 ₁₃ _T are respectively arranged above the first memory units M0 ₁₁ _B, M0 ₁₂ _B, and M0 ₁₃ _B, and respectively form a memory cell group MCt0. Similarly, the block BLK1 has first memory cells M1 ₁₁ _B, M1 ₁₂ _B, M1 ₁₃ _B and second memory cells M1 ₁₁ _T, M1 ₁₂ _T, and M1 ₁₃ _T. The second memory units M1 ₁₁ _T, M1 ₁₂ _T, and M1 ₁₃ _T are respectively disposed above the first memory units M1 ₁₁ _B, M1 ₁₂ _B, and M1 ₁₃ _B, and respectively form a memory cell group MCt1.

1A and FIG. 2, the memory device 10 further includes a bit line BL_B and a bit line BL_T extending in the first direction d1. The bit line BL_T is correspondingly arranged above the bit line BL_B. The bit line BL_B is, for example, a bit line including BL0_B, BL1_B, ... BL9_B, or more. The bit line BL_T is, for example, a bit line including BL0_T, BL1_T,...BL9_T, or more. Each bit line BL_B and bit line BL_T can be connected in series with the drain of the first memory cell and the drain of the second memory cell in different blocks BLK. For example, the bit line BL0_B can be connected in series _{with the drain of the first memory cell M0 11} _B in the block BLK0 and the drain of the first memory cell M1 ₁₁ _B in the block BLK1. The bit line BL0_T can be connected in series _{with the drain of the second memory cell M0 11} _T in the block BLK0 and the drain of the second memory cell M1 ₁₁ _T in the block BLK1.

1A and FIG. 2, the memory element 10 further includes a plurality of source lines SL to connect the common sources of the first memory cells and the second memory cells in the same row in the same block BLK. For example, the memory element 10 further includes source lines SL0 and SL1. The source line SL0 can be connected in series to _{the common source of the first memory cell M0 11} _B and the second memory cell M0 ₁₁ _T, and the common source of the first memory cell M0 ₁₂ _B and the second memory cell M0 ₁₂ _T in the block BLK0 And the common source of the first memory cell M0 ₁₃ _B and the second memory cell M0 _{13 _T.} Similarly, the source line SL1 can be connected in series to _{the common source of the first memory cell M1 11} _B and the second memory cell M1 ₁₁ _T, the first memory cell M1 ₁₂ _B and the second memory cell M1 ₁₂ _T in the block BLK1 The common source of the first memory cell M1 ₁₃ _B and the common source of the second memory cell M1 _{13 _T.}

1A and 2, the memory element 10 also includes a plurality of word lines WL to connect the gates of the first memory cells in the same row or the gates of the second memory cells in the same row in the same block BLK Gate. For example, the word line WL00 connects the gates _{of the first memory cells M0 11} _B, M0 ₁₂ _B, and M0 ₁₃ _B in the same column (first column) in the block BLK0. The word line WL01 connects the gates of the second memory cells M0 ₁₁ _T, M0 ₁₂ _T, and M0 ₁₃ _T in the same row (second row) in the block BLK0. The word line WL10 connects the gates of the first memory cells M1 ₁₁ _B, M1 ₁₂ _B, and M1 ₁₃ _B in the same row (first row) in the block BLK1. The word line WL11 connects the gates of the second memory cells M1 ₁₁ _T, M1 ₁₂ _T, and M1 ₁₃ _T in the same row (second row) in the block BLK1.

1B, in this embodiment, the memory cell group MCt0 in the block BLK0 includes a first memory cell M0 ₁₁ _B and a second memory cell M0 ₁₁ _T. The first memory cell M0 ₁₁ _B includes a gate G0 (that is, a word line WL00), a charge storage structure 140B, a channel pillar CP, a bit line BL0_B (drain D0), and a source line SL0 (source S, or shared Source). The second memory unit M0 ₁₁ _T is arranged above the first memory unit M0 ₁₁ _B. The second memory cell M0 ₁₁ _T includes a gate G1 (that is, a word line WL01), a charge storage structure 140T, a channel pillar CP, a bit line BL0_T (drain D1), and a source line SL0 (source S, or called Shared source). The gate G0 and the gate G1 are arranged between the bit line BL0_B (drain D0) and the bit line BL0_T (drain D1).

The charge storage structure 140B and the charge storage structure 140T are separated from each other, and form the charge storage structure 140. The charge storage structure 140T is located above the charge storage structure 140B. The charge storage structure 140B covers and physically contacts the top surface and the bottom surface of the gate electrode G0, and is located between the sidewall of the gate electrode G0 and the lower part of the outer sidewall of the channel pillar CP and is in contact with each other. The charge storage structure 140T covers and physically contacts the top surface and the bottom surface of the gate electrode G1, and is located between the sidewall of the gate electrode G1 and the upper part of the outer sidewall of the channel pillar CP and is in contact with each other. The source line SL0 (source S) is arranged between the gate G0 and the gate G1. The source line SL0 (source S) is a continuous layer, which is in physical contact with the middle of the outer sidewall of the channel pillar CP. The bit line BL0_B (drain D0) is in physical contact with the bottom surface of the channel column CP. The bit line BL0_T (drain D1) is electrically connected to the top surface of the channel pillar CP through the via V1.

1A and 1C, the end of the word line WL00 is connected to the metal layer ML through the word line contact window WLC0. The end of the word line WL01 is connected to the metal layer ML through the word line contact WLC1. The end of the source line SL0 is connected to the metal layer ML via the source line contact SLC. The end of the word line WL00, the end of the source line SL0, and the end of the word line WL01 are arranged in the second region R2 of the block BLK0. The end of the word line WL00, the end of the source line SL0, and the end of the word line WL01 can be stepped, so the second region R2 can also be called a stepped region.

1A and 1B, in some embodiments, the second region R2 further includes a plurality of dummy pillars DP. The dummy post DP is used to provide support for the structure in the process to avoid collapse of the layer or structure. The dummy pillar DP may be formed at the same time when the memory hole (or channel hole) and the channel pillar CP are formed. The structure of the dummy pillar DP may be the same as the structure of the channel pillar CP, but the size may be the same or similar to the size of the memory hole (or channel hole). Taking the channel column CP and the dummy column DP arranged in the block BLK0 as an example, there is a first bit line BL0_B under the channel column CP and electrically connected to the bit line BL0_B, and there is no bit under the dummy column DP The line BL0_B is electrically disconnected from the bit line BL0_B. An interlayer window is formed above the channel pillar CP, such as a via window V1, to be electrically connected to the bit line BL0_T, and a via window is not formed above the dummy pillar DP. Therefore, the dummy pillar DP and the bit line BL0_T are electrically connected to each other. Sex is not connected. There are gate G0, source line SL0, gate G1 or charge storage structure 140 around the sidewall of the dummy pillar DP.

Referring to FIG. 3A, the manufacturing method of the memory device 10 (as shown in FIG. 1A) of the embodiment of the present invention is as follows. The following embodiments are described by forming a single memory cell group MCt. However, a plurality of memory cell groups MCt can be formed by the following process. First, a substrate (not shown) is provided. The substrate includes a semiconductor substrate, such as a silicon substrate. A dielectric layer 102 is formed on the substrate. The material of the dielectric layer 102 is, for example, silicon oxide formed by chemical vapor deposition. A bit line BL_B is formed on the dielectric layer 102. The bit line BL_B can also be called the drain (D0). In some embodiments, the method for forming the bit line BL_B is, for example, using chemical vapor deposition to form doped polysilicon, and then patterning through lithography and etching processes. Then, another dielectric layer (not shown) is formed, and then a planarization process such as a chemical mechanical polishing process is performed to remove the another dielectric layer on the bit line BL_B. In an alternative embodiment, before forming the bit line BL_B, the another dielectric layer is formed first, and then the another dielectric layer is patterned to form a bit line trench. Thereafter, a doped polysilicon layer is formed and filled on the other dielectric layer and the bit line trench, and then a planarization process such as a chemical mechanical polishing process is performed to remove the doped polysilicon on the other dielectric layer A polysilicon layer, thereby forming a bit line BL_B.

Next, a first stacked structure 110, a conductive layer 120, and a second stacked structure 130 are formed on the bit line BL_B and the dielectric layer 102. The first stacked structure 110 includes a first insulating layer 112, a sacrificial layer 114, and a second insulating layer 116 stacked from bottom to top. The material of the first insulating layer 112 and the second insulating layer 116 is, for example, silicon oxide formed by chemical vapor deposition. The material of the sacrificial layer 114 is different from the materials of the first insulating layer 112 and the second insulating layer 116, for example, silicon nitride formed by chemical vapor deposition. The thickness of the first insulating layer 112, the sacrificial layer 114, and the second insulating layer 116 may be the same or different.

The conductive layer 120 is, for example, a doped polysilicon layer formed by a chemical vapor deposition method. The conductor layer 120 serves as a source line SL (source S). The second stacked structure 130 includes a first insulating layer 132, a sacrificial layer 134, and a second insulating layer 136 stacked from bottom to top. The material of the first insulating layer 132 and the second insulating layer 136 is, for example, silicon oxide formed by chemical vapor deposition. The material of the sacrificial layer 134 is different from the materials of the first insulating layer 132 and the second insulating layer 136, for example, silicon nitride formed by chemical vapor deposition. The thickness of the first insulating layer 132, the sacrificial layer 134, and the second insulating layer 136 may be the same or different. For example, the thickness of the second insulating layer 136 may be greater than the thickness of the first insulating layer 132 and the sacrificial layer 134.

Referring to FIG. 3B, a patterning process is performed by lithography and etching processes to form holes 138 in the second stacked structure 130, the conductive layer 120, and the first stacked structure 110. The hole 138 may also be referred to as a memory hole or a channel hole. The hole 138 exposes the bit line BL_B. From the top view shown in FIG. 1A, the shape of the hole 138 may be a circle, an ellipse, or the like. In some embodiments, a plurality of holes (not shown) are also formed in the second stack structure 130, the conductor layer 120, and the first stack structure 110 in the step area (not shown) of the substrate, and there is no position under the holes. Element line BL_B. These holes are used to form dummy pillars (as shown in FIG. 1A) to support the structure of the semiconductor device in the subsequent process to avoid layer or structure collapse.

Referring to FIGS. 3C to 3E, a process of forming a channel pillar CP in the hole 138 is performed. In some embodiments, the method for forming the channel column CP includes the following steps. First, a channel layer 150A and an insulating material 152A are formed on the second stack structure 130 and in the hole 138, as shown in FIG. 3C. The channel layer 150A conformally covers the second stack structure 130, the sidewall of the hole 138, and the top surface of the bit line BL_B, and is electrically connected to the bit line BL_B. The channel layer 150A includes a doped semiconductor material, an undoped semiconductor material, or a combination thereof. For example, the channel layer 150A may be formed by first forming an undoped polysilicon layer through a chemical vapor deposition process or a physical vapor deposition process, and then through a tempering process. The insulating material 152A covers the channel layer 150A and fills the hole 138. The insulating material 152A is, for example, silicon oxide, silicon nitride, silicon oxynitride formed by chemical vapor deposition, other suitable dielectric materials, or a combination thereof.

Referring to FIG. 3D, part of the insulating material 152A is removed to form an insulating core 152 in the hole 138. The removal process may use a single-stage etching process, a two-stage etching process, a multi-stage etching process, a chemical mechanical polishing process, or a combination thereof. The etching process can be, for example, anisotropic etching, isotropic etching, or a combination thereof. The top surface of the insulating core 152 is lower than the top surface of the second stack structure 130, and therefore, a groove (not shown) is provided on the top surface of the insulating core 152. Next, a conductive layer 154A is formed on the top surface of the second stacked structure 130 and in the groove above the insulating core 152. The conductive layer 154A is, for example, doped polysilicon, tungsten, platinum, or a combination thereof formed by a chemical vapor deposition process or a physical vapor deposition process.

3E, an etch-back or chemical mechanical polishing process is performed to remove the conductive material layer 154A on the top surface of the second stacked structure 130 to form a conductive plug 154 in the groove to complete the channel pillar CP Make. The channel pillar CP includes an insulating core 152, a conductive plug 154 and a channel layer 150. The insulating core 152 is located in the hole 138. The conductive plug 154 is located on the insulating core 152 and is electrically connected to the channel layer 150. The channel layer 150 is a conformal layer that surrounds the sidewalls of the insulating core 152 and the conductive plug 154, covers the bottom of the insulating core 152, and is electrically connected to the conductive plug 154, the bit line BL_B, and the conductor layer 120. The conductor layer 120 serves as the source line SL, or source S. In some embodiments, structures similar to the insulating core 152, the conductive plug 154, and the channel layer 150 are also formed in a plurality of holes (not shown) in the stepped area of the substrate to form dummy pillars. There is no bit line BL_B under the dummy column, and the dummy column is electrically disconnected from the bit line BL_B.

Referring to FIG. 3F, a stop layer 162 is formed on the second stack structure 130. The material of the stop layer 162 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or a combination thereof formed by CVD. In some embodiments, the stop layer 162 includes a material different from the material of the topmost second insulating layer 136. Next, a recess 164 is formed in the stop layer 162, the second stack structure 130, the conductor layer 120, and the first stack structure 110. In some examples, the depth of the recess 164 at least extends through the sacrificial layer 114, so that the bottom of the recess 164 exposes the first insulating layer 112.

Referring to FIG. 3F, an etching process is performed to remove the sacrificial layers 114 and 134 to form gate trenches 172 and 174. The etching method may adopt dry etching, wet etching or a combination thereof. In the embodiment where the sacrificial layers 114 and 134 are silicon nitride, phosphoric acid can be used as the etchant. During this stage of the process, the dummy pillars in the stepped area of the substrate can provide support for the structure during the process to avoid collapse of the layer or structure.

Referring to FIG. 3G, a charge storage structure 140A and a conductive layer 170 are formed on the exposed surfaces of the gate trenches 172 and 174 and the sidewalls of the recess 164. In an embodiment, the charge storage structure 140A may include a tunneling layer 142, a charge storage layer 144, and a blocking layer 146. The tunneling layer 142/charge storage layer 144/blocking layer 146 is, for example, a composite layer of oxide/nitride/oxide (ONO), or a composite layer formed of other materials. The charge storage structure 140A can also be, for example, a composite layer of oxide/nitride/oxide/nitride/oxide (ONONO), silicon/oxide/nitride/oxide/silicon (SONOS), aluminum oxide/oxide /Nitride/Oxide (Al ₂ O ₃ /O/N/O) or other suitable composite layers. The charge storage structure 140A can be formed by processes such as chemical vapor deposition, thermal oxidation, nitridation, and etching. The conductive layer 170 is formed of conductive materials such as doped polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide ( WSi _x ) or cobalt silicide (CoSi _x ).

Referring to FIG. 3H, an anisotropic etching process is performed to remove the conductor layer 170 and the charge storage structure 140A covering the top surface of the stop layer 162 and filling in the recess 164 to form the charge storage structure 140 And the gate G0 and the gate G1. The charge storage structure 140 includes a charge storage structure 140B and a charge storage structure 140T that are separated from each other.

The charge storage structure 140B and the gate G0 are formed in the gate trench 172. The charge storage structure 140B covers the top surface and the bottom surface of the gate electrode G0, and is located between the sidewall of the gate electrode G0 and the lower part of the outer sidewall of the channel pillar CP. The charge storage structure 140T and the gate G1 are formed in the gate trench 174. The charge storage structure 140T covers the top surface and the bottom surface of the gate electrode G1, and is located between the sidewall of the gate electrode G1 and the upper part of the outer sidewall of the channel pillar CP.

Referring to FIG. 3I, an insulating wall St is formed in the recess 164. The formation method of the insulating wall St is, for example, a chemical vapor deposition method or a spin coating method to form an insulating material layer on the stop layer 162, such as silicon oxide, spin-on glass, and the like. After that, using the stop layer 162 as a polishing stop layer or an etching stop layer, an etch-back process or a chemical mechanical polishing process is performed to remove the insulating material layer on the stop layer 162.

Referring to FIG. 3J, a via V1 is formed in the stop layer 162. The method for forming the via V1 is, for example, to form a via hole in the stop layer 162 by a photolithography etching method. Afterwards, a conductive material, such as doped polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), silicide, is formed on the stop layer 162 through a chemical vapor deposition process or a physical vapor deposition process. Tungsten (WSi _x ) or cobalt silicide (CoSi _x ). Thereafter, an etch-back process or a chemical mechanical polishing process is performed to remove the conductive material covering the surface of the stop layer 162.

After that, a bit line BL_T (drain D1) is formed on the stop layer 162. The method for forming the bit line BL_T is, for example, using chemical vapor deposition to form doped polysilicon, and then patterning through lithography and etching processes. The bit line BL_T is electrically connected to the channel pillar CP through the via V1.

The gate electrode G0, the charge storage structure 140B, the lower portion of the channel pillar CP, the drain electrode D0 and the source electrode S form a first memory cell M_B. The gate G1, the charge storage structure 140T, the upper portion of the channel pillar CP, the drain D1 and the source S form a second memory cell M_T. The second memory unit M_T is stacked on the first memory unit M_B. In addition, the charge storage structure 140B and the charge storage structure 140T are separated from each other and are not in physical contact with the source S. The charge storage structure 140B and the source electrode S are separated by a first insulating layer 116; the charge storage structure 140T and the source electrode S are separated by a first insulating layer 132.

In the foregoing embodiment, the channel pillar CP includes the insulating core 152, the conductive plug 154, and the channel layer 150, however, the embodiment of the present invention is not limited thereto. In other embodiments, the channel pillar CP may be formed of a solid doped semiconductor pillar 150B, as shown in FIGS. 4A and 4B. 3C and 4A, the method for forming the doped semiconductor pillar 150B is, for example, forming a doped semiconductor layer on the second stack structure 130, and the doped semiconductor layer also fills the hole 138. The doped semiconductor layer is, for example, doped epitaxial silicon. Thereafter, an etch-back process or a chemical mechanical polishing process is performed to remove the conductive material covering the surface of the stop layer 162. The memory element using such a solid doped semiconductor pillar 150B as the channel pillar CP is shown in FIG. 4B. 4B, the channel pillar CP is a solid doped semiconductor pillar 150B, which is in direct contact with and electrically connected to the bit line BL_B (drain D0), and is in direct contact with the via window V1 and directly passes through the via window V1 is electrically connected to the bit line BL_T, and there is no need to go through a conductive plug. The structure of the dummy post DP in the step area can be the same as the combined structure of the channel post CP, but the size can be the same or similar to the size of the memory hole (or channel hole).

In addition, referring to FIG. 1A, in some embodiments, the upper and lower sides of each channel pillar CP may be crossed by a single bit line BL_B and a single bit line BL_T. For example, the channel column CP of the memory cell group MCt0 is crossed by a single bit line BL0_B and a single bit line BL0_T. In other embodiments, the upper and lower sides of each channel column CP may be crossed by two bit lines BL_T and two bit lines BL_B (not shown) below them, as shown in FIG. 5.

Please refer to FIG. 5, the memory element includes a bit line BL_B (not shown) and a bit line BL_T. The bit line BL_B includes BL0_B, BL1_B... BL19_B (not shown). The bit line BL_T includes BL0_T, BL1_T... BL19_T. The bit lines BL0_T and BL1_T both cross the channel pillars CP1 and CP3 in the same row, and are within the width W1 defined by the channel pillar CP1 and the width W3 defined by the channel pillar CP3. The bit line BL0_T is electrically connected to the channel column CP1, but is not electrically connected to the channel column CP3. The bit line BL1_T is not electrically connected to the channel column CP1, but is electrically connected to the channel column CP3. The bit lines BL2_T and BL3_T both cross the channel pillars CP2 and CP4 in the same row, and are within the width W2 defined by the channel pillar CP2 and the width W4 defined by the channel pillar CP4. The bit line BL2_T is electrically connected to the channel column CP2, but is not electrically connected to the channel column CP4. The bit line BL3_T is not electrically connected to the channel column CP4; it is electrically connected to the channel column CP4. In other words, the vias V (such as V1 and V3) above the channel pillars CP (such as CP1 and CP3) in the same row are staggered in the first direction d1, but not aligned. The vias V (such as V1 and V5) above the channel pillars CP (such as CP1 and CP5) in the same row can be aligned or staggered in the second direction d2.

In other embodiments, the above-mentioned memory devices can also be made into three-dimensional memory devices by stacking.

6A, 6B, and 6C, the three-dimensional memory device 10' includes a multi-layer semiconductor layer T. In FIGS. 6B and 6C, two tier semiconductor layers T1 and T2 are used for illustration. However, the present invention is not limited to this, and the three-dimensional memory device 10' may include more semiconductor layers. For example, the three-dimensional memory element 10' may include 2 to 12 semiconductor layers T. The semiconductor layer T1 has a similar structure to the memory element 10 described above. However, for the sake of brevity, only two insulating walls St' (such as St0, St1) and a single block BLK' (such as BLK0') are drawn in FIGS. 6A, 6B, and 6C.

6A and 6B, the semiconductor layer T2 and the semiconductor layer T1 have a similar structure. The semiconductor layer T2 includes a plurality of memory cell groups MCt' (such as MCt0') in each block BLK' (such as BLK0') separated by a plurality of insulating walls St' (such as St0', St1') The structure and arrangement of M can be the same as or similar to the structure and arrangement of the multiple memory cell groups MCt in each block BLK. The semiconductor layer T2 includes a plurality of memory cell groups MCt'. Each memory cell group MCt' includes two superimposed third memory cells M_B' and fourth memory cells M_T' in the third direction d3.

6A, the semiconductor layer T2 further includes a plurality of bit lines BL_B' and a plurality of bit lines BL_T' extending in the first direction d1. The bit line BL_B' is, for example, a bit line including BL0_B', BL1_B', BL2_B', BL3_B', BL4_B', or more. The bit line BL_T' is, for example, a bit line including BL0_T', BL1_T', BL2_T', BL3_T', BL4_T', or more. Each bit line BL_B' of the semiconductor layer T2 is located on the bit line BL_T of the semiconductor layer T1, and each bit line BL_T' of the semiconductor layer T2 is located on the bit line BL_B'. The ends of the bit lines BL_B and BL_T of the semiconductor layer T1 and the ends of the BL_B' and BL_T' of the semiconductor layer T2 may be stepped. The bit line BL_B is connected to the metal layer ML through the bit line contact BLC0. In this embodiment, the bit lines BL_T and BL_B' can be shared, and they can be connected to the metal layer ML via the bit line contact window BLC2. The bit line BL_T' is connected to the metal layer ML through the bit line contact BLC3.

6A and 6C, the semiconductor layer T2 further includes a word line WL00', a word line WL01' and a source line SL0' extending in the second direction d2. In the second region R2, the end of the word line WL00 of the semiconductor layer T1 is connected to the metal layer ML via the word line contact WLC0. The end of the word line WL01 is connected to the metal layer ML through the word line contact WLC1. The end of the source line SL0 is connected to the metal layer ML via the source line contact SLC. The end of the word line WL00' of the semiconductor layer T2 is connected to the metal layer ML via the word line contact WLC0'. The end of the word line WL01' is connected to the metal layer ML via the word line contact WLC1'. The end of the source line SL0' is connected to the metal layer ML via the source line contact SLC'.

The end of the word line WL00, the end of the source line SL0, the end of the word line WL01, the end of the word line WL00', the end of the source line SL0', and the end of the word line WL01' are set in the block BLK0 The second area R2 may be stepped. In addition, a plurality of dummy pillars DP' may be included in the second region R2 to provide structural support during the manufacturing process and avoid collapse of the layer or structure. The structure of the dummy post DP' may be similar to that of the dummy post DP.

FIG. 7 illustrates the equivalent circuit diagram of FIG. 6C. 6C and FIG. 7, the memory cell M_B includes a gate G0, a source S, a drain D0, a charge storage structure 140B, and a channel pillar CP. The memory cell M_T includes a gate G1, a source S, a drain D1, a charge storage structure 140T, and a channel pillar CP. The memory cell M_B' includes a gate G0', a source S', a drain D0', a charge storage structure 140B', and a channel pillar CP'. The memory cell M_T' includes a gate G1', a source S', a drain D1', a charge storage structure 140T', and a channel pillar CP'. The memory cell M_B' and the memory cell M_T' share the source S'. The drain D0' of the memory cell M_B' is shared with the drain D1 of the memory cell M_T. The charge storage structure 140B' and the charge storage structure 140T' are separated from each other, and they are collectively referred to as the charge storage structure 140'.

The method for manufacturing the three-dimensional memory element 10' can form the semiconductor element 10 according to the above-mentioned method to complete the production of the first semiconductor layer T1. Afterwards, the production of the second semiconductor layer T2 can be completed by performing a cyclic manufacturing process. The at least one cycle process includes repeating the steps of forming the first stacked structure 110, the conductor layer 120, and the second stacked structure 130 in FIG. 3A to forming a plurality of bit lines BL_T in FIG. 3J, and/or according to FIGS. 4A and 4B .

In summary, the NOR flash memory device of the present invention includes two memory cells stacked vertically in a unit area, which can effectively utilize the area of the substrate. The three-dimensional NOR flash memory device of the present invention may include a plurality of memory cells stacked vertically in a unit area, which can effectively utilize the area of the substrate. In addition, the manufacturing process of the NOR flash memory device and the three-dimensional NOR flash memory device of the present invention can be compatible with existing manufacturing processes.

10: memory element 10': three-dimensional memory element 146: barrier layer 100: substrate 102: dielectric layer 110: first stacked structure 112, 132: first insulating layer 114, 134: sacrificial layer 116, 136: second insulating layer 120: Conductor layer 170: Conductor layer 130: Second stack structure 138: Hole 140, 140A, 140', 140B, 140T, 140B', 140T': Charge storage structure 142: Tunneling layer 144: Charge storage layer 146: Blocking Layers 150, 150A: channel layer 150B: semiconductor pillar 152: insulating core 152A: insulating material 154: conductive plug 154A: conductive layer 162: stop layer 164, 164S: recess 168: source line trench 172, 174: gate Ditch BL_B, BL0_B, BL1_B, BL2_B, BL3_B, BL4_B, BL5_B, BL6_B, BL7_B, BL8_B, BL9_B, BL_B', BL0_B', BL1_B', BL2_B', BL3_B', BL4_B', BL3_B', BL4_B', BL3_B', BL4_B', BL3_B', BL4_B', BL3_B', , BL4_T, BL5_T, BL6_T, BL7_T, BL8_T, BL9_T, BL_T', BL0_T', BL1_T', BL2_T', BL3_T', BL4_T': bit lines BLK, BLK0, BLK1, BLK', BLK0': block CP, CP1, CP2, CP3, CP4, CP5: channel column d1: first direction d2: second direction d3: third direction D0, D1, D0', D1': drain DP, DP': dummy column G0, G0' , G1, G1': gate ML: metal layer M_B, M0 ₁₁ _B, M0 ₁₂ _B, M0 ₁₃ _B, M1 ₁₁ _B, M1 ₁₂ _B, M1 ₁₃ _B, M_B': first memory cell M_T, M0 ₁₁ _T , M0 ₁₂ _T, M0 ₁₃ _T, M1 ₁₁ _T, M1 ₁₂ _T, M1 ₁₃ _T, M_T': second memory unit MCt, MCt0, MCt1, MCt', MCt0': memory unit group R1: first area R2: The second area S, S': source SL0, SL1, SL0': source line SLC, SLC': source line contact window St, St0, St1, St2, St', St0', St1': insulating wall T , T1, T2: semiconductor layer V1, V2, V3, V4, V5, V1', V2': via WL, WL00, WL01, WL10, WL11, WL', WL00', WL01': word line WLC0, WLC1, WLC0', WLC1': character line contact window W1, W2, W3, W4: width

FIG. 1A is a top view of a memory device according to an embodiment of the invention. Fig. 1B is a cross-sectional view taken along the line B-B' of Fig. 1A. Fig. 1C is a cross-sectional view taken along the line C-C' of Fig. 1A. Fig. 2 is a partial equivalent circuit diagram of Fig. 1A. 3A to 3J are schematic cross-sectional views of a manufacturing process of a memory device according to an embodiment of the invention. 4A to 4B are schematic cross-sectional views of a partial manufacturing process of a memory device according to another embodiment of the present invention. Fig. 5 is a top view of a memory device according to other embodiments of the present invention. Fig. 6A is a top view of a three-dimensional memory device according to an embodiment of the present invention. Fig. 6B is a cross-sectional view taken along the line B-B' of Fig. 6A. Fig. 6C is a cross-sectional view taken along the line C-C' of Fig. 6A. Fig. 7 is an equivalent circuit diagram of Fig. 6C.

102: Dielectric layer

140, 140B, 140T: charge storage structure

BL_B, BL0_B: the first bit line

BL_T, BL0_T: the second bit line

D0, D1: drain

CP: Channel column

G0: Gate

G1: Gate

M_B, M0 ₁₁ _B: the first memory unit

M_T, M0 ₁₁ _T: the second memory unit

MCt, MCt0: memory cell group

S: source

SL0: source line

St0: insulated wall

V1: Interlayer window

WL00, WL01: Character line

Claims (10)

A memory element includes: at least one semiconductor layer located above the dielectric layer, the at least one semiconductor layer includes: a first bit line and a second bit line, wherein the first bit line is located on the dielectric layer On the layer, the second bit line is located above the first bit line; the first word line and the second word line are located between the first bit line and the second bit line; source Polar line, located between the first word line and the second word line; channel pillar, penetrating the first word line, the source line and the second word line, and and The first bit line, the source line, and the second bit line are connected; a first charge storage structure surrounds the top surface and the bottom surface of the first word line and is located between the first Between the sidewalls of the word line and the lower part of the sidewall of the channel pillar; and a second charge storage structure, which surrounds the top and bottom surfaces of the second word line and is located between the sidewalls of the second word line And the upper part of the sidewall of the channel column; wherein the first character line, the first charge storage structure and the channel column form a first memory cell; the second character line, the The second charge storage structure and the channel pillar form a second memory cell. The memory element according to claim 1, wherein the channel pillar includes an insulating core, a conductive plug, and a channel layer surrounding the sidewalls of the insulating core and the conductive plug and the bottom of the insulating core. The memory element according to claim 1, wherein the source line is located between the first charge storage structure and the second charge storage structure, and is connected to the first charge storage structure and the second charge storage structure. The storage structures are separated from each other. The memory element according to claim 1, wherein the at least one semiconductor layer includes a first semiconductor layer and a second semiconductor layer located above the first semiconductor layer, and the first bit line of the second semiconductor layer is connected to The second bit line of the first semiconductor layer is shared. The memory device according to claim 1, further comprising a word line contact window extending downwardly through the second charge storage structure and contacting the end of the top surface of the second word line. The memory element according to claim 1, further comprising: another channel column arranged in the same row as the channel column; and a third bit line arranged in parallel with the second bit line, wherein the first bit line The three-bit line and the second bit line cross the channel column and the other channel column, and are between the width defined by the channel column and the other width defined by the another channel column Inside. The memory element according to claim 6, wherein the another channel column is electrically connected to the third bit line, and the channel column is electrically connected to the second bit line. The memory element according to claim 7, wherein the another channel column is electrically disconnected from the second bit line, and the channel column is electrically disconnected from the third bit line. A method for manufacturing a memory element includes: forming a first bit line on a dielectric layer; and at least one cycle process, the at least one cycle process includes: on the first bit line and the dielectric layer A first stacked structure, a conductive layer, and a second stacked structure are formed, wherein the first stacked structure and the second stacked structure each include a first insulating layer, a sacrificial layer, and a second insulating layer from bottom to top, so The conductor layer is used as a source line; a hole is formed through the second stack structure, the conductor layer, and the first stack structure; a channel column is formed in the hole, and the channel column is connected to the first stack structure. A bit line; forming a slit in the second stacked structure, the conductor layer, and at least a part of the first stacked structure; removing the second stacked structure and the second stacked structure exposed by the slit The sacrificial layer of the first stack structure to form a first character line trench and a second character line trench, wherein the first character line trench and the second character line trench expose the channel pillar Sidewall; forming a first charge storage structure to cover the top and bottom surfaces of the first character line trench and the sidewall of the channel layer, and forming a second charge storage structure to cover The top and bottom surfaces of the second character line trench and the sidewalls of the channel layer; forming a first character line in the first character line trench, and forming a first character line in the second character line trench A second character line is formed in the groove; an insulating material is filled in the recess; and a second bit line is formed above the second stack structure, and the second bit line is electrically connected to the channel pillar , Wherein the first word line, the first charge storage structure and the channel pillar form a first memory cell; the second word line, the second charge storage structure and the channel pillar form a first memory cell Two memory unit. The method of manufacturing a memory element according to claim 9, wherein the recess extends at least to the first insulating layer of the first stack structure.

Images