TWI718889B - Method for improving read retry of flash memory and related controller and storage device - Google Patents

Abstract

A method for use in management of a plurality of memory units of a flash memory module is provided. The method includes: performing error detection on at least one part of each second memory units that have been written with data; and performing a second refresh operation according to a result of the error detection, including when the result of error detection indicates a number of error bits included in at least one part of a second memory unit is greater than a threshold; reading data stored in a first memory unit comprising the second memory unit and correcting the data and programming the corrected data into another first memory unit; generating a programed timestamp corresponding to the another first memory unit.

Description

Method, controller and related storage device for improving read retry of flash memory

The present invention relates to flash memory, in particular to a method for improving the read retry of flash memory and related controllers and related storage devices.

In recent years, the use of flash memory has become more and more popular, especially on various mobile devices. The reason is that compared to other traditional storage devices, flash memory has the characteristics of high speed, high density, and non-volatility. However, despite the above-mentioned advantages of flash memory, there are still defects that have to be addressed, that is, service life and data retention (Data Retention). The memory unit (for example, block) in the flash memory often encounters errors after a certain number of uses, resulting in the inability to read the correct data. Among them, the cause of the error is mainly related to the number of erase cycles (Program/Erase Cycles) and the data storage time. Generally speaking, the flash memory has a higher error rate after more erasing times, or when the stored data has not been updated for a long time. Therefore, the controller often needs to read and retry the flash memory, and adjust the read voltage to improve the chance of correctly reading the data. However, during the read retry process, a variety of different read voltage combinations may be tried according to the above-mentioned erasing times and data storage time to correctly read the data. However, such a process will increase the delay and reduce the reading efficiency.

In view of the above-mentioned problems, the present invention provides a management mechanism for flash memory devices to improve read retry. Among them, the method of the present invention reduces the influence of data storage time on read retries by periodically refreshing the data stored in the memory cell in the flash memory. In other words, the storage time of the data in the memory cell varies within a relatively small range, so the adjustment range of the read voltage in the read retry can be effectively reduced. On the other hand, the present invention also adds an error checking mechanism to conditionally refresh memory cells with an excessively high error rate, which can also reduce the burden of read retry operations.

An embodiment of the present invention provides a method for managing a plurality of memory cells in a flash memory module. The method includes: performing an error check on at least a part of each of the second memory cells in which data has been written; and performing a second refresh operation according to the result of the error check. Wherein, performing the second refresh operation includes: when the result of the error check indicates that the number of error bits contained in at least a part of a second memory cell is greater than a threshold value, reading that the second memory cell is included The data stored in the first memory cell of one of the cells is corrected and written to the other first memory cell; and a programming time stamp associated with the other first memory cell is established.

An embodiment of the present invention provides a controller for managing a plurality of memory cells of a flash memory. The controller includes: a storage unit and a processing unit. The storage unit is used to store a program code. The processing unit is coupled to the storage unit, and is used to read the program code from the storage unit to execute the program code to perform the following operations: Perform an error check at least in part; and perform a second refresh operation according to the result of the error check. Wherein, performing the second refresh operation includes: when the result of the error check indicates that the number of error bits contained in at least a part of a second memory cell is greater than a threshold value, reading that the second memory cell is included The data stored in the first memory cell of one of the cells is corrected and written to the other first memory cell; and a programming time stamp associated with the other first memory cell is established.

An embodiment of the present invention provides a storage device. The storage device includes: a flash memory module and a controller. The flash memory module includes a plurality of memory units. The controller is used to access the flash memory module and includes: a storage unit and a processing unit. The storage unit is used to store a program code. The processing unit is coupled to the storage unit, and is used to read the program code from the storage unit to execute the program code to perform the following operations: Performing an error check at least in part; and performing a second refresh operation according to the result of the error check, wherein performing the second refresh operation includes: when the result of the error check indicates at least one of a second memory cell When the number of error bits included in part is greater than a critical value, the data stored in one of the first memory cells including the second memory cell is read, and the data is corrected and written to another first memory cell. Memory cell; and establishing a programming timestamp associated with the other first memory cell.

In the following text, many specific details are described to provide readers with a thorough understanding of the embodiments of the present invention. However, those skilled in the art will understand how to implement the present invention without one or more specific details or using other methods or elements. In other cases, well-known structures, materials or operations will not be shown or described in detail, so as to avoid obscuring the core concept of the present invention.

In addition, any examples or explanations given in the specification should not be limited or defined by any vocabulary used therein. On the contrary, these examples or explanations should be considered as describing a specific embodiment, and only as an illustration. Those skilled in the art will understand that any vocabulary used in these examples or explanations will cover other embodiments given elsewhere in this specification. The terms used to indicate these non-limiting examples include, but are not limited to: "for example," "such as," "for example," "in one embodiment," and "in an example."

The processes and blocks in the flowcharts in the specification show the architecture, functions, and operations that can be implemented by the system, method, and computer software product based on various embodiments of the present invention. In this regard, each block in the flowchart or the functional block diagram may represent a module, section or part of the program code, which includes one or more executable instructions for implementing the specified logical function. In addition, each block in the function block diagram and/or flowchart, as well as the combination of blocks, can basically be realized by a dedicated hardware system that performs a specified function or action, or a combination of dedicated hardware and computer program instructions. . These computer program instructions can also be stored in a computer-readable medium, which can make a computer or other programmable data processing device work in a specific manner, so that the instructions stored in the computer-readable medium implement flowcharts and/or functional blocks The functions/actions specified by the squares in the figure.

Figure 1 is a schematic diagram of an embodiment of the present invention. As shown in the figure, the storage device 100 includes a controller 120 and a flash memory module 130, and is controlled by a host device 200 (the storage device 100 may even be a part of the host device 200). The host 200 may include at least one central processing unit (not shown), and control the operation of the host 200 by operating an operating system and an application program, and is linked with peripheral devices (not shown). The storage device 100 can be used to provide storage space for the host 200 to store program codes and data necessary for operating the operating system and various applications. Examples of the main control device 50 may include: a multifunctional mobile phone, a tablet, a wearable device, and a personal computer such as a desktop computer or a notebook computer. Examples of the storage device 100 may include (but are not limited to): a solid state drive (SSD) and various embedded storage devices (for example, an embedded storage device compliant with UFS or EMMC specifications).

The controller 120 can be used to access the flash memory module 130. In one embodiment, the flash memory module 130 may be a three-dimensional NAND-type flash (3D NAND-type flash), and may include at least one flash memory chip (Flash memory chip), but this is not Limitations of the present invention. Each flash memory chip includes a plurality of blocks, and the controller 120 performs data erasing operations on the flash memory module 130 in units of blocks. In addition, a block can record a specific number of data pages (Pages), and the controller 120 writes data to the flash memory module 130 in units of data pages.

The controller 120 may include a processing circuit such as a microprocessor 122 and a storage unit 124, such as a read only memory (ROM). The read only memory 124 is mainly used to store program codes and specific data, and the microprocessor 122 is used to execute program codes to control access to the flash memory module 130. In addition, the controller 120 may also include other interface logic, control logic, buffers, etc., to assist in implementing various operations described below. However, for the sake of brevity in the description, it is omitted here. After reading the following, those skilled in the art should be able to know how to use known circuits in combination with the circuit elements and structures disclosed in the text to implement various operations and related applications mentioned in the embodiments of the present invention.

In this embodiment, the host 200 can indirectly access the storage device 100 by sending a host command and a corresponding logical address to the controller 120. The controller 120 receives a main control command (read or write command) and a logical address, and translates the main control command into a memory operation command, and then controls the flash memory module 130 to read, write, and program with the operation command (Program), or erase (erase) the memory unit or data page (page) or block (block) of a specific physical address in the flash memory module 130. Furthermore, the controller 120 will also execute the program code 1242C and/or refer to the data in the storage unit 124 to execute a series of operations to implement the specific operations mentioned below.

For the read operation, if the controller 120 cannot read the correct data in one read operation, the controller 120 will read one or more read retry tables stored in the storage unit 124, according to the read The read voltage recorded in the retry table is taken, and the flash memory module 130 is controlled to read data with different read voltages, so as to correctly read the data required by the host 200.

In the present invention, the selection of the controller 120 for reading the retry table is related to the data storage time. The controller 120 establishes a programming time stamp corresponding to the first memory cell for the time information corresponding to the write operation of each first memory cell in the flash memory module 130. When the host 200 subsequently issues a read command, the controller 120 will select the read retry table according to the information in the programming time stamp and the system time. In one embodiment, the first memory unit may be a super block.

Please further refer to the example in Figure 2. In this example, it is assumed that the flash memory module 130 includes a plurality of first memory cells UNT1, UNT2, ... and UNTM (this is not a limitation of the present invention) of the same size, and there is data in the use history P1 Writing to the first memory unit UNT1, data is written into the first memory unit UNT2 in the use history P2, and data is written into the first memory unit UNT3 in the use history P3. Then, if in the use history P1, when the host 200 sends a read command to request to read the data in the first memory unit UNT1, the controller 120 will use the retry table to read RTAB1 for reading. If in the use history P2, when the host 200 sends a read command to read the data in the first memory unit UNT1, the controller 120 will use the read retry table to read RTAB2 for reading, and use the history P2 Inside, the read operation for the data in the first memory unit UNT2 will use the read retry table RTAB1 to read. If in the use history P3, when the host 200 sends a read command to read the data in the first memory unit UNT1, the first memory unit UNT2, and the first memory unit UNT3, the controller 120 will use the read command respectively. Retry tables RTAB3, RTAB2 and RTAB1 for reading. Among them, the read retry tables RTAB3, RTAB2, and RTAB1 are suitable for reading data with a long to short storage time in sequence.

In one embodiment, in order to reduce the number of read retry tables and improve the efficiency of read retry, the controller 120 will perform a programming time stamp corresponding to the first memory cell in the flash memory module 130. A first refresh operation performed globally and periodically. Please refer to the example in FIG. 3 to further understand the operation principle and influence of the first refresh operation of the present invention. As shown in the figure, it is assumed that the flash memory 130 includes first memory units UNT1 to UNTM (this is not a limitation of the present invention). The controller 120 maintains a refresh list RLIST in the storage unit 124, records the programming timestamps corresponding to each first memory unit, and sorts them according to the new and old to refresh.

Suppose, in the use process P1, the first memory units UNT1 and UNT4 are written with data; in the use process P2, the first memory units UNT2 and UNT5 are written with data; and in the use process P3, the first memory Data is written in units UNT6 and UNT8. Then, the controller 120 refreshes the first memory cell with data written in the previous use history in the current use history, and completes before the end of the current use history. For example, in this embodiment, the controller 120 is in the use history P2, and the controller 120 refreshes and refreshes the first memory cells UNT1 and UNT4 to which data was written in the previous use history P1 according to the order of the refresh list RLIST. The refresh operation is completed before the end of the use course P2; in the use course P3, the controller 120 refreshes the first memory cells UNT2 and UNT5 to which data was written in the previous use course P2 according to the order of the refresh list RLIST. And finish the refresh operation before the end of the use course P3. In the use course P4, the controller 120 refreshes the first memory cells UNT6 and UNT8 to which data was written in the previous use course P3 according to the order of the refresh list RLIST, and completes the refresh operation before the end of the use course P4 . In addition, the first memory cell newly written by the refresh operation will also be refreshed in the next usage history. For example, suppose that in the use course P2, for the refresh operation of the first memory units UNT1 and UNT4, data is moved to the first memory units UNT3 and UNT7, then in the use course P3, the first memory unit UNT3 and UNT7 will also be refreshed, and so on.

In this way, the data retention time of any first memory unit in the flash memory module 130 is only two usage history at the longest (assuming that the refresh is completed at the end of one usage history at the latest). Therefore, the storage unit 124 of the controller 120 only needs to store two read retry tables RTAB1 and RTAB2, which can cover all read errors caused by excessive storage time. For example, if you intend to read the data in the first memory unit UNT1 in the usage history P2, if the data in the first memory unit UNT1 has been moved to the first memory unit through the above refresh operation at this time When in UNT3, you only need to use the read retry table RTAB1 to read; also in the use history P2, when you intend to read the data in the first memory unit UNT4, if the data in the first memory unit UNT4 is If the data is not refreshed, it needs to be read with the read retry table RTAB2.

The above selection of the first refresh operation and read retry table can be summarized as the process shown in Figure 4, which includes the following steps:

Step 410: Create a programming time stamp corresponding to the first memory cell for the data writing time of each first memory cell;

Step 420: According to the programming time stamp of the first memory cell, select a corresponding read retry table to perform a read operation on the first memory cell; and

Step 430: Perform a first refresh operation according to the programming time stamp of the first memory cell in which data has been written.

Since steps 410 to 430 are simplified from the operations introduced in the foregoing embodiment, the description will not be repeated here.

In one embodiment, in order to increase the reliability of the data and ensure the success rate of read retry, a second refresh operation is additionally performed in addition to the first refresh operation. Among them, the flow of the second refresh operation is shown in Figure 5, including the following steps:

Step 510: Perform an error check on at least a part of each of the second memory cells in which data has been written; and

Step 520: When the result of the error check indicates that the number of error bits is greater than a critical value, read the data stored in the first memory unit including the second memory unit, and write the data after correction Into another first memory unit; and

Step 530: Create a programming time stamp of the other first memory cell.

Please further cooperate with the description of FIG. 6 to further understand how the embodiment of the present invention performs the second refresh operation. As shown in the figure, the flash memory 130 may include a plurality of second memory cells SUNT1, SUNT2,... And SNTQ of the same size. Each memory cell SUNT1~ SUNTQ may contain the same number of second sub-memory cells SSUNT1~SSUNTZ.

In step 510, the controller 120 performs an error check on at least a part of each of the second memory units SUNT1 to SUNTQ. Among them, in an embodiment, the controller 120 unit may select the second sub-memory unit SSUNT1 from the second memory unit SUNT1, select the second sub-memory unit SSUNT2 from the second memory unit SUNT2, ... and The second memory unit SNTQ selects the second sub-memory unit SSUNTQ for error checking. This selection method is to avoid causing uneven sampling. For example, if the sub-memory unit SSUNT1 or the sub-memory unit SSUNTQ is selected for inspection in each second memory unit, it may be because the sub-memory units with the same number are close in physical structure and have similar physical characteristics. It ignores other memory cells that have different physical characteristics and are prone to errors. In one embodiment, the second memory units SUNT1~SunTQ may be super pages, and the second sub-memory units SSUNT1~SSNTZ may be data pages.

In the present invention, the second refresh operation is conditional, that is, only when the selected second sub-memory unit fails the error check, the controller 120 will perform the second operation for the second memory unit containing the second memory unit. Refresh operation. In step 520, the controller 120 determines whether the error check is passed by checking whether the number of error bits of the selected second sub-memory unit exceeds a threshold value. If the result of the error check indicates that the number of error bits in at least a part of a second memory cell is greater than a threshold, the controller 120 reads the first memory cell including the second memory cell And write the data in the other first memory unit after calibrated. That is, if it is checked that the number of error bits in a certain data page in a super data page is too high, the data including the first super block of one of the second super data pages will be refreshed. And in step 530, a programming time stamp of the first memory cell is established. This is the second refresh operation of the present invention.

In this embodiment, the first memory unit that needs to be refreshed is inserted into the sorting of the refresh list RLIST stored in the storage unit 124 of the controller 120. Please refer to the description in Figure 7. As shown in FIG. 7, the controller 120 originally performs the first refresh operation according to the refresh list RLIST, and periodically performs the sequence of UNT2, UNT3, UNT4, and UNT6. In addition, error checks are also periodically performed at the same time. However, when the controller 120 finds that a certain checked second memory unit SUNT2 fails to pass the check at time T1, it will insert the corresponding first memory unit SUNT2 that contains the second memory unit SUNT2 into the refresh list RLIST. The refresh operation of the memory unit UNT3 is the second refresh operation, and at the time point T2, the refresh operation for the data in the first memory unit UNT3 is executed.

As mentioned above, the present invention periodically refreshes the first memory cell (such as a super block) where data has been written. And in each usage history, the memory unit written in the previous usage history is executed, thereby effectively reducing the number of read retry tables required. In addition, by periodically selecting parts of the second memory unit (such as data pages) for error checking, it is better to ensure that the number of read retry tables is reduced and the read retry can still be performed efficiently. test. In this way, the efficiency of read retry can be improved. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention should fall within the scope of the present invention.

100 storage devices 120 controller 122 Processing Unit 124 storage unit 130 flash memory module 130_1~130_N Flash memory chip UNT1~UNTM First memory unit SUNT1~ SUNTQ second memory unit SSUNT1~ SSUNTZ The second sub-memory unit 410~430, 510~530 Steps

Figure 1 shows the architecture of related storage devices, controllers and flash memory modules according to an embodiment of the present invention. Figure 2 explains how the present invention chooses to read the retry table. Figure 3 explains how the present invention performs the first refresh operation for the first memory cell. FIG. 4 is a flowchart related to the selection of the read retry table and the execution of the first refresh operation in the embodiment of the present invention. FIG. 5 shows a flowchart of the second refresh operation in the embodiment of the present invention. Fig. 6 explains the method of selecting the second sub-memory unit for error checking in the embodiment of the present invention. Fig. 7 explains the association between the first refresh operation and the second refresh operation in the embodiment of the present invention.

510~530 Steps

Claims (15)

A method for managing a plurality of memory cells in a flash memory module includes: Perform an error check on at least a part of each of the second memory cells in which data has been written; and Perform a second refresh operation according to the result of the error check, including: When the result of the error check indicates that the number of error bits contained in at least a part of a second memory cell is greater than a threshold value, it is read out that the number of error bits contained in one of the second memory cells is included. Store the data, and write the data to another first memory unit after calibration; and A programming time stamp associated with the other first memory cell is established. The method described in claim 1, which additionally includes: Establishing a programming time stamp corresponding to the first memory cell for the data writing time of each first memory cell; Provide a plurality of read retry tables, each of which corresponds to a specific length of time that has elapsed after the first memory is written or refreshed; According to the programming time stamp of the first memory cell, select a corresponding read retry table to perform a read operation on the first memory cell; and According to the programming time stamp of the first memory cell in which data has been written, a first refresh operation is performed. The method according to claim 2, wherein the step of performing the first refresh operation includes: For a plurality of first memory cells to which data has been written in a first use history, perform the first refresh operation in a second use history, wherein the second use history is after the first use history, and The first refresh operation completes the refresh of all the first memory cells whose data has been written in the first use history during the second use history. The method according to claim 3, wherein the step of selecting the corresponding read retry table includes: Select a first read retry table for the reading of the first memory unit to which data is written during the first use history; and A second read retry table is selected for the reading of the first memory cell whose data is written in the second usage history. The method according to claim 2, wherein the part for performing the first refresh operation includes: For each first memory unit: Read out the data stored in the first memory unit, and write the data to another first memory unit; and A programming time stamp of the other first memory cell is established. A controller for managing a plurality of memory units of a flash memory, including: A storage unit for storing a program code and a plurality of read retry tables, where each read retry table corresponds to a specific length of time that elapses after the memory unit is written or refreshed; and A processing unit, coupled to the storage unit, is used to read the program code from the storage unit to execute the program code, so as to perform the following operations: Perform an error check on at least a part of each of the second memory cells in which data has been written; and Perform a second refresh operation according to the result of the error check, where the second refresh operation includes: when the result of the error check indicates that at least a part of a second memory cell contains more than one bit error When the threshold value is reached, read the data stored in one of the second memory units, and write the data to the other first memory unit after correction; and create the other first memory unit A programming time stamp of a memory cell. The controller according to claim 6, wherein the processing unit executes the code to perform the following operations: Establishing a programming time stamp corresponding to the first memory cell for the data writing time of each first memory cell; According to the programming time stamp of the first memory cell, select a corresponding read retry table to perform a read operation on the first memory cell; and According to the programming time stamp of the first memory cell in which data has been written, a first refresh operation is performed. The controller according to claim 7, wherein the processing unit executes the code to perform the second use history in a second use history for a plurality of first memory units written in a first use history A refresh operation, wherein the second usage history is after the first usage history, and the first refresh operation is completed in the second usage history for all the first memories that have written data in the first usage history Unit refresh. The controller according to claim 8, wherein the processing unit executes the code to: Select a first read retry table for the reading of the first memory unit to which data is written during the first use history; and A second read retry table is selected for the reading of the first memory cell whose data is written in the second usage history. The controller according to claim 7, wherein the processing unit executes the program code for each first memory unit: reads out the data stored in the first memory unit, and writes the data to Another first memory cell; and establishing a programming time stamp of the another first memory cell. A storage device including: A flash memory module including a plurality of memory units; and A controller for accessing the flash memory module, including: A storage unit for storing a program code and a plurality of read retry tables, where each read retry table corresponds to a specific length of time that elapses after the memory unit is written or refreshed; and A processing unit, coupled to the storage unit, is used to read the program code from the storage unit to execute the program code, so as to perform the following operations: Perform an error check on at least a part of each of the second memory cells in which data has been written; and Perform a second refresh operation according to the result of the error check, where the second refresh operation includes: when the result of the error check indicates that at least a part of a second memory cell contains more than one bit error When the threshold value is reached, read the data stored in one of the second memory units, and write the data to the other first memory unit after correction; and create the other first memory unit A programming time stamp of a memory cell. The storage device according to claim 11, wherein the controller: Establishing a programming time stamp corresponding to the first memory cell for the data writing time of each first memory cell; According to the programming time stamp of the first memory cell, select a corresponding read retry table to perform a read operation on the first memory cell; and According to the programming time stamp of the first memory cell in which data has been written, a first refresh operation is performed. The storage device according to claim 12, wherein the controller performs the first refresh operation in a second use history for a plurality of first memory cells to which data has been written in a first use history, wherein The second usage history is after the first usage history, and the first refresh operation is to complete the refresh of all the first memory cells that have written data in the first usage history in the second usage history. The storage device according to claim 13, wherein the controller selects a first read retry table for reading the first memory unit whose data is written in the first use history; and To read the first memory unit whose data is written in the second use history, select a second read retry table. The storage device according to claim 12, wherein the controller for each first memory unit: reads out the data stored in the first memory unit, and writes the data to another first memory And establishing a programming time stamp of the other first memory cell, thereby completing the first refresh operation.

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