TWI711044B - Memory device and operating method thereof - Google Patents

Abstract

A memory device is provided. The memory device includes a plurality of memory cell blocks and a source voltage generator. Each of the memory cell blocks has at least one memory cell. The source voltage generator is coupled to the plurality of memory cell blocks and configured to cause a source voltage of the memory cell block to be a first voltage according to that a memory cell in each of the memory cell blocks is in a selected state and cause a source voltage of the memory cell block to be a second voltage according to that all memory cells in each of the memory cell blocks are in an unselected state, wherein an absolute value of the first voltage is less than an absolute value of the second voltage. In addition, an operating method of the memory device is also provided.

Description

Memory device and its operation method

The present invention relates to a memory device and an operation method thereof, and more particularly to a memory device and an operation method thereof that reduce data reading and writing errors.

With the advancement of electronic technology, electronic products have become important tools in people's lives. Similarly, in order to provide more functions and transmit more information, the capacity of memory devices in electronic products is also increasing. As the demand for capacity increases, the size of the memory array also increases.

However, when performing data reading and writing operations of a memory device, the sensing current is composed of an on current (Ion) and an off current (Ioff). Therefore, when the memory array has a large size, the turn-on current of the selected memory cell may be interfered by the accumulated turn-off current of the unselected memory cell, so that the subsequent circuit cannot recognize the correct logic, causing the memory Read and write error of the device. In addition, excessive turn-off current will also cause the deterioration of the threshold voltage margin.

The invention provides a memory device and an operation method thereof, which can reduce the shutdown current to reduce the error of data reading and writing.

The memory device of the present invention includes a plurality of memory cell blocks and a source voltage generator. Each memory cell block has at least one memory cell. The source voltage generator is coupled to a plurality of memory cell blocks, and is used for making the source voltage of the memory cell block the first voltage according to the selected state of a memory cell in each memory cell block. All memory cells in the cell block are not selected, so that the source voltage of the memory cell block is the second voltage, wherein the absolute value of the first voltage is less than the absolute value of the second voltage.

The operating method of the memory device of the present invention includes: providing a source voltage generator to make the source voltage of the memory cell block based on the selected state of a memory cell in each of the plurality of memory cell blocks Is the first voltage. And according to the unselected state of all the memory cells in each memory cell block, the source voltage of the memory cell block is the second voltage, wherein the absolute value of the first voltage is smaller than the absolute value of the second voltage.

Based on the foregoing, embodiments of the present invention provide a memory device and an operating method thereof. When a memory cell in a memory cell block is selected, the source voltage generator outputs a first voltage to the memory cell block Source terminals of all memory cells; when all memory cells in the memory cell block are not selected, the source voltage generator outputs a second voltage whose absolute value is greater than the first voltage to all memory cells in the memory cell block The source extreme. In this way, the shutdown current can be reduced to reduce data read and write errors and improve the deterioration of the threshold voltage margin.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention. 1, the memory device 100 includes a plurality of memory cell blocks and a source voltage generator 110, the source voltage generator 110 is coupled to the plurality of memory cell blocks, and each memory cell block has at least one memory Cell. The memory device 100 is, for example, a non-volatile memory, which is not limited by the present invention.

For ease of description, the memory device 100 of this embodiment includes a memory cell block 120, a memory cell block 130, and a memory cell block 140, but the number of memory cell blocks is not limited in the present invention. In addition, each memory cell block in this embodiment has two memory cells. The memory cell block 120 has a memory cell 121 and a memory cell 122. The memory cell block 130 has a memory cell 131 and a memory cell 132. The memory cell block 140 has a memory cell 141 and a memory cell 142, but the number of memory cells in a memory cell block is not limited by the present invention.

FIG. 2 shows a detailed flowchart of the operation method of the memory device according to an embodiment of the invention. The operating method 200 of the memory device in the embodiment in FIG. 2 is applicable to the memory device 100 in the embodiment in FIG. 1. Hereinafter, the operation method 200 of the memory device of the embodiment of FIG. 2 will be described in detail with reference to various components of the embodiment of FIG. 1.

First, the source voltage generator 110 makes the source voltage of the memory cell block the first voltage according to the selected state of a memory cell in each memory cell block (step S220). That is, when one memory cell in the memory cell block is selected, the source voltage generator 110 outputs the first voltage to the source terminals of all the memory cells in the memory cell block. For example, referring to FIG. 1, if the memory cell 131 in the memory cell block 130 is in the unselected state and the memory cell 132 is in the selected state, the source voltage generator 110 outputs the source voltage Vs to the first voltage. Memory cell block 130. It is worth mentioning that the unselected state and the selected state of the memory cell will be further illustrated in FIG. 3.

Subsequently, the source voltage generator 110 sets the source voltage of the memory cell block to the second voltage according to the unselected state of all the memory cells in each memory cell block (step S240). In particular, the absolute value of the first voltage is smaller than the absolute value of the second voltage. That is, when all memory cells in the memory cell block are not selected, the source voltage generator 110 outputs a second voltage whose absolute value is greater than the first voltage to the source of all memory cells in the memory cell block. extreme. For example, referring to FIG. 1 again, if both the memory cell 121 and the memory cell 122 in the memory cell block 120 are not selected, the source voltage generator 110 outputs the source voltage Vs of the second voltage to the memory cell Block 120. Similarly, if both the memory cell 141 and the memory cell 142 in the memory cell block 140 are not selected, the source voltage generator 110 also outputs the source voltage Vs of the second voltage to the memory cell block 140.

Here, step S220 and step S240 can be performed at the same time or interchanged, and the sequence of steps described is only an implementation manner of this embodiment, and the present invention is not limited thereto.

FIG. 3 is a schematic diagram of a memory cell according to an embodiment of the invention. 3, the memory cell 300 includes a select transistor 310 and a floating gate transistor 320. The select transistor 310 has a first terminal N1, a second terminal N2, and a gate terminal G1. The floating gate transistor 320 has a third terminal. N3, the fourth terminal N4 and the gate terminal G2, the third terminal N3 of the floating gate transistor 320 is coupled to the second terminal N2 of the selection transistor 310, and the fourth terminal N4 is coupled to the bit line BL.

In this embodiment, the first terminal N1 receives the source voltage Vs, the gate terminal G1 receives the selection signal SEL, and the gate terminal G2 receives the control signal CRL. When the gate terminal G1 receives the selection signal SEL of the voltage 0, the memory cell 300 is in the unselected state; on the contrary, when the gate terminal G1 receives the selection signal SEL of the voltage Vcc, the memory cell 300 is in the selected state. It is worth noting that only one memory cell in the memory device 100 can be in the selected state, and the remaining memory cells are all in the unselected state.

4 is a schematic diagram of multiple memory cell blocks of a memory device according to an embodiment of the invention. Please refer to FIG. 4. The multiple memory cell blocks in FIG. 4 are similar to the multiple memory cell blocks in FIG. 1. The only difference between the two is that each memory cell block in FIG. 4 has at least two memory cells. However, the same as in FIG. 1, for ease of description, each memory cell block in this embodiment has two memory cells.

The following describes in detail the interconnection structure of memory cells in each memory cell block of this embodiment. Take the memory cell block 130 as an example. The memory cell block 130 has a memory cell 131 and a memory cell 132. The first end N11 of the select transistor 311 in the memory cell 131 is coupled to the first end of the select transistor 312 in the memory cell 132. N12 to jointly receive the source voltage Vs. The fourth terminal N41 of the floating gate transistor 321 in the memory cell 131 and the fourth terminal N42 of the floating gate transistor 322 in the memory cell 132 are both coupled to the bit line BL. The interconnection structure of the memory cells in the memory cell block 120 and the memory cell block 140 is the same as the interconnection structure of the memory cells in the memory cell block 130, which will not be repeated here.

In this embodiment, the memory cell 132 is in the selected state, and the remaining memory cells are in the unselected state. Therefore, in the memory cell block 130, the gate terminal G11 of the selection transistor 311 in the memory cell 131 receives the selection signal of voltage 0, and the gate terminal G12 of the selection transistor 312 in the memory cell 132 receives the selection signal of the voltage Vcc. The source voltage generator 110 outputs the source voltage Vs as the voltage V1 to the memory cell block 130. And in the memory cell block 120 and the memory cell block 140, the gate terminals of the selection transistors in the memory cell 121, the memory cell 122, the memory cell 141, and the memory cell 142 all receive the selection signal of voltage 0, and the source voltage is generated The device 110 outputs the source voltage Vs as the voltage V2 to the memory cell block 120 and the memory cell block 140.

It is worth mentioning that in this embodiment, the gate terminal G21 of the floating gate transistor 321 in the memory cell 131 and the gate terminal G22 of the floating gate transistor 322 in the memory cell 132 both receive the control signal of voltage 0. In addition, the gate terminals of the floating gate transistors in the memory cell 121, the memory cell 122, the memory cell 141, and the memory cell 142 also receive the control signal of the voltage 0. In addition, in this embodiment, the absolute value of the voltage V1 is smaller than the absolute value of the voltage V2.

In one implementation, the voltage V1 is 0 volts, and the voltage V2 is greater than 0 volts, so that the Vgs of the unselected memory cells (memory cell 121, memory cell 122, memory cell 141, and memory cell 142) are less than 0 volts and are strongly turned off Unselected memory cells (memory cell 121, memory cell 122, memory cell 141, and memory cell 142). Therefore, during data reading and writing operations of the memory device, the off current Ioff in the memory device can be reduced to improve the interference of the on current Ion of the selected memory cell by the accumulated off current Ioff of the unselected memory cell The situation also improves the deterioration of the threshold voltage margin, and improves the read and write accuracy of the memory device.

Please refer to FIG. 1 again. In one embodiment, when each memory cell block has at least two memory cells, the source voltage generator 110 includes a logic operation circuit 111. The logic operation circuit 111 targets the memory cell block 120 and the memory cell. The cell block 130 and the memory cell block 140 perform a logic operation to generate the source voltage Vs.

FIG. 5 is a schematic diagram of a logic operation circuit according to an embodiment of the invention. Please refer to FIG. 5, the logic operation circuit 500 includes a plurality of NOR gates and a plurality of multiplexers. However, in this implementation, only one inverted OR gate (inverted OR gate 510) and one multiplexer (multiplexer 520) are taken as examples. The inverter gate 510 is coupled to the memory cell block, and the multiplexer 520 is coupled to the inverter gate 510. The inverter 510 receives the selection signals of all the memory cells in each memory cell block (here, the selection signal SEL1 and the selection signal SEL2 are taken as examples), and outputs the control signal CL to the multiplexer 520. The multiplexer 520 selects the output voltage V1 or the voltage V2 to the source terminals of all the memory cells in the memory cell block according to the control signal CL.

In this embodiment, the logical operation may be an inverse OR logical operation. However, in another embodiment, the logical operation may also be a logical operation equivalent to the inverse OR logical operation, and the present invention is not limited. In addition, in this embodiment, the absolute value of the voltage V1 is smaller than the absolute value of the voltage V2. However, in other embodiments, when the logic operation is an OR logic operation, the absolute value of the voltage V1 may be greater than the absolute value of the voltage V2. In addition, in this embodiment, the multiplexer 520 can be designed through a hardware description language (Hardware Description Language, HDL) or any other digital circuit design method known to those with ordinary knowledge in the art, and is A multiplexer known to those with ordinary knowledge in the art.

In particular, the logic operation circuit of FIG. 5 can be applied to multiple memory cell blocks of the memory device of FIG. 4 to perform logic operations on the multiple memory cell blocks of FIG. 4 to generate the source voltage Vs.

It is worth mentioning that the memory device of the embodiment of the present invention may be a two-dimensional flash memory or a three-dimensional flash memory. Please refer to FIGS. 6 to 9 respectively. FIGS. 6 and 7 are schematic diagrams of a memory device with a two-dimensional architecture according to an embodiment of the present invention. 8 and 9 are schematic diagrams of a memory device with a three-dimensional architecture according to an embodiment of the present invention. It should be noted that FIGS. 6 to 9 illustrate a memory device with two memory cells per memory cell block.

In FIG. 6, the memory device 600 is a two-dimensional flash memory. The memory device 600 has word lines WL1 to WL6, bit lines BL1 to BL10, selection signal lines GSL1 to GSL6, and source lines SL1 to SL3. The word line WL1, the selection signal line GSL1, the source line SL1, the selection signal line GSL2, and the word line WL2 are vertically arranged in sequence. The source voltage generator 110 is used to generate a source voltage Vs to drive a plurality of source lines SL1 to SL3. In FIG. 6, at the interleaved positions of the bit line BL1 and the word line WL1, the selection signal line GSL1 and the source line SL1, memory cells, as well as the bit line BL1 and the source line SL1, the selection signal line GSL2 and At the interleaved position of the word line WL2, another memory cell can be provided. The two memory cells constitute a memory cell block in the memory device 600 and receive the source voltage Vs through the same source line SL1.

In this embodiment, the memory device 600 has a plurality of memory cell blocks, and the structures of the plurality of memory cell blocks are all as described above, and will not be repeated here. In addition, in this embodiment, the number of word lines, bit lines, select signal lines, and source lines is not as large as the number of word lines, bit lines, select signal lines, and source lines in the memory device 600 of FIG. 6 The number is limited.

FIG. 7 is a schematic side view of the memory device 600 and may also be a side view of the memory device 100. In FIG. 7, multiple N-type heavily doped regions (N+) are configured as the transistor in the memory cell 121, the transistor in the memory cell 122, the transistor in the memory cell 131, the transistor in the memory cell 132, and the memory cell 141. The source and drain of the transistor in the transistor and the memory cell 142. In addition, the logic operation circuit 500 of FIG. 5 is used to perform a logic operation on the memory cell block 120, the memory cell block 130, and the memory cell block 140 to generate the source voltage Vs. Specifically, the reverse OR gate 710, the reverse OR gate 720 and the reverse OR gate 730 are respectively coupled to the memory cell block 120, the memory cell block 130 and the memory cell block 140, the multiplexer 712, the multiplexer 722 and the multiplexer The worker 732 is respectively coupled to the reverse OR gate 710, the reverse OR gate 720 and the reverse OR gate 730. The inverter 710 receives the selection signal SEL11 of the memory cell 121 and the selection signal SEL12 of the memory cell 122 and outputs the control signal CS1. Then, the multiplexer 712 selects the output voltage V1 or the voltage V2 to the memory cell block 120 according to the control signal CS1. The source terminal of the middle memory cell 121 and the memory cell 122. Similarly, the inverter 720 receives the selection signal SEL21 of the memory cell 131 and the selection signal SEL22 of the memory cell 132 and outputs the control signal CS2. Then, the multiplexer 722 selects the output voltage V1 or the voltage V2 to the memory cell according to the control signal CS2. The source terminals of the memory cell 131 and the memory cell 132 in the block 130. The inverter 730 receives the selection signal SEL31 of the memory cell 141 and the selection signal SEL32 of the memory cell 142 and outputs the control signal CS3. Then, the multiplexer 732 selects the output voltage V1 or the voltage V2 to the memory cell block 140 according to the control signal CS3. The source terminal of the middle memory cell 141 and the memory cell 142.

In FIG. 8, the memory device 800 is a flash memory with a three-dimensional structure. The memory device 800 has word lines WL1 to WL3, bit lines BL1 to BL5, multiple selection signal lines GSL (not shown), and source lines SL1 and SL2. The source voltage generator 110 is used to generate a source voltage Vs to drive the source lines SL1 and SL2. Similar to FIG. 6, in FIG. 8, memory cells can be arranged at the interleaved positions of the bit line and the word line, the selection signal line and the source line.

In this embodiment, based on the three-dimensional architecture, the word lines WL1 to WL3 can be configured according to different height levels, respectively. The word lines WL1, WL2, and WL3 extend in the horizontal direction. The bit lines BL1 to BL5 can be arranged orthogonally to the word lines WL1 to WL3. In addition, in this embodiment, the number of word lines, bit lines, select signal lines, and source lines are not as large as the number of word lines, bit lines, select signal lines, and source lines in the memory device 800 of FIG. 8. The number is limited.

FIG. 9 is a schematic side view of the memory device 800. In FIG. 9, the bit line BL1 is located on the front side of the bit line BL2. In addition, a plurality of N-type heavily doped regions (N+) are configured as the source of the transistor in the memory cell. The drain of the transistor is coupled to the bit line through a vertical channel. In addition, the logic operation circuit 500 of FIG. 5 is used to perform a logic operation on a plurality of memory cell blocks to generate the source voltage Vs. Since the logic operation is similar to that of FIG. 7, it will not be repeated here.

FIG. 10 is a diagram showing the difference in improving the deterioration of the threshold voltage margin when the memory device performs data reading and writing operations according to an embodiment of the present invention. Referring to FIG. 10, in this embodiment, the memory device uses a source bias method to reduce the off current loff. In detail, when the size of the memory device becomes larger, the range of the threshold voltage Vt will change from the width W to the width W'. Therefore, the embodiment of the present invention selects the gate voltage Vg of the transistor in the memory cell to be equal to 0 volts, and the source voltage Vs is greater than 0 volts. Since Vgs is less than 0 volts, the threshold voltage Vt can be moved to the left to increase Over-drive, that is, to make the width Won and the width Woff become the width Won' and the width Woff' respectively, to reserve more margin for the higher turn-on current Ion, and greatly suppress the turn-off current Ioff to Improve the situation where the turn-on current Ion of the selected memory cell is interfered by the accumulated turn-off current Ioff of the unselected memory cell, and at the same time improve the situation where the threshold voltage margin deteriorates due to the increase in size, and improve the read and write accuracy of the memory device Sex.

In summary, the memory device and its operating method provided by the present invention select and output the first voltage to all memory cells in the memory cell block when there are memory cells in the selected state. Source terminal; when there is no memory cell in the selected state in the memory cell block, select and output a second voltage whose absolute value is greater than the first voltage to the source terminal of all memory cells in the memory cell block. In this way, the generation of the shutdown current can be suppressed to improve the interruption of the shutdown current, and at the same time improve the deterioration of the threshold voltage margin, and improve the accuracy of reading and writing of the memory device.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100, 600, 800: memory device

110: Source voltage generator

111, 500: logic operation circuit

120, 130, 140: memory cell block

121, 122, 131, 132, 141, 142, 300: memory cells

200: How to operate

310, 311, 312: select transistors

320, 321, 322: floating gate transistor

510, 710, 720, 730: reverse or gate

520, 712, 722, 732: multiplexer

BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8, BL9, BL10: bit lines

CRL, CS1, CS2, CS3: control signal

G1, G2, G11, G12, G21, G22: gate terminal

GSL1, GSL2, GSL3, GSL4, GSL5, GSL6: select signal line

Ioff: shutdown current

Ion: Turn on current

N1, N11, N12: first end

N2: second end

N3: third end

N4, N41, N42: the fourth end

S220, S240: steps

SEL, SEL1, SEL2, SEL11, SEL12, SEL21, SEL22, SEL31, SEL32: select signal

SL1, SL2, SL3: source line

V1, V2, Vcc: voltage

Vg: Gate voltage

Vs: source voltage

Vt: critical voltage

W, W’, Woff, Woff’, Won, Won’: width

WL1, WL2, WL3, WL4, WL5, WL6: character lines

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention. FIG. 2 shows a detailed flowchart of the operation method of the memory device according to an embodiment of the invention. FIG. 3 is a schematic diagram of a memory cell according to an embodiment of the invention. 4 is a schematic diagram of multiple memory cell blocks of a memory device according to an embodiment of the invention. FIG. 5 is a schematic diagram of a logic operation circuit according to an embodiment of the invention. 6 and 7 are schematic diagrams of a memory device with a two-dimensional structure according to an embodiment of the present invention. 8 and 9 are schematic diagrams of a memory device with a three-dimensional architecture according to an embodiment of the present invention. FIG. 10 is a diagram showing the difference in improving the deterioration of the threshold voltage margin when the memory device performs data reading and writing operations according to an embodiment of the present invention.

200: How to operate

S220, S240: steps

Claims (8)

A memory device includes: a plurality of memory cell blocks, each memory cell block has at least one memory cell; and a source voltage generator coupled to the plurality of memory cell regions Block for: making a source voltage of the memory cell block a first voltage according to a memory cell in each of the memory cell blocks as a selected state, according to each memory cell block All memory cells in the memory cell are not selected, so that the source voltage of the memory cell block is a second voltage, wherein the absolute value of the first voltage is smaller than the absolute value of the second voltage, wherein Each of the memory cell blocks has at least two memory cells, and the source voltage generator includes a logic operation circuit, wherein the logic operation circuit includes a plurality of inverted OR gates, and the plurality of inverted OR gates are respectively coupled Connected to the plurality of memory cell blocks, the plurality of inverters or gates respectively receive selection signals of the at least two memory cells in the plurality of memory cell blocks, and respectively output a plurality of control signals; and Multiplexers are respectively coupled to the plurality of inverters or gates, and the plurality of multiplexers respectively select and output the first voltage or the second voltage to the plurality of memory cells according to the plurality of control signals The source terminals of the at least two memory cells in the block. The memory device according to claim 1, wherein the logic operation circuit performs a logic operation on the plurality of memory cell blocks to generate all The source voltage. As for the memory device described in item 2 of the scope of patent application, the logical operation is an inverse OR logical operation. The memory device according to claim 2, wherein each of the at least two memory cells includes: a select transistor having a first end, a second end and a first gate terminal, and the first One end receives the source voltage, the first gate terminal receives the selection signal; and a floating gate transistor having a third terminal, a fourth terminal and a second gate terminal, the third The terminal is coupled to the second terminal, the fourth terminal is coupled to a bit line, and the second gate terminal receives a control signal. The memory device according to claim 4, wherein each memory cell block has a first memory cell and a second memory cell, wherein the first memory cell of the selection transistor in the first memory cell Terminal is coupled to the first terminal of the selection transistor in the second memory cell to jointly receive the source voltage, wherein the first terminal of the floating gate transistor in the first memory cell Both the four terminals and the fourth terminal of the floating gate transistor in the second memory cell are coupled to the bit line. The memory device according to the first item of the scope of patent application, wherein the memory device is a two-dimensional flash memory or a three-dimensional flash memory. An operating method of a memory device includes: Providing a source voltage generator to make a source voltage of the memory cell block a first voltage based on a memory cell in each memory cell block of the plurality of memory cell blocks being selected; and According to the unselected state of all the memory cells in each of the memory cell blocks, the source voltage of the memory cell block is a second voltage, wherein the absolute value of the first voltage is less than the For the absolute value of the second voltage, each of the memory cell blocks has at least two memory cells, and the step of providing the source voltage generator further includes providing a logic operation circuit, wherein the logic operation circuit is provided The steps further include providing a plurality of inverters to respectively receive the gate voltages of the at least two memory cells in the plurality of memory cell blocks, and respectively output a plurality of control signals; and providing a plurality of multiplexers To selectively output the first voltage or the second voltage to the source terminals of the at least two memory cells in the plurality of memory cell blocks respectively according to the plurality of control signals. According to the operation method described in claim 7, wherein the step of providing the logic operation circuit further includes providing the logic operation circuit to perform a logic operation on the plurality of memory cell blocks to generate the Source voltage.

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