TWI709212B - Wafer bonding structure and method of forming the same - Google Patents

Abstract

A wafer bonding structure and a method of forming the same are provided. The method includes forming a first wafer and bonding a second wafer to the bonding dielectric layer and the bonding pad of the first wafer. Forming the first wafer includes the following processes. A semiconductor structure is provided. The semiconductor structure has a first roll off region on the edge thereof. An additional dielectric layer is formed to fill the first roll off region. A bonding dielectric layer having an opening is formed on the semiconductor structure and the additional dielectric layer. A conductive layer is formed on the bonding dielectric layer and filled in the opening, wherein the conductive layer over the additional dielectric layer has a protrusion. A removal process is performed to remove the conductive layer on the bonding dielectric layer. The conductive layer remained in the opening form a bonding pad. The removal process includes a planarization process, and the protrusion is removed by the planarization process.

Description

Wafer bonding structure and its forming method

The embodiment of the present invention relates to a wafer bonding structure and a forming method thereof.

Due to the continuous increase in the accumulation density of various electronic components (for example, transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid growth. To a large extent, this increase in product density comes from the continuous reduction of the minimum feature size, which allows more and smaller components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize a smaller area than previous packages. Some smaller types of packages of semiconductor components include quad flat package (QFP), pin grid array (PGA) package, ball grid array (BGA) package, Flip chip (FC) packaging, three-dimensional integrated chip (3DIC), wafer level package (WLP) and package on package (PoP) devices, etc.

Three-dimensional integrated wafers provide increased integration density and other advantages due to the reduced length of interconnection lines between stacked wafers, such as faster speed and higher bandwidth. However, there are still many challenges to be dealt with for 3D integrated wafer technology.

According to some embodiments of the present disclosure, a method for forming a wafer bonding structure includes forming a first wafer and bonding a second wafer to a bonding dielectric layer and bonding pads of the first wafer. Forming the first wafer includes the following processes. A semiconductor structure is provided, and the edge of the semiconductor structure has a first sag area. An additional dielectric layer is formed to fill the first sag area. A bonding dielectric layer with openings is formed on the semiconductor structure and the additional dielectric layer. A conductive layer is formed on the bonding dielectric layer and filled into the opening, wherein the conductive layer above the additional dielectric layer has protrusions. A removal process is performed to remove the conductive layer located on the bonding dielectric layer, and the conductive layer remaining in the opening forms a bonding pad. The removal process includes a planarization process, and the bumps are removed by the planarization process.

According to other embodiments of the present disclosure, a method for forming a wafer bonding structure includes forming a first wafer and bonding a second wafer to the bonding structure of the first wafer. Forming the first wafer includes: providing a semiconductor structure; forming an additional dielectric layer on the side of the semiconductor structure; and forming a bonding structure on the semiconductor structure and the additional dielectric layer. The formation of the bonding structure includes the following processes. A bonding dielectric layer with openings is formed. A conductive layer is formed on the bonding dielectric layer and filled into the opening. A planarization process is performed to remove part of the conductive layer located above the bonding dielectric layer. An edge ball removal process is performed to remove residues of the conductive layer above the bonding dielectric layer after the planarization process, wherein the conductive layer remaining in the opening forms a bonding pad.

According to some embodiments of the present disclosure, a wafer bonding structure includes a first wafer and a second wafer. The first wafer includes an interconnect structure, a bonding structure, and an additional dielectric layer on the substrate. The bonding structure is located above the interconnection structure and is electrically connected to the interconnection structure. The additional dielectric layer is located on the side of the interconnect structure and between the bonding structure and the interconnect structure. The second wafer is bonded to the bonding structure of the first wafer.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of elements and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, forming the second feature "on" or "on" the first feature in the following description may include an embodiment in which the second feature and the first feature are formed in direct contact, and may also include An embodiment in which an additional feature may be formed between the second feature and the first feature, so that the second feature may not directly contact the first feature. In addition, the present disclosure may reuse reference numbers and/or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and/or configurations discussed.

In addition, for ease of description, this article may use, for example, "beneath", "below", "lower", "on )", "above", "upper" and other spatially relative terms are used to describe the relationship between one element or feature shown in the figure and another (other) element or feature. The terminology of spatial relativity is intended to encompass the different orientations of the device in use or operation in addition to the orientation shown in the figure. The device can have other orientations (rotated by 90 degrees or other orientations), and the terms of spatial relativity used herein can also be interpreted accordingly.

The disclosure may also include other features and manufacturing processes. For example, a test structure may be included to perform verification testing of three-dimensional packaging or three-dimensional integrated chip devices. The test structure may include, for example, test pads formed in the redistribution layer or on the substrate. The test pads can be used to test three-dimensional packages or three-dimensional integrated wafers, using probes and/or probe cards. card) etc. In addition, verification tests can also be performed on the intermediate structure and the final structure. In addition, the structure and method disclosed herein can be used in conjunction with a test method including intermediate verification of known good dies to improve yield and reduce cost.

1A to 1J show schematic cross-sectional views of a method for manufacturing a wafer and a wafer bonding structure according to a first embodiment of the present disclosure. FIG. 5A shows a schematic cross-sectional view of a wafer according to the first embodiment of the present disclosure. FIG. 5A shows in detail the components of the wafer shown in FIG. 1I.

Referring to FIG. 5A, in some embodiments, the wafer 50a includes a substrate 10, a plurality of integrated circuit components 11, an interconnect structure InC, an additional dielectric layer 17 and a bonding structure 28. The substrate 10 is a semiconductor substrate, such as a silicon substrate. For example, the substrate 10 is a bulk silicon substrate, a doped silicon substrate, an undoped silicon substrate, or a silicon-on-insulator (SOI) substrate. The dopants of the doped silicon substrate may be N-type dopants, P-type dopants, or a combination of N-type dopants and P-type dopants. The substrate 10 may also be formed of other semiconductor materials. The other semiconductor materials include, but are not limited to, silicon germanium, silicon carbide, gallium arsenide or the like.

The substrate 10 includes multiple active regions and isolation structures (not shown in the figure). A plurality of integrated circuit elements 11 are formed on the active area of the substrate 10. In some embodiments, the plurality of integrated circuit components 11 include active components, passive components or a combination thereof. In some embodiments, for example, the integrated circuit element 11 includes a transistor, a capacitor, a resistor, a diode, a photodiode, a fuse, or other similar elements.

The interconnect structure InC is formed on the substrate 10 and the integrated circuit element 11. In some embodiments, the interconnect structure InC includes a dielectric structure 12 and an interconnect 13. The internal wiring 13 is disposed in the dielectric structure 12, and is electrically connected to different integrated circuit components 11 to form a functional circuit. In some embodiments, the dielectric structure 12 includes multiple dielectric layers, for example, an inter-layer dielectric layer (ILD) and one or more inter-metal dielectric layers (ILD). IMD). In some embodiments, the material of the dielectric structure 12 includes oxide (such as silicon oxide), nitride (such as silicon nitride), oxynitride (such as silicon oxynitride), phosphosilicate glass (PSG). ), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG) and combinations thereof. In some embodiments, the interconnect 13 includes multiple layers of wires and plugs. The wires and plugs include conductive materials, such as copper, aluminum, tungsten, alloys thereof, or combinations thereof. The plug includes a contact window and a via window. The contact window is located in the inner dielectric layer and connects the metal wire and the integrated circuit component 11. The interlayer window is located in the intermetal dielectric layer and connects metal wires of different layers.

In some embodiments, the dielectric layer 14 and the conductive feature 16e are the top dielectric layer and the top conductive feature of the interconnect structure InC. That is, the dielectric layer 14 is the top dielectric layer of the dielectric structure 12. The conductive feature 16e is the top conductive feature of the interconnect 13 and may be referred to as a pad 16e. The bonding structure 28 is located on the inner wire connection structure InC, and is electrically connected to the pad 16e. The additional dielectric layer 17 is located at the edge of the interconnect structure InC and surrounds the interconnect structure InC. The material of the additional dielectric layer 17 may be the same as or different from the material of the dielectric structure 12. For example, it may include oxide (such as silicon oxide), nitride (such as silicon nitride), oxynitride (such as silicon oxynitride), Carbides (such as silicon carbide) or combinations thereof or other suitable dielectric materials.

1A to FIG. 1I are schematic cross-sectional views of the manufacturing method of the pad 16e, the additional dielectric layer 17 and the bonding structure 28 of the wafer 50a. For the sake of brevity, the integrated circuit element 11 in FIG. 5A and the interconnection structure InC between the pad 16e and the substrate 10 are not specifically shown in FIGS. 1A to 1I, and will be changed before the wafer manufacturing is completed. The wafer is labeled 50.

1A, a wafer 50 including a substrate 10 is provided. In some embodiments, the wafer 50 includes an inner region IR and an edge region ER. The edge region ER is the edge portion of the wafer 50 and surrounds the inner region IR of the wafer 50.

A dielectric layer 14 is formed on the substrate 10. The dielectric layer 14 is, for example, the top dielectric layer corresponding to the dielectric structure 12 shown in FIG. 5A. In some embodiments, the dielectric layer 14 includes oxide (such as silicon oxide), nitride (such as silicon nitride), oxynitride (such as silicon oxynitride), phosphosilicate glass (PSG), Borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG) and their combinations, etc. The dielectric layer 14 is made by spin-coating (spin-coating), chemical vapor deposition (CVD), flowable chemical vapor deposition (flowable CVD), plasma enhanced chemical vapor deposition (plasma -enhanced CVD, PECVD), atomic layer deposition or a combination of suitable deposition techniques.

The dielectric layer 14 is patterned to form a plurality of openings (or called grooves) 15. In some embodiments, the patterning method includes lithography and etching processes. For example, a photoresist layer is formed on the dielectric layer 14, and the photoresist layer is patterned by a photolithography process to form an opening in the photoresist layer corresponding to the position where the opening 15 is to be formed, exposing part The top surface of the dielectric layer 14. Then, using the patterned photoresist layer as a mask, the dielectric layer 14 exposed by the patterned photoresist layer is removed by an etching process. After that, the patterned photoresist layer is removed.

In some embodiments, the opening 15 can be, for example, a via, a trench, or a combination thereof. The cross-sectional shape of the opening 15 may be a square, a rectangle, an inverted trapezoid, or other suitable shapes. The side walls of the opening 15 may be straight, inclined or curved. This disclosure is not limited to this.

Please continue to refer to FIG. 1A, a conductive layer (or called a pad material layer) 16 is formed on the substrate 10. The conductive layer 16 covers the dielectric layer 14 and fills the opening 15. In some embodiments, the conductive layer 16 includes metal or metal alloy. For example, the conductive layer 16 may include copper, aluminum, tungsten, nickel, alloys thereof, or combinations thereof. In some embodiments, the method for forming the conductive layer 16 includes sputtering, chemical vapor deposition, physical vapor deposition, electrochemical plating (ECP), electroplating, electroless plating, or a combination thereof. However, this disclosure is not limited to this.

In some embodiments, the conductive layer 16 has an uneven top surface. For example, the conductive layer 16 located in the edge region ER of the wafer 50 protrudes from the conductive layer 16 located in the inner region IR. In other words, the conductive layer 16 has a main body portion 16a and an edge portion 16d. The main body portion 16 a is located directly above the inner region IR substrate 10. The edge portion 16d is located directly above the edge area ER substrate 10 and surrounds the main body portion 16a. In some embodiments, the main body portion 16a has a substantially flat top surface, and the top surface of the edge portion 16d protrudes from the top surface of the main body portion 16a. The top surface of the edge portion 16d may be uneven, such as an arc shape, a spur shape, or the like. In some embodiments, the edge portion 16d is a convex ball, but the disclosure is not limited to this. In other words, the edge portion 16d has a protrusion, and the protrusion is a portion of the edge portion 16d protruding from the top surface of the main body portion 16a.

4A shows an enlarged cross-sectional view of a part of the main body portion 16a and the edge portion 16d of the conductive layer 16 in the wafer 50. For brevity, the dielectric layer 14 is not shown in FIG. 4A. 4A, in some embodiments, the conductive layer 16 includes a barrier layer 70, a seed layer 71, and a metal layer 72. The barrier layer 70 may include a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), a combination thereof, or the like. The seed layer 71 may be a copper seed layer or other suitable metal seed layer. The material of the seed layer 71 may include titanium, tantalum, copper, combinations thereof, or the like. The seed layer 71 may be a single layer or a multilayer structure. In some embodiments, the seed layer 71 has a two-layer structure, including a titanium layer and a copper layer on the titanium layer. The formation method of the seed layer 71 includes physical vapor deposition (PVD), such as sputtering.

The metal layer 72 may be a suitable metal or metal alloy. In some embodiments, the metal layer 72 is a copper layer, which is formed by an electroplating process. For example, after the seed layer 71 is formed, the wafer to be plated with the copper metal layer 72 is placed in an electrolyte (for example, a copper sulfate solution), and the negative electrode 75 connected to the negative electrode of the power supply is connected to the crystal of the wafer. Seed layer 71, and place the positive electrode (for example, copper electrode) connected to the positive electrode of the power source in the electrolyte. During the electroplating process, the metal copper of the positive electrode loses electrons and becomes copper ions (Cu ²⁺ ) and dissolves in the electrolyte. The copper ions in the electrolyte obtain electrons at the negative electrode 75, and then in the crystal connected to the negative electrode 75 Copper is deposited on the surface of the circle to form a copper metal layer 72 on the seed layer 71.

FIG. 4B shows a top view of the negative electrode 75 and the wafer 50. 4A and 4B, in some embodiments, the negative electrode 75 has a ring shape and is placed on the seed layer 71 on the edge of the wafer 50. Since the negative electrode 75 needs to be placed on the seed layer 71 at the edge of the wafer, the metal layer 72 is not formed in the area occupied by the negative electrode 75. Therefore, the metal layer 72 is formed in the ring-shaped area surrounded by the inner side wall of the negative electrode 75.

In other words, the metal layer 72 is formed on the seed layer 71 and covers a part of the surface of the seed layer 71. In some embodiments, part of the seed layer 71 near the edge of the wafer is not covered by the metal layer 72. Although the barrier layer 70 and the seed layer 71 extend to the edge of the wafer, the metal layer 72 only covers a part of the seed layer 71 that extends to the edge of the wafer, so that the seed layer 71 that extends to the edge of the wafer The other part is not covered by the metal layer 72. In some embodiments, the edge ER of the wafer 50 has a flat area P and a rounded area S. The plane area P has a flat surface, or has a relatively flat surface relative to the round corner area S. The surface of the plane area P is substantially flush with the surface of the inner area of the wafer. The rounded corner area S has, for example, an arc-shaped or circular surface. In some embodiments, the barrier layer 70 and the seed layer 71 extend to the plane area P covering the edge ER of the wafer, but do not extend to the fillet area S of the wafer, but the disclosure is not limited thereto. In other embodiments, the barrier layer 70 and the seed layer 71 not only extend to the plane area P covering the wafer, but also extend to the fillet area S covering the wafer.

4A, in other words, the conductive layer 16 includes a barrier layer 70, a seed layer 71, and a metal layer 72, and can be divided into a main portion 16a and an edge portion 16d. The edge portion 16d includes a convex portion 16b and a concave portion 16c. The main body portion 16a includes a barrier layer 70a, a seed layer 71a, and a metal layer 72a. The protrusion 16b includes a barrier layer 70b, a seed layer 71b, and a metal layer 72b. In some embodiments, the metal layer 72a of the main body portion 16a has a substantially flat top surface, and the top surface of the metal layer 72b of the convex portion 16b protrudes from the top surface of the metal layer 72a of the main body portion 16a, and may be uneven. . In some embodiments, the height of the top surface of the metal layer 72b gradually increases away from the main portion 16a, but the disclosure is not limited thereto. The recessed portion 16c includes a barrier layer 70c and a seed layer 71c, and does not have a metal layer, so its top surface is recessed and lower than the top surfaces of the main body portion 16a and the convex portion 16b. In other words, the edge portion 16d of the conductive layer 16 has a recess RC at a position closest to the edge of the wafer, and the recess RC is located above the recess portion 16c.

Referring back to FIGS. 1A to 1B, after the conductive layer 16 is formed, the positive electrode and the negative electrode 75 are removed. Thereafter, a removal process is performed to remove the edge portion 16d of the conductive layer 16. This removal process causes a recess RC' to be formed in the edge region ER of the wafer, that is, the edge of the conductive layer 16. In some embodiments, the removal process includes an Edge Beed Removal (EBR) process. For example, the EBR process includes spraying an etchant onto the edge portion 16d of the conductive layer 16 using a nozzle to remove the edge portion 16d by etching. In some embodiments, the nozzle can be arranged at a fixed position above the edge portion 16d, and the wafer 50 can rotate with its centerline as the axis. As the wafer 50 rotates, the etchant can be sprayed to the entire edge portion 16d, thereby moving Except for the edge portion 16d, this disclosure is not limited to this. In some embodiments, the etchant includes, for example, a combination of sulfuric acid, hydrogen peroxide, and deionized water or the like. The etchant has a high etching selection ratio between the conductive layer and the dielectric layer, and substantially does not damage the underlying dielectric layer 14. The EBR process removes at least the protruding portion protruding from the edge portion 16d of the main body portion 16a of the conductive layer 16. In some embodiments, the edge portion 16d of the conductive layer 16 is partially removed, but the disclosure is not limited to this. In other embodiments, the edge portion 16d is completely removed.

FIG. 4C shows a partial enlarged view of the conductive layer 16 after the EBR process. 4A and 4C, in some embodiments, the edge portion 16d is partially removed, leaving the edge portion 16d'. In some embodiments, the height of the top surface (or surface) of the edge portion 16d' is lower than the height of the top surface of the main body portion 16a, and gradually decreases as it moves away from the main body portion 16a. For example, the EBR process removes part of the metal layer 72b of the protrusion 16b, part of the seed layer 71b, and the seed layer 71c of the recess 16c, leaving the protrusion 16b' and the recess 16c'. The protrusion 16b' includes a barrier layer 70b, a seed layer 71b', and a metal layer 72b'. In some embodiments, the top surface of the metal layer 72b' of the convex portion 16b' is not higher than the top surface of the metal layer 72a of the main body portion 16a. In other words, the top surface of the metal layer 72b' of the convex portion 16b' may be lower than or substantially flush with the top surface of the metal layer 72a of the main portion 16a, and the height of the top surface of the metal layer 72b' gradually increases away from the main portion 16a. Decrease, but this disclosure is not limited to this. In other embodiments, part of the top surface of the metal layer 72b' may also be slightly higher than the top surface (not shown) of the metal layer 72a of the main portion 16a. In some embodiments, the seed layer 71c of the recess 16c is completely removed, and the recess 16c' includes the barrier layer 70c. In some embodiments, the barrier layer 70c is not removed in the EBR process, but the disclosure is not limited thereto. As shown in FIGS. 4A and 4C, the EBR process expands the (smaller) recess RC range of the conductive layer 16 and forms a (larger) recess RC'. The sidewall of the recess RC' exposes the seed layer 71b' and the metal layer 72b' of the convex portion 16b'; the bottom of the recess RC' exposes the barrier layer 70c.

Please refer to FIG. 1B to FIG. 1C, and then perform a planarization process to remove the conductive layer 16 on the top surface of the dielectric layer 14. After the planarization process, the conductive layer 16e remaining in the opening 15 of the dielectric layer 14 forms the top conductive feature (or called the pad) of the interconnect structure InC. The top surface of the pad 16e is substantially flush with the top surface of the dielectric layer 14. In some embodiments, the barrier layer 70c (FIG. 4C) of the conductive layer 16 serves as a stop layer for the planarization process, and then the barrier layer 70c above the dielectric layer 14 is removed. In some embodiments, the planarization process includes, for example, a chemical mechanical polishing (CMP) process.

1B, 1C, and 4C, during the planarization process, since the conductive layer 16 has a recess RC' in the edge region ER, the planarization process will not only remove the barrier layer 70c at the bottom of the recess RC', but may also A portion of the dielectric layer 14 under the barrier layer 70c (ie, under the recess RC') is removed. In other words, during the planarization process, the dielectric layer 14 located in the edge region ER may be damaged and roll off.

In some embodiments, the method of forming other metal features and the dielectric layer of the interconnect structure under the top conductive feature 16e and the dielectric layer 14 is similar to the method of forming the pad 16e and the dielectric layer 14, for example, including patterns. The dielectric layer is electroplated to form a conductive layer, an EBR process is performed to remove edge protrusions, and then a planarization process is performed to remove the conductive layer above the dielectric layer. The EBR process can ensure that no excess conductive layer remains in the edge area of the wafer after the planarization process. However, since the EBR process will form a large depression at the edge of the conductive layer, the planarization process will damage the dielectric layer under the conductive layer, and cause the dielectric layer to collapse. The sag will gradually accumulate at the edge of the dielectric structure during the formation of each layer of the interconnection. That is to say, in some embodiments, before the dielectric layer 14 is formed in FIG. 1A, the edge of the dielectric layer of the interconnect structure InC located under the dielectric layer 14 has collapsed. Shows.

Please refer to FIG. 1C and FIG. 5A. The dashed line in FIG. 1C exemplarily shows the sag area RO1 accumulated during the formation of the interconnect 13 (including the pad 16e). The sag area RO1 refers to an area where the dielectric layer is removed during the planarization process of the conductive layer during the formation of the interconnect 13. The sag area RO1 extends from the top surface of the dielectric layer 14 of the dielectric structure 12 to the dielectric layer 24 below the dielectric layer 14. In some embodiments, the sag area RO1 has a ring shape when projected onto the surface of the substrate 10, which surrounds the inner region IR of the wafer, and the surface IS1 (or called the sag surface) of the sag area RO1 may be inclined , Curved or similar-shaped surfaces, but the disclosure is not limited to this. The surface IS1 is connected to the top surface of the dielectric layer 14 and then extends down to the sidewall of the wafer. In other words, the surface IS1 is lower than the top surface of the dielectric layer 14. In some embodiments, the sag region RO1 has a width W1 and a height H1, the width W1 ranges from 15 mm to 1 mm, for example, and the height H1 ranges from 20 μm to 0.5 μm, for example. The sag surface IS1 has end points E1 and E2. The end point E1 is the intersection of the flat top surface of the dielectric layer 14 and the collapsed surface IS1, and the end point E2 is the intersection of the collapsed surface IS1 and the sidewall of the wafer. In other words, the dielectric structure 12 begins to collapse from the end point E1 located on the top surface of the dielectric layer 14 and extends to the end point E2. In some embodiments, the height of the collapsed surface IS1 relative to the top surface of the base 10 gradually decreases from the end points E1 to E2. It should be noted that the aforementioned width W1 refers to the horizontal distance from the end E1 of the top surface of the dielectric layer 14 to the sidewall of the wafer in a direction parallel to the top surface of the substrate 10. The height H1 refers to the vertical distance from the end point E2 to the top surface of the dielectric layer 14 in the direction perpendicular to the top surface of the substrate 10 of the sag surface IS1.

1C, after the planarization process, the dielectric layer 14 includes an inner dielectric layer 14a located in the inner region IR of the wafer and an edge dielectric layer 14b located in the edge region ER. The inner dielectric layer 14a has a substantially flat top surface and is substantially flush with the top surface of the pad 16e. The edge dielectric layer 14b is adjacent to the sag region RO1, and the surface of the edge dielectric layer 14b (ie, a part of the sag surface IS1) is lower than the top surface of the inner dielectric layer 14a. The surface of the edge dielectric layer 14b may also be referred to as the sidewall of the dielectric layer 14. In some embodiments, the surface of the edge dielectric layer 14b is inclined, curved or similar. The cross-sectional shape of the edge dielectric layer 14b is, for example, a triangle, a fan shape or the like, but the disclosure is not limited to this.

In some embodiments, the structure shown in FIG. 1C, that is, the substrate 10 and the interconnection structure InC above it may be referred to as a semiconductor structure 500. The edge of the semiconductor structure 500 has a sag area RO1.

1C and FIG. 1D, an additional dielectric layer 17 is formed to fill the sag area RO1 of the semiconductor structure 500. Specifically, an additional dielectric layer 17 is formed on the sag area RO1 of the interconnect structure InC to fill the sag area RO1. The material of the additional dielectric layer 17 may be the same as or different from the material of the dielectric layer 14. In some embodiments, the material of the additional dielectric layer 17 may include oxide (such as silicon oxide), nitride (such as silicon nitride), oxynitride (such as silicon oxynitride), and carbide (such as silicon carbide). Or a combination or other suitable dielectric material. The additional dielectric layer 17 can be selectively deposited or grown by CVD, PVD, ALD, thermal oxidation and other processes, but the disclosure is not limited to this.

In some embodiments, the additional dielectric layer 17 is formed by PECVD. For example, the PECVD may include the following process: placing the wafer shown in FIG. 1C in a processing chamber, and covering the inner area IR of the front surface of the wafer with a plasma exclusion ring On the upper side and/or the back side of the wafer, the collapsed area RO1 is exposed, and then the process gas is introduced. The front side of the wafer is opposite to the back side. The front side of the wafer refers to the side having or close to the pad 16e; and the back side of the wafer refers to the side away from the pad 16e. Since the inner area IR of the front surface of the wafer and the back surface of the wafer are covered by the plasma elimination ring, the additional dielectric layer 17 can be selectively deposited on the surface IS1 of the sag area RO1. In some embodiments, after the selective deposition process is performed, a planarization process (for example, CMP) is performed on the additional dielectric layer 17 to planarize the top surface of the additional dielectric layer 17.

Please continue to refer to FIG. 1D, the additional dielectric layer 17 fills the sag area RO1 and covers the sag surface IS1. In some embodiments, the additional dielectric layer 17 has a ring shape when projected onto the surface of the substrate 10, surrounding the inner region IR of the wafer. The cross-sectional shape of the additional dielectric layer 17 may be triangular or similar. In some embodiments, the top surface of the additional dielectric layer 17 is substantially flush with the top surface of the dielectric layer 14 of the interconnect structure InC and the top surface of the pad 16e, and the sidewall of the additional dielectric layer 17 is substantially flush with the wafer The side walls are aligned, but the disclosure is not limited to this. In other words, there is an interface (IF) between the additional dielectric layer 17 and the dielectric structure of the interconnect structure InC. The interface IF extends from the top surface of the dielectric layer 14 to the dielectric layer 24 (FIG. 5) below the dielectric layer 14.

1E, a bonding dielectric layer 18 is formed on the substrate 10. The bonding dielectric layer 18 may be a single layer or a multilayer structure. The bonding dielectric layer 18 includes silicon oxide, silicon nitride, silicon oxynitride, polymer or a combination thereof or the like. The polymer is, for example, polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), combinations thereof, or the like. The forming method of the bonding dielectric layer 18 includes spin coating, CVD, PECVD or similar processes. The bonding dielectric layer 18 covers the top surface of the pad 16 e, the top surface of the dielectric layer 14 and the top surface of the additional dielectric layer 17. In the disclosed embodiment, since the sag area RO1 is filled by the additional dielectric layer 17, the bonding dielectric layer 18 may have a substantially flat top surface.

1F to 1G, a via 19 and a trench 20 are formed in the bonding dielectric layer 18. In some embodiments, the via 19 and the trench 20 are formed by a dual damascene process. The dual damascene process may include a trench first process, a via first process, and a self-aligned process. Figures 1F to 1G illustrate the formation of vias 19 and trenches 20 using a dual damascene process with vias as an example. However, it should be understood that the present disclosure is not limited to this, and vias 19 and trenches 20 can also be formed by It is formed by other types of dual damascene processes, single damascene processes or similar processes.

1F, in some embodiments, a via 19 is first formed in the bonding dielectric layer 18 to expose a part of the top surface of the pad 16e. The via 19 is formed by, for example, a photolithography process. For example, a first patterned mask layer is formed over the bonding dielectric layer 18. The first patterned mask layer has a first opening corresponding to the position where the via 19 is to be formed, and partially exposes the top surface of the dielectric layer 18. Then, an etching process is performed using the first patterned mask layer as a mask to remove the bonding dielectric layer 18 exposed by the first opening, and form a via 19 penetrating the bonding dielectric layer 18. After that, the first patterned mask layer is removed.

Next, referring to FIG. 1G, a trench 20 is formed on the upper portion of the bonding dielectric layer 18. The trench 20 is formed by, for example, the following process: forming a second patterned mask layer on the bonding dielectric layer 18. The second patterned mask layer has a second opening corresponding to the position where the trench 20 is to be formed. The size (for example, width) of the second opening is larger than the size (for example, width) of the first opening, exposing a part of the top surface of the bonding dielectric layer and the via 19. Then, an etching process is performed using the second patterned mask layer as a mask to remove a portion of the bonding dielectric layer 18 exposed by the second opening, so as to form a trench 20 in the upper portion of the bonding dielectric layer 18. In some embodiments, the bonding dielectric layer 18 includes a multilayer structure and has an etch stop layer therein. The etching stop layer is used to define the position where the etching process of the trench 20 stops. The trench 20 is located above the via 19 and spatially communicates with the via 19. Part of the pad 16e is exposed by the via 19 and the trench 20.

1H, a conductive layer 22 is formed on the substrate 10. The conductive layer 22 covers the top surface of the bonding dielectric layer 18 and fills the via 19 and the trench 20. The material and forming method of the conductive layer 22 are similar to the material and the forming method of the conductive layer 16, and can be the same or different, and will not be repeated here.

1H, in some embodiments, similar to the conductive layer 16 (FIG. 1A), the conductive layer 22 has an uneven surface. For example, the conductive layer 22 has a body portion BP located in the inner region IR and an edge portion EP located in the edge region ER. The edge EP protrudes from the main body BP. In other words, the edge EP has a first part P1 and a second part P2 located on the first part P1. The first part P1 refers to a part that is substantially flush with the main body BP and does not protrude from the main body BP. The second portion P2 protrudes from the top surface of the main body portion BP, and may be referred to as a protrusion P2. The structural features of the conductive layer 22 are similar to the structural features of the conductive layer 16 (FIG. 1A ), and will not be repeated here. A partial enlarged view of the conductive layer 22 is also shown in FIG. 4A. In some embodiments, the edge EP of the conductive layer 22 also has a recess RC due to the placement of the negative electrode 75.

1H to FIG. 1I, then the conductive layer 22 is planarized to remove the conductive layer 22 located above the bonding dielectric layer 18, and leave the conductive layer 22a located in the via 19 and the trench 20. Specifically, the planarization process removes a portion of the body portion BP and the edge portion EP above the dielectric layer. In other words, the first portion P1 and the protrusion P2 of the edge portion EP are removed by the planarization process. In some embodiments, the conductive layer 22 located above the top surface of the bonding dielectric layer 18 is completely removed by the planarization process. In some embodiments, the planarization process includes a CMP process, but the disclosure is not limited to this.

In some embodiments, the formation of the conductive layer 22a omits the EBR process, that is, after the conductive layer 22 is formed and before the planarization process, the EBR process is not performed to remove the edge EP of the conductive layer 22, but the planarization is directly performed. The chemical process removes the conductive layer 22 (including part of the body portion BP and the edge portion EP) above the bonding dielectric layer 18. In the disclosed embodiment, the sag area RO1 caused by the EBR process has been filled by the additional dielectric layer 17 during the formation of the interconnect structure, so that the bonding dielectric layer 18 has a substantially flat top. Therefore, the EBR process can be omitted for the conductive layer 22, and the process parameters of the planarization process can be adjusted, so that the conductive layer 22 above the bonding dielectric layer 18 is removed cleanly without being in the edge area ER of the wafer There are residual conductive layers. In addition, since the EBR process is omitted, the edge EP of the conductive layer 22 will not produce large recesses caused by the EBR process (similar to the recesses RC' of the conductive layer 16 shown in FIG. 4C and FIG. 1B), thereby avoiding bonding media. The electrical layer 18 collapsed.

Please continue to refer to FIGS. 1H to 1I. In some embodiments, as shown in FIG. 4A, since the edge EP of the conductive layer 22 also has a small recess RC caused by the negative electrode 75, the conductive layer 22 is flattened The manufacturing process may slightly damage the bonding dielectric layer 18, thereby generating the sag area RO2 and the sag surface IS2. The sag area RO2 refers to the area of the bonding dielectric layer 18 that is removed during the planarization process of the conductive layer 22. The sag surface IS2 is lower than the top surface of the bonding dielectric layer 18, and extends from the top surface of the bonding dielectric layer 18 to the sidewall of the bonding dielectric layer 18. The level of the sag surface IS2 relative to the top surface of the substrate 10 increases with It is gradually lowered away from the top surface of the bonding dielectric layer 18. In some embodiments, compared to the larger recesses caused by the EBR process (such as the recess RC' of the conductive layer 16 shown in FIG. 4C and FIG. 1B), the recess RC generated by the placement of the negative electrode 75 is extremely small, so that the The range of the sag area RO2 generated in the dielectric layer 18 is extremely small, or even negligible. In some embodiments, the width W2 and height H2 of the sag region RO2 are much smaller than the width W1 and height H1 of the sag region RO1. For example, the width W2 of the sag region RO2 ranges from 0.3 mm to 0.8 mm, and the height H2 ranges from -0.5 μm to 0.5 μm. Here, the case where the height H2 is a negative value means that, in some embodiments, after the planarization process removes the conductive layer 22 above the bonding dielectric layer 18, it may continue to remove part of the bonding dielectric layer 18 downward. And a part of the conductive layer 20 located in the trench 20 may further cause the edge portion of the bonding dielectric layer 18 to have bumps that protrude from the top surface of the bonding dielectric layer 18 in the inner region IR. The bump may be caused by the removal rate of the edge of the wafer being lower than the removal rate of the inner region. In some embodiments, the height H2 in the above range does not affect the subsequent bonding process.

Please refer to FIG. 1I. In some embodiments, the conductive layer 22a is also called a bonding pad 22a. The bonding pad 22a is embedded in the bonding dielectric layer 18 and passes through the bonding dielectric layer 18 to be electrically connected to the bonding pad 16e. In some embodiments, the bonding pad 22a includes a first portion 22b and a second portion 22c on the first portion 22b. The first part 22b is located in the via 19 (FIG. 1G), and is physically and electrically connected to the pad 16e. In some embodiments, the first portion 22b may be referred to as a through hole. The second portion 22c is located in the trench 20 and is electrically connected to the pad 16e through the through hole 22b. The bonding pad 22a and the bonding dielectric layer 18 constitute a bonding structure 28 for the subsequent bonding process.

Please refer to FIG. 1I and FIG. 5A, the wafer 50a is now completed. In some embodiments, the wafer 50a includes a substrate 10, an interconnect structure InC, an additional dielectric layer 17 and a bonding structure 28. The dielectric layer 14 and the pads 16e embedded in the dielectric layer 14 are located on the top of the interconnect structure InC. In some embodiments, the dielectric structure 12 of the interconnect structure InC has a sag area RO1 in the edge area ER of the wafer 50a. The sag area RO1 extends from the top surface of the top dielectric layer 14 toward the substrate 10. In some embodiments, the slumped area RO1 extends from the top surface of the top dielectric layer 14 to the bottom dielectric layer (ie, the inner dielectric layer) or the first layer of intermetal dielectric of the dielectric structure 12 However, this disclosure is not limited to this. In some embodiments, the sag area RO1 does not extend to the substrate 10. In other words, the slumped area RO1 is located above a part of the bottommost dielectric layer of the dielectric structure 12, and is located at the side of the part of the dielectric structure 12, and surrounds the interconnect structure InC.

The additional dielectric layer 17 fills the sag area RO1 of the dielectric structure 12. In other words, the additional dielectric layer 17 is located above a portion of the dielectric layer of the dielectric structure 12 and on the side of the portion of the dielectric layer of the dielectric structure 12, and surrounds the interconnect structure InC. In some embodiments, the top surface of the additional dielectric layer 17 is substantially flush with the top surface of the pad 16e of the interconnect structure InC and the top surface of the dielectric layer 14. From another perspective, the additional dielectric layer 17 is located on the side of the interconnect structure InC, and between the bonding structure 28 and the interconnect structure InC, or between the bonding structure 28 and the substrate 10. In some embodiments, the additional dielectric layer 17 is not in contact with the substrate 10 but is separated by a portion of the dielectric structure 12 between the additional dielectric layer 17 and the substrate 10.

The bonding structure 28 is located on the interconnect structure InC and the additional dielectric layer 17, and includes the bonding pad 22 a and the bonding dielectric layer 18. In some embodiments, the dielectric layer 18 of the bonding structure 28 also has a small sag area RO2. The size of the sag area RO2 is much smaller than the size of the sag area RO1 of the dielectric structure 12 in the interconnect structure InC.

In some embodiments, the wafer 50a includes a plurality of dies, such as application-specific integrated circuit (ASIC) chips, analog chips, and sensor chips. , Wireless and radio frequency chips, voltage regulator chip or memory chip. In some embodiments, a plurality of dies are arranged in an array in the wafer 50a, and may be the same type of dies or different types of dies.

1J, in some embodiments, a bonding process is then performed to bond the wafer 50a to another wafer 50a' to form a wafer stack structure (or called a wafer bonding structure) 100a. The wafer 50a' may be the same type or a different type of wafer as the wafer 50a. In some embodiments, the wafer 50a' includes a substrate 10', an interconnect structure InC', an additional dielectric layer 17', and a bonding structure 28'. The dielectric layer 14' and the pad 16e' are the top dielectric layer and top conductive feature of the interconnect structure InC'. The bonding structure 28' includes a bonding dielectric layer 18' and a bonding pad 22a' embedded in the bonding dielectric layer 18'. The bonding pad 22a' is electrically connected to the bonding pad 16e'. The structural features and forming method of the wafer 50a' are similar to the structural features and forming method of the wafer 50a, and will not be repeated here. In some embodiments, the wafer 50a and the wafer 50a' are bonded face to face, that is, face to face.

In some embodiments, the bonding structure 28' of the wafer 50a' is aligned with the bonding structure 28 of the wafer 50, wherein the bonding pad 22a' is aligned with the bonding pad 22a, and the dielectric layer 18' is aligned with the dielectric layer 18 Then, the bonding process is performed to bond the bonding structure 28 ′ and the bonding structure 28. The bonding process includes hybrid bonding, fusion bonding, or a combination thereof. In some embodiments where the bonding process includes hybrid bonding, the hybrid bonding includes at least two types of bonding, for example, including metal-to-metal bonding and non-metal and non-metal bonding (for example, dielectric Quality and dielectric bonding (dielectric-to-dielectric bonding). That is, the bonding pad 22a and the bonding pad 22a' are bonded by metal-to-metal bonding, and the bonding dielectric layer 18 and the bonding dielectric layer 18' are bonded by dielectric-to-dielectric bonding.

In some embodiments where the bonding process includes fusion bonding, the bonding operation of fusion bonding may be performed as follows. First, in order to avoid the generation of unbonded areas (for example, interface bubbles), the surface to be bonded of the wafer 50a and the surface to be bonded of the wafer 50a' (ie, the surfaces of the bonding structure 28 and the bonding structure 28') are processed , Make it clean and smooth enough. Then, the wafer 50a' and the wafer 50 are aligned and placed in physical contact with the wafer 50 at room temperature with slight pressure to start the bonding operation. Thereafter, an annealing process is performed at an elevated temperature to strengthen the chemical bond between the surface to be bonded of the wafer 50a' and the surface of the wafer 50 to be bonded, and to convert the chemical bond into a covalent bond.

Please continue to refer to FIG. 1J. FIG. 1J includes enlarged views A and B of the area BR of the bonded wafer. The area BR is the edge bonding area of the wafers 50a and 50a'. In some embodiments, the wafer 50a and the wafer 50a' have the same size. For example, the width W3 of the wafer 50a and the width W4 of the wafer 50a' are the same. As shown in the enlarged view A, in some embodiments, after the bonding process, the sidewall SW1 of the wafer 50a and the sidewall SW2 of the wafer 50a' are aligned with each other in a direction perpendicular to the substrate 10. In some embodiments, as shown in the enlarged view A, after the wafer 50a' and the wafer 50a are bonded, since the wafer 50a and the wafer 50a' respectively have sag regions RO2 and RO2', the wafer 50a and There may be non-bond regions (or referred to as non-bond regions) NR caused by the sag regions RO2 and RO2' between the edges of the wafer 50a'. However, the present disclosure is not limited to this. In other embodiments, the wafer 50a and the wafer 50a' do not include the sag area, so no unbonded area is generated. In still other embodiments, the sag areas of the wafer 50a and the wafer 50a' are extremely small, so during the bonding process, the bonding dielectric layer 18 and the bonding dielectric layer 18' can be well melted with each other without causing any undesirable Bonding area.

In some embodiments, after the wafer 50a and the wafer 50a' are bonded, the wafer 50a' bonded above the wafer 50a is further subjected to a polishing process to reduce the thickness of the wafer 50a'. Next, in some embodiments where there is an unbonded area NR between the wafer 50a and the wafer 50a', as shown in the enlarged view B, the wafer 50a' may be subjected to a trimming process to remove A portion of the wafer 50a' above the unbonded area NR (the removed portion is shown in dashed lines), so as to prevent the wafer 50a' from cracking when more layers of wafers are stacked later. The trimming process reduces the size (for example, width) of the wafer 50a', that is, makes the size of the wafer 50a' smaller than the size of the wafer 50a. In some embodiments, the width of the removed part of the wafer 50a' is Wt, and the width Wt depends on the width of the sag area RO2' of the wafer 50a'. The smaller the width of the sag area RO2', the smaller the width Wt of the wafer 50a' to be trimmed and removed. In the embodiment of the present disclosure, taking a circular wafer 50a/50a' with a radius of 150mm as an example, the width Wt of the wafer 50a' to be removed by the trimming process ranges from 0.8 mm to 1.5 mm, and the radius The wafer within the range of 147 mm is a good die area, so the trimming process will not affect the good die area of the wafer 50a'.

In some embodiments, the trimmed wafer 50a' has a width W4' (W4'=W4-Wt). The width W4' is slightly smaller than the initial width W4 of the wafer 50a' or the width W3 of the wafer 50a. For example, in some embodiments, the ratio (W4':W3) of the width W4' of the trimmed wafer 50a' to the width W3 of the wafer 50a ranges from about 99% to about 99.5%. In some embodiments where the top-view shape of the wafer is circular, the width of the wafer here refers to the diameter of the wafer. As shown in the enlarged view B, after the trimming process, the sidewall SW2' of the wafer 50a' and the sidewall SW1 of the wafer 50a are staggered with each other in a direction perpendicular to the top surface of the substrate 10. The side wall SW1 of the wafer 50a laterally protrudes from the side wall SW2' of the wafer 50a'. The sidewall SW2' of the wafer 50a' is closer to the inner region of the wafer than the sidewall SW1 of the wafer 50a in the horizontal direction.

In the disclosed embodiment, since the formation of the bonding pads omits the EBR process, the size of the collapsed area of the bonding dielectric layer of the wafer is greatly reduced, thereby greatly reducing the collapsed area caused by the wafer stacking. The unjoined area. Therefore, the trimming process only needs to trim the wafer above the unbonded area in a small amount without reducing its size too much. In other words, during wafer stacking, each layer of wafers is only trimmed in a small amount, so that a large enough good die area can be maintained, so more layers of wafers can be stacked.

FIG. 1J exemplarily shows a wafer stack structure 100a formed by wafer-to-wafer bonding (wafer-to-wafer bonding) of a wafer 50a. In some embodiments, each of wafer 50a and wafer 50a' includes a plurality of dies. The plurality of dies are aligned with each other and joined together during the joining process to form a three-dimensional integrated chip (3DIC) structure. In some embodiments, after the wafer is bonded, a dicing process can be performed along the dicing lane of the wafer to cut a plurality of 3DIC structures. In some embodiments, after the dicing process, the 3DIC structure near the edge of the wafer may include an additional dielectric layer 17, but the disclosure is not limited to this. In other embodiments, after the wafer bonding, the dicing process may not be performed. The wafer bonding structure 100a including multiple 3DIC structures can also be directly applied to some specific fields, such as artificial intelligence (AI), However, this disclosure is not limited to this.

In other embodiments, a wafer-to-die bonding process may also be performed to bond a plurality of dies to the wafer 50a. In addition, the bonding process can be performed in a face-to-face manner or a back-to-face manner. FIG. 1J shows a two-layer wafer stack, but it should be understood that this is only an example, and the disclosure is not limited thereto.

FIG. 5B exemplarily shows a multilayer wafer stack structure 100b. In some embodiments, the wafer stack structure 100b includes wafer 50a, wafer 200, wafer 201, wafer 202, and wafer 203 that are sequentially stacked from bottom to top. In some embodiments, a more detailed schematic cross-sectional view of the wafer 50a is shown in FIG. 5A. The wafers 200, 201, 202, and 203 each include a substrate 400, integrated circuit components, interconnection structures, additional dielectric layers, and bonding structures 401 and 402. The integrated circuit components, interconnection structures and additional dielectric layers of the wafers 200 to 203 are similar to those of the wafer 50a, and will not be repeated here. For the sake of brevity, the additional dielectric layer is not specifically shown in FIG. 5B.

In some embodiments, the bonding structure of the wafer may be disposed on the front surface, the back surface of the wafer, or a combination thereof. For example, the wafer 50a has a bonding structure 28 on its front surface. The wafers 200, 201, and 202 each have a bonding structure 401 on the back side and a bonding structure 402 on the front side. The wafer 203 has a bonding structure 402 on its front side. The bonding structures 401 and 402 are similar to the bonding structure 28 and include a dielectric layer and bonding pads that are electrically connected to conductive features in the interconnect structure of the corresponding wafer. In some embodiments, the bonding structure 401 on the back side of the wafers 200, 201, and 202 is electrically connected to the conductive features of the interconnect structure of the corresponding wafer through a through substrate via (TSV). The substrate through hole TSV includes conductive materials, such as copper, aluminum, tungsten, alloys thereof, or combinations thereof. In some embodiments, the base through hole TSV further includes a barrier layer. The barrier layer is located between the conductive material and the substrate 400 to prevent the conductive material from diffusing into the substrate 400. The material of the barrier layer is, for example, titanium, tantalum, titanium nitride, tantalum nitride or a combination thereof.

The wafer and wafer can be bonded face to face (front to front), face to back (front to back) or back to back. For example, the wafer 50a and the wafer 200 are bonded together in a face-to-back manner through the bonding structure 28 and the bonding structure 401. The wafer 200 and the wafer 201 are bonded together by the bonding structure 402 and the bonding structure 401 in a face-to-back manner. The wafer 201 and the wafer 202 are bonded together by the bonding structure 402 and the bonding structure 401 in a face-to-back manner. The wafer 202 and the wafer 203 are bonded together in a face-to-face manner through the bonding structure 402 and the bonding structure 402.

In some embodiments, a dielectric cap layer 405 is formed on the topmost wafer 203. The material of the dielectric covering layer 405 includes silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, combinations thereof, or the like. The connector 406 passes through the dielectric cover layer 405 and is electrically connected to the base through hole TSV of the wafer 203 to serve as an external connection from the wafer 50 a to the wafer 203. The connector 406 includes conductive materials such as metal or metal alloy, such as copper, aluminum, tungsten, nickel, alloys thereof, or combinations thereof.

Please continue to refer to FIG. 5B. In some embodiments, a passivation layer is formed on the dielectric covering layer 405 and the connecting member 406. The passivation layer can be a single layer or a multilayer structure. In some embodiments, the passivation layer has a multilayer structure and includes a first passivation layer 407 and a second passivation layer 408. The materials of the first passivation layer 407 and the second passivation layer 408 may be the same or different. In some embodiments, the first passivation layer 407 and the second passivation layer 408 may respectively include silicon oxide, silicon nitride, silicon oxynitride, polymer, combinations thereof, or the like. The polymer is, for example, PBO, PI, BCB, a combination thereof, or the like.

The conductive pad 409 is formed on the first passivation layer 407 and penetrates the first passivation layer 407 to be electrically connected to the connection member 406. The material of the conductive pad 409 may be the same as or different from the material of the connecting member 406. The second passivation layer 408 covers the sidewalls and part of the top surface of the conductive pad 409. The second passivation layer 408 has an opening, exposing a part of the top surface of the conductive pad 409. The connection terminal (or conductive ball or conductive bump) 410 is disposed on the conductive pad 409 exposed by the second passivation layer 408. The material of the connection terminal 410 includes copper, aluminum, a lead-free alloy (for example, gold, tin, silver, or copper alloy), or a lead alloy (for example, a lead-tin alloy). In some embodiments, the connection terminal 410 is, for example, a controlled collapse chip connection (C4) bump or a solder ball. In some embodiments, the connection terminal 410 is placed on the conductive pad 409 by a ball mounting process. In some embodiments, before forming the connection terminal 410, it further includes forming an under-ball metallurgy (UBM) layer 411 on the conductive pad 409 exposed by the second passivation layer 408. The material of the under-bump metal layer 411 includes metal or metal alloy. The under-bump metal layer 411 is, for example, copper, tin, alloys thereof, or a combination thereof. The formation method of the under-bump metal layer 411 is, for example, a physical vapor deposition method or an electroplating method. The connection terminal 410 may be electrically connected to the conductive pad 409 through the under-bump metal layer 411. In some embodiments, after the connection terminals 410 are formed, a dicing process may be performed to cut the wafer stack structure 100b into a plurality of independent 3DIC structures. However, this disclosure is not limited to this. In other embodiments, after the wafer bonding, the dicing process may not be performed. The wafer bonding structure 100b including multiple 3DIC structures can also be directly applied to some specific fields, such as artificial intelligence (AI), However, this disclosure is not limited to this.

In some embodiments, in the process of stacking (bonding) each layer of wafers, after the wafers are bonded, a trimming process needs to be performed on the wafers above the unbonded areas that may occur. For example, in some embodiments, the formation of the wafer stack structure 100b shown in FIG. 5B may include the following processes to provide wafers 50a, 200, 201, 202, and 203. Before the bonding process, these wafers have, for example, the same size, but the disclosure is not limited to this. First, the wafer 200 is bonded to the wafer 50a, and then the first trimming process is performed to remove a part of the wafer 200 above the unbonded area of the wafer 50a and the wafer 200. The size of the wafer 200 after the first trimming process Slightly smaller than the size of wafer 50a. The wafer 201 is bonded to the wafer 200. A second trimming process is performed to remove a portion of the wafer 201 above the unbonded area of the wafer 201 and the wafer 200. The size of the wafer 201 after the second trimming process is slightly smaller than the size of the wafer 200. Repeat the bonding and trimming process to continue stacking wafer 202 and wafer 203 upward. Therefore, in the formed wafer stack structure 100b, the size of the wafer 50a to the wafer 203 gradually decreases from bottom to top.

In the disclosed embodiment, since the formation of the bonding pads omits the EBR process, the size of the collapsed area of the bonding dielectric layer of the wafer is greatly reduced, thereby greatly reducing the collapsed area caused by the wafer stacking. The unjoined area. Therefore, the trimming process only needs to trim the wafer above the unbonded area in a small amount without reducing its size too much. In other words, each layer of wafers is only trimmed in a small amount, so that each layer of wafers can retain a large enough good grain area, so that more layers of wafers can be stacked.

The number of wafer layers shown in FIG. 5B is only for illustration, and the disclosure is not limited thereto. In the disclosed embodiment, since the unbonded area between the wafer and the wafer is greatly reduced, more layers of wafers can be stacked.

2A to 2C are schematic cross-sectional views of a method for manufacturing a wafer stack structure according to a second embodiment of the present disclosure. The difference between the second embodiment and the first embodiment is that the formation of the bonding pad 22a includes the EBR process after the planarization process.

FIG. 2A corresponds to the structure of FIG. 1H in the first embodiment. Please refer to FIG. 2A to FIG. 2B. The conductive layer 22 is formed, and the edge EP of the formed conductive layer 22 protrudes from the main body BP. The edge EP includes a first portion P1 and a protrusion P2. Afterwards, a planarization process (such as CMP) is performed to remove a portion of the conductive layer 22 located above the bonding dielectric layer 18. In some embodiments, the planarization process may remove the main portion BP and most of the edge portion EP of the conductive layer 22, and the edge EP of the conductive layer 22 may not be completely removed by the planarization process, but at the edge of the wafer The lower edge EP2 remains in the area ER. Specifically, the protrusion P2 of the edge portion EP and most of the first portion P1 are removed by the planarization process, and some of the first portions P1 at the bottom are not removed by the planarization process to form the edge portion EP2.

2B to 2C, after the planarization process, an EBR process is then performed to remove the remaining edge EP2. That is, the EBR process removes the residue of the conductive layer 22 above the bonding dielectric layer 18 after the planarization process. Since the etchant used in the EBR process has high etching selectivity between the conductive layer and the dielectric layer, the EBR process only removes the remaining edge EP2 of the conductive layer without damaging the bonding dielectric layer 18. In this embodiment, performing the EBR process after the planarization process can not only ensure that no conductive layer remains on the bonding dielectric layer 18, but also avoid damage to the bonding dielectric layer 18 and sag.

2C, the wafer 50b is now completed, and the structure of the wafer 50b is similar to that of the wafer 50a. In some embodiments, since the EBR process is performed after the planarization process, during the planarization process, since the edge portion EP2 of the conductive layer above the bonding dielectric layer 18 in the edge region is still protected, the planarization process may not damage the bonding Dielectric layer 18. The subsequent EBR process will not cause damage to the bonding dielectric layer 18, so the bonding dielectric layer 18 of the wafer 50b may not have the collapse of the wafer 50a (FIG. 1I), thereby avoiding subsequent wafer bonding. Unjoined area appears when However, this disclosure is not limited to this. In other embodiments, since the edge EP of the conductive layer itself has a recess RC (FIG. 4A ), the planarization process may also damage the bonding dielectric layer 18 under the recess RC, and a collapsed area similar to the wafer 50a may appear. RO1 (Figure 1I). After that, the wafer 50b may enter a subsequent bonding process such as shown in FIG. 1J.

In the above embodiments, the planarization process and the EBR process may be performed in separate CMP machines and EBR machines, for example. Taking the second embodiment as an example, after the conductive layer 22 is formed as shown in FIG. 2A, the wafer is loaded into the CMP machine for a CMP process to form the structure shown in FIG. 2B, and then the wafer is carried out of the CMP machine , And load the resulting wafer (Figure 2B) into the EBR machine for the EBR process. However, this disclosure is not limited to this.

In other embodiments, the planarization process and the EBR process can be performed in the same CMP machine. The CMP machine includes an EBR chamber or an EBR nozzle, so that the CMP process and the EBR process can be performed in the same CMP machine.

3A to 3B are schematic cross-sectional views of a method for manufacturing a wafer stack structure according to a third embodiment of the present disclosure. FIG. 6 shows a schematic diagram of a CMP machine according to some embodiments of the disclosure. The third embodiment exemplarily shows that the CMP process and the EBR process are performed in the same CMP machine.

Referring to FIG. 6, in some embodiments, the CMP machine 300 includes a CMP chamber 306, a transfer station 307, a robot arm 308, a cleaning module 313, a robot arm 314, a metrology device 315, and a load port ) 316. The CMP chamber 306 includes one or more polishing tables 301, a polishing pad adjuster 302, a polishing liquid supply device 303, a polishing head 304 and a load cup 305. FIG. 6 exemplarily shows three polishing stations 301, but the number of polishing stations is not limited thereto. Multiple polishing tables 301 can process multiple wafers at the same time, and each polishing table 301 has a corresponding polishing pad regulator 302, a polishing liquid supply device 303, and a polishing head 304. The polishing pad adjuster 302 can adjust the polishing pad on the corresponding polishing table 301. The polishing liquid supply device 303 supplies the polishing liquid to the polished wafer surface during the CMP process. The loading cup 305 is used to load the wafer to the polishing table 301 or to load the wafer from the polishing table 301. The wafers in the CMP chamber 306 can be transferred to the transfer station 307.

The wafers in the transfer station 307 can be transferred to the cleaning module 313 through the robot arm 308. The cleaning module 313 can be used to perform EBR process, cleaning and drying processes on the polished wafer. The cleaning process may include an ultrasonic cleaning process and a brush cleaning process. In some embodiments, the cleaning module 313 includes an EBR chamber 309, an ultrasonic device 310, a brush cleaner 311, and a dryer 312. The brush cleaner 311 includes, for example, a roller-type brush, a pen-type brush, or the like or a combination thereof.

The robotic arm 314 can be used to transfer the wafer from the cleaning module 313 to the measuring device 315 or the load port 316. The measuring device 315 can test the wafer. The load port 316 is used to store wafers.

Referring to FIGS. 3A to 3B and FIG. 6, in some embodiments, after the conductive layer 22 is formed on the substrate 10, the wafer 50 shown in FIG. 3A is loaded into the CMP machine 300. In some embodiments, the wafer 50 is loaded into the CMP chamber 306 to perform a CMP process on the conductive layer 22. For example, the wafer 50 is loaded into the loading cup 305 of the CMP chamber 306, and then the wafer 50 loaded into the cup 305 is loaded onto the polishing pad of the polishing table 301, and the wafer 50 to be polished is electrically conductive. The layer 22 faces the polishing head 304, that is, the wafer 50 is placed between the polishing pad of the polishing table 301 and the polishing head 304. During the polishing process, the polishing liquid supply device 303 supplies the polishing liquid to the surface of the conductive layer 22 of the wafer 50 to be polished. The polishing head 304 contacts the surface of the conductive layer 22 and rotates the polishing head 304 to polish the conductive layer 22. In some embodiments, the polishing table 301 rotates in the opposite direction to the polishing head 304 during the polishing process.

After the CMP process of the wafer 50 is completed in the CMP chamber 306, the wafer 50 is carried out from the CMP chamber 306 to the transfer station 307 through the loading cup 305. Then, the wafer 50 is transferred to the cleaning module 313 by the robot arm 308. In some embodiments, the wafer 50 is transferred to the EBR chamber 309 in the cleaning module 313 to perform an EBR process on the wafer 50. The EBR chamber 309 includes, for example, one or more EBR spray heads or nozzles, and the EBR etchant can be sprayed to the edge of the wafer 50 to remove the conductive layer 22 that may remain on the bonding dielectric layer 18 on the edge of the wafer 50 .

Then, the ultrasonic device 310 and the brush cleaner 311 are used to perform ultrasonic cleaning and brush cleaning on the wafer 50. The cleaning process may also include other types of physical and/or chemical cleaning steps. After the cleaning process, the wafer 50 is dried by the dryer 312. After that, the wafer 50 can be transferred to the measuring device 315 by the robotic arm 314 to inspect the wafer 50. For example, the measuring device 315 can detect the flatness of the wafer surface after the CMP process and the EBR process and whether there is any remaining conductive layer above the bonding dielectric layer 18. If the wafer is inspected well, the robot arm 314 can transfer the inspected wafer to the load port 316. If the inspection fails, the robotic arm 314 can be used to transfer the wafer to the CMP chamber 306 or the cleaning module 313 again until the inspection passes, and the wafer that passes the inspection is transferred to the load port 316. So far, the wafer 50c shown in FIG. 3B is completed and stored in the load port 316. After that, the wafer 50c can be unloaded from the load port 316 for subsequent processing. In the third embodiment, the structural features of the wafer 50c and the wafer 50a or 50b are similar, and will not be repeated here. The difference is that the wafer 50c undergoes the CMP process and the EBR process in the same CMP machine.

FIG. 6 is only an example of the CMP machine integrating the CMP equipment and the EBR equipment, and the disclosure is not limited to this. In some embodiments, the EBR chamber may be included in the CMP chamber. For example, an EBR nozzle can be arranged near the polishing liquid supplier, and the EBR nozzle can supply EBR etchant to the wafer to be processed on the polishing table, so as to perform the EBR process on the wafer. However, this disclosure is not limited to this.

7 to 8 show a flowchart of a method of manufacturing a wafer bonding structure according to some embodiments of the disclosure. Please refer to FIG. 7. In some embodiments, the formation of the wafer bonding structure includes the following processes. In step 1200, an interconnection structure is formed on the substrate. Step 1200 includes step 1100 to step 1104. In step 1100, a dielectric layer is formed on the substrate. In step 1101, the dielectric layer is patterned to form openings in the dielectric layer. In step 1102, a conductive layer is formed on the dielectric layer to cover the top surface of the dielectric layer and fill the openings of the dielectric layer. In step 1103, an edge ball removal (EBR) process is performed on the conductive layer to remove the edge of the conductive layer. Then in step 1104, after the EBR process, the conductive layer is subjected to a chemical mechanical polishing (CMP) process to remove the conductive layer located above the top surface of the dielectric layer, and the conductive layer remaining in the opening of the dielectric layer forms a contact pad.

After step 1200, step 1201 is performed to form an additional dielectric layer to fill the sag area at the edge of the interconnect structure. Then in step 1202, a bonding dielectric layer is formed on the interconnect structure and the additional dielectric layer. In step 1203, the bonding dielectric layer is patterned to form openings in the bonding dielectric layer. In step 1204, a bonding pad material layer is formed on the bonding dielectric layer to cover the top surface of the bonding dielectric layer and filling the openings of the bonding dielectric layer. Afterwards, in some embodiments, step 1205 is performed to perform a CMP process on the bonding pad material layer. The CMP process removes the bonding pad material layer above the top surface of the bonding dielectric layer, leaving the bonding dielectric layer in the opening The bonding pad material layer forms the bonding pad. In some embodiments, the bonding pad material layer above the top surface of the bonding dielectric layer is completely removed by the CMP process.

In other embodiments, after step 1204, step 2205 is performed to perform a CMP process on the bonding pad material layer. The CMP process removes part of the bonding pad material layer above the top surface of the bonding dielectric layer, and performs a CMP process on the bonding medium layer. A part of the edge of the bonding pad material layer remains above the edge of the electrical layer. Then, in step 2206, an EBR process is performed to remove the remaining edge portion of the bonding pad material layer, and the bonding pad material layer remaining in the opening of the bonding dielectric layer forms a bonding pad. In some embodiments, the CMP process and the EBR process in steps 2205 and 2206 are performed in separate CMP machines and EBR machines. In other embodiments, the CMP process and the EBR process in steps 2205 and 2206 are performed in the same CMP machine.

In the embodiment of the present disclosure, the EBR process is omitted for the formation of the bonding pad, or the EBR process is performed after the planarization process. Therefore, the bonding dielectric layer of the wafer can be prevented from being damaged during the bonding pad formation process, thereby causing the crystal The round bonding dielectric layer does not have a sag area, or the size of the sag area can be greatly reduced, which can greatly reduce the unbonded area between the wafers caused by the sag area when the wafer is stacked . In turn, the size of the wafer that needs to be trimmed for the wafer above the unbonded area is greatly reduced, which can prevent the trimming from affecting the good grain area of the wafer, and thus allows more layers of wafers to be stacked.

According to some embodiments of the present disclosure, a method for forming a wafer bonding structure includes forming a first wafer and bonding a second wafer to a bonding dielectric layer and bonding pads of the first wafer. Forming the first wafer includes the following processes. A semiconductor structure is provided, and the edge of the semiconductor structure has a first sag area. An additional dielectric layer is formed to fill the first sag area. A bonding dielectric layer with openings is formed on the semiconductor structure and the additional dielectric layer. A conductive layer is formed on the bonding dielectric layer and filled into the opening, wherein the conductive layer above the additional dielectric layer has protrusions. A removal process is performed to remove the conductive layer located on the bonding dielectric layer, and the conductive layer remaining in the opening forms a bonding pad. The removal process includes a planarization process, and the bumps are removed by the planarization process.

According to other embodiments of the present disclosure, a method for forming a wafer bonding structure includes forming a first wafer and bonding a second wafer to the bonding structure of the first wafer. Forming the first wafer includes: providing a semiconductor structure; forming an additional dielectric layer on the side of the semiconductor structure; and forming a bonding structure on the semiconductor structure and the additional dielectric layer. The formation of the bonding structure includes the following processes. A bonding dielectric layer with openings is formed. A conductive layer is formed on the bonding dielectric layer and filled into the opening. A planarization process is performed to remove part of the conductive layer located above the bonding dielectric layer. An edge ball removal process is performed to remove residues of the conductive layer above the bonding dielectric layer after the planarization process, wherein the conductive layer remaining in the opening forms a bonding pad.

According to some embodiments of the present disclosure, a wafer bonding structure includes a first wafer and a second wafer. The first wafer includes an interconnect structure, a bonding structure, and an additional dielectric layer on the substrate. The bonding structure is located above the interconnection structure and is electrically connected to the interconnection structure. The additional dielectric layer is located on the side of the interconnect structure and between the bonding structure and the interconnect structure. The second wafer is bonded to the bonding structure of the first wafer.

The features of several embodiments have been summarized above, so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should know that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purpose as the embodiment described herein and/or achieve the same purpose as the embodiment described herein. The same advantages as the embodiment. Those skilled in the art should also realize that these equivalent configurations do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and substitutions without departing from the spirit and scope of the present disclosure. change.

10, 10’, 400: base 11: Integrated circuit components 12: Dielectric structure 13: internal connection 14, 14’, 24: Dielectric layer 14a: Internal dielectric layer 14b: Edge dielectric layer 15: opening 16, 22: Conductive layer 16a, BP: main body 16b, 16b': convex part 16c, 16c’: recess 16d, 16d’, EP, EP2: edge 16e, 16e’: pad 17, 17’: Additional dielectric layer 18, 18': Bonding dielectric layer 19: Mesopore 20: Ditch 22a, 22a’: Bonding pad 22b, P1: Part One 22c, P2: Part Two 28, 28’, 401, 402: Joint structure 50, 50a, 50a’, 50b, 50c, 200, 201, 202, 203: Wafer 70, 70a, 70b, 70c: barrier layer 71, 71a, 71b, 71b', 71c: seed layer 72, 72a, 72b, 72b': metal layer 75: Negative electrode 100a, 100b: Wafer stack structure 300: CMP machine 301: Grinding table 302: Polishing pad adjuster 303: Grinding liquid supply device 304: Grinding head 305: Loading cup 306: CMP chamber 307: Transfer Station 308: Robotic arm 309: EBR chamber 310: Ultrasonic device 311: Brush cleaner 312: Dryer 313: Cleaning module 314: Robotic arm 315: Measuring equipment 316: Load port 405: Dielectric cover layer 406: Connector 407: The first passivation layer 408: The second passivation layer 409: conductive pad 410: Connection terminal 411: Metal under bump 500: Semiconductor structure 1100, 1101, 1102, 1103, 1104, 1200, 1201, 1202, 1203, 1204, 1205, 2205, 2206: steps BR: Region NR: unjoined area E1, E2: Endpoint ER: fringe zone H1, H2: height IF: Interface IR: inner zone IS1, IS2: sag surface P: plane area RC, RC’: recessed RO1, RO2, RO2’: collapsed area S: Fillet area SW1, SW2, SW2’: side walls TSV: base perforation W1, W2, W3, W4, W4’: width

Various aspects of the present disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It is worth noting that, in accordance with industry standard practices, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features can be increased or decreased arbitrarily. 1A to 1J show schematic cross-sectional views of a method for manufacturing a wafer and a wafer bonding structure according to a first embodiment of the present disclosure. 2A to 2C are schematic cross-sectional views of a method for manufacturing a wafer bonding structure according to a second embodiment of the present disclosure. 3A to 3B are schematic cross-sectional views of a method of manufacturing a wafer bonding structure according to a third embodiment of the present disclosure. 4A shows a schematic enlarged cross-sectional view of the edge portion of the conductive layer before the EBR process according to some embodiments of the disclosure. 4B shows a top view of the negative electrode placed on the edge of the wafer during the electroplating process of the conductive layer according to some embodiments of the present disclosure. 4C shows a schematic enlarged cross-sectional view of the edge portion of the conductive layer after the EBR process according to some embodiments of the present disclosure. FIG. 5A shows a schematic cross-sectional view of a wafer according to the first embodiment of the present disclosure. FIG. 5B shows a schematic cross-sectional view of a wafer bonding structure according to some embodiments of the present disclosure. FIG. 6 shows a schematic diagram of a chemical mechanical polishing machine according to some embodiments of the present disclosure. 7 to 8 show a flowchart of manufacturing a wafer according to some examples of the present disclosure.

10: Base 14, 14’: Dielectric layer 16e, 16e’: pad 17, 17’: Additional dielectric layer 18, 18': Bonding dielectric layer 22a, 22a’: Bonding pad 28, 28’: Joint structure 50a, 50a’: Wafer 100a: Wafer stack structure BR: Region NR: unjoined area ER: fringe zone IR: inner zone RO2, RO2’: collapsed area SW1, SW2, SW2’: side walls W3, W4, W4’: width

Claims (9)

A method for forming a wafer bonding structure includes: forming a first wafer, including: providing a semiconductor structure with a first sag area on the edge of the semiconductor structure; and forming an additional dielectric layer to fill the first sag Area; forming a bonding dielectric layer with openings on the semiconductor structure and the additional dielectric layer; forming a conductive layer on the bonding dielectric layer and filling the openings, wherein the additional dielectric The conductive layer above the layer has protrusions; and a removal process is performed to remove the conductive layer on the bonding dielectric layer, and the conductive layer remaining in the opening forms a bonding pad, The removal process includes a planarization process, and the bumps are removed by the planarization process; and the bonding dielectric layer and the bonding of the second wafer to the first wafer pad. The method for forming a wafer bonding structure according to claim 1, wherein providing the semiconductor structure includes forming an interconnection structure on a substrate, wherein the first sag area is in the interconnection structure Formed during the formation process. According to the method for forming a wafer bonding structure as described in claim 1, wherein the removing process does not include the edge ball removing process. The method for forming a wafer bonding structure as described in claim 1, wherein the planarization process removes the main body portion and the edge portion of the conductive layer on the bonding dielectric layer, and the edge portion Including the protrusion. According to the method for forming a wafer bonding structure as described in claim 1, wherein the planarization process further removes a part of the bonding dielectric layer, so that a second sag is formed on the edge of the bonding dielectric layer Area, wherein the size of the second collapsed area is smaller than the size of the first collapsed area. A method for forming a wafer bonding structure includes: forming a first wafer, including: providing a semiconductor structure; forming an additional dielectric layer on the side of the semiconductor structure; and forming an additional dielectric layer on the semiconductor structure and the additional dielectric layer Forming a bonding structure on top includes: forming a bonding dielectric layer with openings; forming a conductive layer on the bonding dielectric layer and filling the openings; performing a planarization process to remove the bonding dielectric layer Part of the conductive layer above; and performing an edge ball removal process to remove residues of the conductive layer located above the bonding dielectric layer after the planarization process, which remains in the The conductive layer in the opening forms a bonding pad; and the bonding structure bonding the second wafer to the first wafer. According to the method for forming a wafer bonding structure as described in claim 6, wherein the planarization process and the edge ball removal process are performed in the same chemical mechanical polishing machine. A wafer bonding structure includes: a first wafer, including: an interconnection structure on a substrate; a bonding structure, which is located above the interconnection structure and is electrically connected to the An interconnect structure; and an additional dielectric layer located on the side of the interconnect structure and between the bonding structure and the interconnect structure; and a second wafer bonded to the first The bonding structure of the wafer, wherein the additional dielectric layer fills a first sag area at the edge of the interconnect structure; the edge of the bonding structure has a second sag area; and the second The width and height of the collapsed area are smaller than the height and width of the first collapsed area. In the wafer bonding structure described in item 8 of the scope of patent application, the ratio of the width of the second wafer to the width of the first wafer is 99% to 99.5%.

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