TWI706390B - Display panel and display device - Google Patents

Abstract

A display panel and a display device are provided. The disaply panel is electrically connected to a gate driving circuit including plural shift registers. The display panel includes (M+1) data lines, an n-th gate line, an (n+1)-th gate line, M jointly connected pixel pairs, M isolated pixel pairs, and M interconnected lines. The M jontly connected pixel pairs include M/2 first jointly connected pixels and M/2 second jointly connected pixels. The M isolated pixel pairs include M/2 first isolated pixels and M/2 second isolated pixels. The interconnected lines are electrically connected between the first isolated pixel pairs and the second jontly connected pixel pairs. Each of the first isolated pixel pairs is corresponding to each of the second jointly connected pixel pairs along a row direction. Moreover, the first isolated pixel pairs are respectively electrically connected to the second jointly connected pixel pairs.

Description

Display panel and display device

The present invention relates to a display panel and a display device, and more particularly to a display panel and a display device applied to ultra-high resolution and narrow width design.

Mobile devices are becoming more and more popular, and many electronic products are equipped with screens for the convenience of users. Therefore, demands for high resolution and narrow bezels are gradually emerging. Among them, high resolution means higher requirements for the drive capability of the screen, and narrow frame means that the width of the drive circuit needs to be smaller. The display device usually includes a display panel, a source driving circuit, and a gate driving circuit. Wherein, the source driver provides the data voltage required by the pixels on the display panel, and the gate driver circuit is used to control the on/off period of the pixels.

When the transistor in the pixel is turned on due to the voltage of the gate line (GL) connected to the shift register (SR), what the transistor receives is transmitted by the source driver The output data voltage will charge the storage capacitor Cs in the pixel. After the storage capacitor Cs is charged by the data voltage, the accumulated charge is used to drive the liquid crystal capacitor Clc.

In conclusion, the transistor in the pixel must be turned on by the gate control signal GL before the storage capacitor Cs in the pixel can be charged by the data voltage. When the storage capacitor Cs in the pixel can be charged at a faster speed, it means that the driving capability of the display device is better. Generally, gate drive The way the circuit generates the gate control signal GL can be divided into two-way driving and unidirectional driving. The following briefly describes these two types of practices. In addition, for ease of description, this article uses a vertical texture to represent red (R) pixels, a horizontal texture to represent green (G) pixels, and a diagonal texture at the top right and bottom left to represent (B) pixels.

Please refer to Figure 1, which is a schematic diagram of a bidirectional driving panel using conventional technology. The gate driving circuit includes buffers 13a, 13b, and shift registers 11a, 11b. The display panel 15 includes a plurality of pixels 15a, 15b, 15c arranged in an array. In this figure, the shift registers 11a and 11b located in the same column generate the same gate control signals (GL) 17a and 17b. The gate control signals (GL) 17a, 17b are transmitted to the pixels 15a, 15b, 15c in the same column via the buffers 13a, 13b.

When the bidirectional driving method is adopted, the pixels 15a, 15b, and 15c in the same column are controlled by the shift registers 11a, 11b on both sides of the display panel 15 respectively. Therefore, the shift register 11a is equivalent to only driving the pixels on the left half of the display panel 15, and the shift register 11b is equivalent to only driving the pixels on the right half of the display panel 15. According to this, the number of pixels to be driven by each shift register 11a, 11b is small, so that a better driving effect can be achieved. However, when the bidirectional driving method is adopted, the shift registers 11a and 11b need to occupy a large area.

Please refer to Figure 2, which is a schematic diagram of a unidirectional driving panel using conventional technology. The gate driving circuit includes buffers 23a, 23b, and shift registers 21a, 21b. The display panel 25 includes a plurality of pixels 25a, 25b, 25c arranged in an array. In this figure, the shift register 21a on the left side of the display panel 25 generates the gate control signal GL to the pixels 25a, 25b, 25c in odd columns; the shift register 21b on the right side of the display panel 25 generates The gate control signal GL is sent to the pixels 25a, 25b, and 25c in even-numbered columns.

When the unidirectional driving method is adopted, the pixels 25a, 25b, and 25c in the same column are controlled only by the shift registers 21a, 21b on one side. Therefore, the allocable pitch length of the shift registers 21a and 21b in the longitudinal direction is longer, so the width in the lateral direction can be reduced. However, when the unidirectional driving method is adopted, each shift register 21a, 21b needs to drive the entire column of pixels 25a, 25b, 25c through the buffer 13a, 13b. Compared with the bidirectional driving method, the driving capability of the shift register 21a, 21b of the unidirectional driving method is poor.

In summary, the two-way drive and one-way drive have their own advantages and disadvantages. The comparison of these two drive modes can be shown in Table 1.

The invention relates to a display panel and a display device. The display panel and display device of the present invention can be applied to ultra-high resolution and narrow side width designs.

According to the first aspect of the present invention, a display panel electrically connected to a gate driving circuit is provided. The display panel is electrically connected to the gate drive circuit. The gate driving circuit includes a first shift register and a second shift register. The first shift register generates the nth gate control signal, and the second shift register generates the (n+1)th gate control signal. Display panel package Including: (M+1) data lines, nth gate line, (n+1)th gate line, M common pixel pairs electrically connected to these data lines, and M isolated pixel pairs . (M+1) data lines are electrically connected to the source driving circuit and parallel to the row direction, wherein each data line receives each data voltage. The nth gate line is electrically connected to the first shift register and parallel to the column direction, and it receives the nth gate control signal. The (n+1)th gate line is electrically connected to the second shift register and parallel to the column direction, which receives the (n+1)th gate control signal. The M commonly connected pixel pairs include: M/2 first commonly connected pixel pairs electrically connected to the nth gate line; and M/2 second commonly connected pixel pairs electrically connected to the (nth +1) Gate lines. The M isolated pixel pairs include: M/2 first isolated pixel pairs and M/2 isolated pixel pairs. The M/2 first isolated pixel pairs are electrically connected to the nth gate line, and they are alternately arranged with the first common pixel pairs along the column direction. The M/2 isolated pixel pairs are electrically connected to the (n+1)th gate line, which are alternately arranged with the second common pixel pairs along the column direction. The position of each first isolated pixel pair along the column direction corresponds to the position of each second common pixel pair along the column direction, and each first isolated pixel pair is electrically connected to each second common pixel pair.

According to the second aspect of the present invention, a display device is provided. The display device includes: a source drive circuit, a gate drive circuit, and a display panel. The source drive circuit outputs (M+1) data voltages. The gate driving circuit includes: a first shift register and a second shift register. The first shift register generates the nth gate control signal; the second shift register generates the (n+1)th gate control signal. The display panel is electrically connected to the source driving circuit and the gate driving circuit. The display panel includes: (M+1) data lines, nth gate line, (n+1)th gate line, M common pixel pairs electrically connected to the data lines, and M isolated Pixel pairs. (M+1) data lines are electrically connected to the source driving circuit and parallel to the row direction, wherein each data line receives each data voltage. The nth gate line is electrically connected to the first shift register The device is parallel to the column direction, and it receives the nth gate control signal. The (n+1)th gate line is electrically connected to the second shift register and parallel to the column direction, which receives the (n+1)th gate control signal. The M commonly connected pixel pairs include: M/2 first commonly connected pixel pairs electrically connected to the nth gate line; and M/2 second commonly connected pixel pairs electrically connected to the (nth +1) Gate lines. The M isolated pixel pairs include: M/2 first isolated pixel pairs and M/2 isolated pixel pairs. The M/2 first isolated pixel pairs are electrically connected to the nth gate line, and they are alternately arranged with the first common pixel pairs along the column direction. The M/2 isolated pixel pairs are electrically connected to the (n+1)th gate line, which are alternately arranged with the second common pixel pairs along the column direction. The position of each first isolated pixel pair along the column direction corresponds to the position of each second common pixel pair along the column direction, and each first isolated pixel pair is electrically connected to each second common pixel pair.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

11a, 11b, 21a, 21b, SR[1], SR[2], SR[N-1], SR[N], SR[1'], SR[2'], SR[(N-1)' ], SR[N']: shift register

13a, 13b, 23a, 23b, 33a, 33b: buffer

17a, 17b, 27a, 27b, GL[1], GL[2], GL[N-1], GL[N], GL[3], GL[4], GL, GL[5]: Gate control Signal (gate line)

15, 25, 35: display panel

15a, 15b, 15c, 25a, 25b, 25c, 35a, 35b, P(1,1)~P(6,8): pixels

3: display device

30: timing controller

32, 50: Source drive circuit

33: Gate drive circuit

351, 41: Active area

353, 43: Inactive area

DL[1], DL[2], DL[3], DL[4], DL[5], DL[6], DL[7], DL, DL[8], DL[9], DL[10 ], DL[11], DL[12], DL[13]: data line

IL13a, IL13b, IL13c, IL24a, IL24b, IL24c, IL57a, IL57b, IL57c, IL68a, IL68b, IL68c, ILx1a, ILx1b, ILx1c, ILx2a, ILx2b, ILx2c, IL35a, IL35b, IL35c, IL46a, IL46b, IL46c, IL7xa, IL7xb, IL7xc, IL8xa, IL8xb, IL8xc, IL: Interconnect wiring

Cs1, Cs2, Cs: storage capacitor

M1, M2: Transistor

Clc1, Clc2, Clc: liquid crystal capacitors

IP: Isolated pixel

JP: Commonly connected pixels

PP(1,1), PP(2,1), PP(3,1), PP(4,1), PP(1,2), PP(2,2), PP(3,2), PP (4,2): pixel pair

IPP: Isolated pixel pair

JPP: Shared pixel pair

A, B, C, D: status

t1~t13: time point

T1~T13, TM1, TM2, TM3, TM4, TM5, TM6,: unit period

Tpc: during precharge

Twt: waiting period

Tup1: During the first update

Tup2: The second data update period

H, L: level

51, 52: source driver

SWa, SWb, SWc: switch control signal

IC[1], IC[2], IC[3], IC[4],: dynamic data line

a1, a2, a3, a4, b1, b2, b3, b4, c1, c2, c3, c4: switch

TM3a, TM3b, TM3c, TM4a, TM4b, TM4c, TM5a, TM5b, TM5c, TM6a, TM6b, TM6c: sub-unit period

PU(1,1), PU(1,2): pixel unit

Figure 1 is a schematic diagram of a bidirectional driving panel using conventional technology.

Figure 2 is a schematic diagram of driving the panel in a unidirectional manner using conventional technology.

Figure 3 is a schematic diagram of driving the panel in a bidirectional manner according to the concept of the present invention.

FIG. 4 is a schematic diagram of the arrangement and connection of pixels on a display panel according to an embodiment of the present invention.

FIG. 5A is a schematic diagram of the internal components of a common pixel according to an embodiment of the invention.

Figure 5B is a schematic diagram of the internal components of an isolated pixel according to an embodiment of the invention.

FIG. 5C is a schematic diagram of the connection mode of driving the pixel transistors on the panel in a bidirectional manner according to the present invention.

FIG. 6A is a schematic diagram summarizing the connection methods of pixels in a display panel according to an embodiment of the present invention.

FIG. 6B is a schematic diagram of the arrangement and connection of pixels on a display panel according to another embodiment of the present invention.

FIG. 7 is a schematic diagram of two types of pixel pairs according to the characteristics of pixels on the display panel.

FIG. 8 is a schematic diagram of the state change of the pixel pair in the display panel according to the embodiment of the present invention.

Figures 9A and 9B are waveform diagrams of signals related to the display panel control shown in Figure 8.

Figures 10A to 10N are schematic diagrams of the state of pixel pairs on the display panel when the display panel of Figure 8 is combined with the signal waveform of Figure 9A.

Figure 11 is a schematic diagram of the level changes of the integrated gate control signals GL[1], GL[2], and GL[3] relative to the state of the pixel pair based on Figures 10A to 10H.

FIG. 12 is a schematic diagram of a display panel according to an embodiment of the present invention, which is further controlled by a demultiplexer.

FIG. 13 is a waveform diagram of signals related to the control of the source driver 51 in the display panel shown in FIG. 12.

Figures 14A, 14B, and 14C show the changes in the unit period TM3 of pixels related to the source driver 51 in the display panel.

Figures 15A, 15B, and 15C show the changes of the pixels associated with the source driver 51 in the unit period TM4 in the display panel.

Figures 16A, 16B, and 16C show changes in the unit period TM5 of the pixels related to the source driver 51 in the display panel.

Figures 17A, 17B, and 17C show the changes in the unit period TM6 of pixels related to the source driver 51 in the display panel.

Fig. 18 is a schematic diagram of a color arrangement method adopted by the pixel unit.

FIG. 19 is a schematic diagram of another color arrangement method adopted by the pixel unit.

As mentioned above, the conventional technology has not yet solved the two requirements for the driving capability of the display panel and the occupied width required to realize the driving circuit. To this end, the present invention proposes a display panel that can improve the driving capability and reduce the width required by the gate driving circuit. Since this case focuses on the driving capability, the operation of the gate driving circuit to generate the gate control signal GL is discussed here. In actual application, the timing controller will control the source drive circuit in response to the gate control signal GL generated by the gate drive circuit, so that the source drive circuit generates the data voltage required by each pixel P correspondingly. Regarding the generation of the data voltage, the color and brightness settings of each pixel P are also involved, which is not specifically described here.

Please refer to FIG. 3, which is a schematic diagram of driving pixels on a display panel in a bidirectional manner according to the concept of the present invention. The display device 3 includes a timing controller 30, a gate driving circuit 33, a source driving circuit 32 and a display panel 35. The gate drive circuit 33 includes buffers 33a, 33b, and shift registers SR[1], SR[2], SR[N-1], SR[N], SR[1'], SR[2' ], SR[(N-1)'], SR[N’]. The display panel 35 includes a plurality of pixels 35a, 35b arranged in an array. It is assumed here that the pixels 35a and 35b are arranged in M rows and Q columns (where Q=N*2). The pixels 35a, 35b receive the (M+1) data voltages transmitted by the source driving circuit 32, and receive the shift registers SR[1], SR[2], SR[N-1 through the buffers 33a, 33b ], SR[N], SR[1'], SR[2'], SR[(N-1)'], SR[N'] issued gate control signals GL[1]~GL[N]. These data voltages can be divided into common data voltages and isolated data voltages according to their uses.

According to the concept of the present invention, the display panel 35 can be further divided into an active area 351 and an inactive area 353. Here, it is assumed that the pixels located in the active area 351 are (N-1)*2 columns, and the pixels P located in the inactive area 353 are 2 columns. In actual applications, the inactive area 353 may include more columns of pixels P. In other words, in Figure 3, the display panel includes M*N*2 pixels P in total. Among them, the pixel P located in the active area 351 corresponds to the (N-1) shift registers SR[1], SR[2], SR[N-1] on the left, and (N-1) on the right ) Shift registers SR[1'], SR[2'], SR[(N-1)']. The pixel P located in the inactive area 353 corresponds to the shift register SR[N] on the left side of the display panel and the shift register SR[N'] on the right side of the display panel.

According to the concept of the present invention, the pixels P on the display panel can be divided into two types. Here, a box with a dot-shaped mesh bottom represents the first-type pixel 35a (isolated pixel IP), and a box without a mesh bottom represents the second-type pixel 35b (commonly connected pixel JP). It can be seen from Figure 3 that every two pixels 35a of the first type and every two pixels 35b of the second type are staggered on the display panel in a checkerboard manner. For example, the connections of the pixels P on the first column and the second column are similar, and the connections of the pixels P on the third column and the fourth column are similar. In the first column and the second column, the pixel P located in the odd row is the first type pixel 35a (isolated pixel IP); the pixel P located in the even row is the second type pixel 35b (commonly connected pixel JP). In the third and fourth columns, the pixel P located in the odd-numbered row is the second-type pixel 35b (commonly connected pixel JP); the pixel P located in the even-numbered row is the first-type pixel 35a (isolated pixel IP). Which is located in The pixels P in the first column and the second column are electrically connected to the gate line GL[1]; the pixels P in the third column and the fourth column are electrically connected to the gate line GL[2].

According to the concept of the present invention, each shift register SR corresponds to two columns of pixels P at the same time, and the pixels P located in the same column simultaneously receive gate control signals synchronously issued by the shift registers SR on both sides GL. For example, the shift registers SR[1] and SR[1'] correspond to the pixels 35a and 35b in the first and second columns at the same time, and the shift registers SR[1] and SR[1' ] Synchronously generate the same gate control signal GL[1] to the pixels 35a and 35b located in the first and second columns. In the same way, the shift registers SR[2], SR[2'] correspond to the pixels 35a, 35b in the third and fourth columns at the same time, and the shift registers SR[2], SR[2 '] synchronously generate the gate control signal GL[2] to the pixels 35a and 35b located in the third and fourth columns.

In Figure 3, the M pixels in each column simultaneously receive the gate control signal GL jointly generated by the shift registers SR on the left and right sides, which can have a better driving capability. On the other hand, because each shift register SR corresponds to two columns of pixels P, the available length of the shift register SR in the vertical direction (row direction) is longer, thereby saving the horizontal direction (column direction). The width of the upper part can achieve the effect of narrow border. For the detailed method of the present invention, please refer to the following description.

Please refer to FIG. 4, which is a schematic diagram of the arrangement and connection of pixels P on the display panel according to one embodiment of the present invention. For ease of description, this article uses M to represent the total number of rows of pixels P, Q to represent the total number of columns of pixels P, and N to represent the number of columns of the shift register SR and the number of gate control signals GL. Suppose here that M=6, N=3, Q=N*2. The display panel has (M+1) data lines DL parallel to the row direction, and N gate lines GL parallel to the column direction. Wherein, each gate line GL includes a first portion (upper) and a second portion (lower) that are parallel to each other.

According to the concept of the present invention, the display panel can be divided into an active area 41 and an inactive area 43. Among them, the inactive area 43 must include at least two rows of pixels P. The connection between the pixel P located in the active area 41 and the pixel P located in the non-active area 43 and the data line DL and the gate line GL The formulas are similar, so there is no special distinction. It is assumed here that the active area 41 corresponds to the pixels P located in the first to sixth columns, and the non-active area 43 corresponds to the pixels P located in the seventh to eighth columns.

For ease of description, the variables m and q are used to represent the row and column of the pixel P, and the variable n is used to represent the order of the gate line GL. Among them, because each gate line GL is connected to two columns of pixels P, q=2*n-1 or q=2*n. M is a positive even number, N, m, n, and q are all positive integers, and m≦M, n≦N, q≦Q, Q=N*2.

In this drawing, a total of 48 pixels P arranged in six rows (where M=6 rows) and eight columns (where Q=4*2=8 columns) are drawn. For ease of description, the position of each pixel P is represented here in a coordinate manner. For example, the pixel P(1,1) is located in the first row and the first column, the pixel P(1,2) is located in the first row and the second column, and the rest It can be deduced by analogy. In order to specifically describe the connection relationship between each pixel P and the data line DL and the gate line GL, the following description is made in the horizontal direction (column) and vertical direction (row) respectively.

First, the connection relationship of pixels will be explained in terms of the column direction. The pixels P located in the first column (where q=1) and the second column (where q=2) are electrically connected to the gate line GL[1] (where n=1). In the two columns of pixels P, the pixels P located in odd rows (where m=1, 3, or 5) are not electrically connected to any data line DL; those located in even rows (where m=2, 4, or 6) The pixels P are electrically connected to different data lines DL according to the number of rows. Furthermore, among the pixels P(1,1)~P(M,1) located in the first column (q=1), the pixels P located in the even rows (where m=2, 4, or 6) are electrically connected to The data line DL[m] located on the left side of it; located in the second column (q=2) pixels P(1,2)~P(M,2), located in the even-numbered row (where m=2, 4 or 6 The pixel P of) is electrically connected to the data line DL[m+1] on its right side.

Furthermore, the pixels located in the third column (q=3) and the fourth column (q=4) are electrically connected to the gate line GL[2] (where n=2). In the two columns of pixels P, pixels P located in odd rows (where m=1, 3, or 5) will be electrically connected to different data lines DL according to the number of columns; located in even rows (where m= The pixel P of 2, 4 or 6) is not electrically connected to any data line DL. Furthermore, among the M pixels P(1,3)~P(M,3) in the third column (q=3), they are located in odd rows (where m=1, 3 or 5) M/2 pixels P are electrically connected to the data line DL[m] on the left; and, in the fourth column (q=4), M pixels P(1,4)~P(M In 4), M/2 pixels P located in odd rows (where m=1, 3, or 5) are electrically connected to the data line DL[m+1] located on the right side thereof.

Isolated pixels P(2,7), P(2,8), P(4,7), P(4,8), P(6,7), P(6,8) in the inactive area 43 No special control is required. On the other hand, the common pixels P(1,7), P(1,8), P(3,7), P(3,8), P(5,7), P (5,8), because it controls the isolated pixels P(1,5), P(1,6), P(3,5), P(3,6), P(5,5) and P(5,6) are related, and the gate control circuit and the source drive circuit still need to provide the gate line GL and the data line DL corresponding to the common pixel JP in the non-active area 43.

For example, the control of the common pixel P(1,7) located in the non-active area 43 of the first row is related to the isolated pixel P(1,5) also located in the active area of the first row, and the non-active area The control of the common pixel P(1, 8) of the active area 43 is related to the isolated pixel P(1, 6) also located in the active area of the first row. The correlation between the remaining pixels can also be deduced by analogy, so it is not repeated here.

Next, the connection relationship of the pixels P will be explained in terms of the row direction. The pixels P(1,1), P(1,2), P(1,3), P(1,4), P(1,5), P( 1,6), P(1,7), P(1,8), pixels P(1,3), P(1,7) are connected to the data line DL[1]; pixel P(1,4) , P(1,8) is connected to data line DL[2]; pixel P(1,1), P(1,2), P(1,5), P(1,6) are not connected to any data line DL. The connection mode between the other pixels P located in odd rows (ie, m=3, 5) and the data line DL is similar to the connection mode of the pixels P located in the first row. It can be inferred from Figure 4 that the alignment is in each odd-numbered row (where m=1, 3, 5, q=1~Q) in the pixel P(m,q), and the even-numbered gate line GL[n]( Among them, n=2, 4) connected Q/2 pixels, among them, those located in the q=n*2-1th column are connected to the data line DL[m] in the mth row; in the q=n*2th column The column is connected to the data line DL[m+1] of the (m+1)th row. On the other hand, Q/2 pixels located in odd rows (where m=1, 3, 5) and connected to odd gate lines GL[n] (where n=1, 3) are isolated pixels IP, It is not connected to any data line DL.

Similarly, in the pixel P(m,q) located in the second row (where m=2, q=1~Q), the pixels P(2,1) and P(2,5) are connected to the data line DL [2]; Pixels P(2,2), P(2,6) are connected to the data line DL[3]; Pixels P(2,3), P(2,4), P(2,7), P (2,8) Not connected to any data line DL. The connection between the other pixels P(m, q) located in the even rows (where m=4, 6) and the data line DL is similar to the connection between the pixels P located in the second row. It can be inferred from Figure 4 that the alignment is in the Q pixels P(m,q) of each even-numbered row (where m=2, 4, 6, q=1~Q), and the odd-numbered gate gate line GL[ n] (where n=1,3) connected to Q/2 pixels P(m,q), those located in the q=n*2-1th column are connected to the data line DL[m]; located in the qth =n*2 rows are connected to the data line DL[m+1]. On the other hand, Q/2 pixels P(m, q) located in even rows (where m=2, 4, 6) and connected to even-numbered gate lines GL[n] (where n=2, 4) ) Is an isolated pixel IP, and the isolated pixel IP is not connected to any data line DL.

Further observing the pixels P(m,q) not connected to the data line DL, the following relationship can be summarized according to the number of rows where the pixels P(m,q) are located. That is, among the pixels P(m, q) located in odd rows (where m=1, 3, 5), the pixels P(m) connected to the odd gate line GL[n] (where n=1, 3) ,q), which is not directly electrically connected to any data line DL; and, in pixels P(m,q) in even rows (where m=2,4,6), and even gate lines GL[n] (Where n=2, 4) the connected pixels P(m, q) are not directly electrically connected to any data line DL.

According to the concept of the present invention, these isolated pixels IP that are not connected to any data line DL cannot directly receive their corresponding isolated data voltages from the data lines DL[m] and DL[m+1]. More specifically, when the pixel P(m, q) is located in an odd row (where m=1, 3, 5) and is connected to an odd gate line GL[n] (where n=1, 3), The pixel P(m,q) is an isolated pixel IP, and the isolated data voltage displayed by the pixel P(m,q) needs to pass through the pixel located in the same m-th row but connected to the next gate line GL[n+1] P(m,q+2) transmission. When the pixel P(m,q) is located in an even-numbered row (where m=2,4,6) and is connected to the even-numbered gate line GL[n] (where n=2,4), the pixel P(m, q) is the isolated pixel IP, And the isolated data voltage displayed by the pixel P(m,q) needs to be transmitted through the pixel P(m,q+2) which is also located in the mth row but connected to the next gate line GL[n+1].

In order to realize this method of indirectly transmitting the data voltage from the co-connected pixels JP located in other columns, the present invention provides an interconnection line IL between the isolated pixels IP and the co-connected pixels JP across the column. The following describes how to set the interconnection wiring IL. The following are the pixels P located in odd-numbered rows (where m=1, 3, 5) and even-numbered rows (where m=2, 4, 6) respectively to illustrate the connection mode of the interconnection line IL.

In Figure 4, the pixels P(1,1), P(3,1), P(5, 1) Through the interconnection lines IL13a, IL13b, and IL13c, they are respectively connected to the pixels P(1,3), P(3,3), P(5,3) in the same row and in the third column (where q=3). ) Connected. The pixels P(1,2), P(3,2), P(5,2) located in odd rows (where m=1,3,5) and located in the second column (where q=2) pass through each other The connecting lines IL24a, IL24b, and IL24c are respectively connected to the pixels P(1,4), P(3,4), P(5,4) located in the same row and located in the fourth column (where q=4). Pixels P(1,5), P(3,5), P(5,5) located in odd rows (where m=1,3,5) and located in the fifth column (where q=5) pass through each other The connecting lines IL57a, IL57b, and IL57c are respectively connected to the pixels P(1,7), P(3,7), P(5,7) located in the same row and located in the seventh column (where q=7). Pixels P(1,6), P(3,6), P(5,6) located in odd rows (where m=1,3,5) and located in the sixth column (where q=6) pass through each other The connecting lines IL68a, IL68b, and IL68c are respectively connected to the pixels P(1,8), P(3,8), P(5,8) located in the same row and located in the eighth column (where q=8).

Further summarizing the foregoing relationship between the interconnection line IL related to the pixel P located in odd rows (where m=1, 3, 5), the following relationship can be seen. Among the pixels P located in odd rows (where m=1, 3, 5), the pixels P connected to odd gate lines GL[n] (where n=1, 3) are in the same row but with the gate An interconnection line ILn(n+1) is provided between the pixels P connected to the line GL[n+1]. In other words, among the Q pixels located in each odd-numbered row (where m=1, 3, 5), and the even-numbered gate line GL[n] (where n=2, 4) The connected pixels P(m,n) have interconnection lines IL(n-1)n between the pixels P located in the same row but connected to the gate line GL[n-1].

In Fig. 4, the pixels P(2,1), P(4,1), P(6, 1) The interconnection wires ILx1a, ILx1b, and ILx1c are floating; the pixels P(2,2), P( located in the even rows (where m=2,4,6) and located in the second column (q=2) 4, 2), P(6, 2) interconnection wiring ILx2a, ILx2b, ILx2c is floating. The pixels P(2,3), P(4,3), P(6,3) located in the even rows (where m=2,4,6) and located in the third column (where q=3) pass through each other The connecting lines IL35a, IL35b, and IL35c are respectively connected to the pixels P(2,5), P(4,5), P(6,5) located in the same row and located in the fifth column (where q=5). The interconnection wiring of pixels P(2,7), P(4,7), P(6,7) located in even rows (where m=2,4,6) and located in the seventh column (q=7) IL7xa, IL7xb, IL7xc are floating; pixels P(2,8), P(4,8) located in even rows (where m=2,4,6) and located in the eighth column (where q=8) , P(6,8) interconnection wiring IL8xa, IL8xb, IL8xc is floating.

Further summarizing the foregoing relationship between the interconnection line IL related to the pixel P located in the even-numbered row (where m=2, 4, 6), the following relationship can be seen. Among the pixels P located in the even rows (where m=2,4,6), the pixels P connected to the even-numbered gate line GL[n] (where n=2,4) are located in the same row but with the gate An interconnection line ILn(n+1) is provided between the pixels P connected to the line GL[n+1]. In other words, among the Q pixels P located in odd rows (where m=1, 3, 5), the pixels P connected to odd gate lines GL[n] (where n=1, 3) are located at the same An interconnection line IL(n-1)n is provided between the pixels P connected to the gate line GL[n-1]. Wherein, when n=1 or n=N, the interconnection wires ILx1 and ILNx connected to the pixels located in the even-numbered rows (where m=2, 4, 6) are floating.

Please refer to FIG. 5A, which is a schematic diagram of the internal components of the shared pixel JP according to an embodiment of the invention. The common pixel JP includes a transistor M1, a storage capacitor Cs1, and a liquid crystal capacitor Clc1 that are electrically connected to each other. Among them, the transistor M1 is electrically connected to the data line DL and the gate line GL, and determines whether to turn on the common data voltage transmitted by the data line DL according to the level of the gate control signal GL To the storage capacitor Cs1, the common data voltage is used to charge the storage capacitor Cs1. In addition, if the transistor M1 is turned on according to the level of the gate control signal GL, the interconnection line IL can also transmit the data voltage to the outside of the common pixel JP. The data voltage received through the shared pixel JP and transmitted to the outside will be used as the isolated data voltage corresponding to the isolated pixel IP.

Please refer to FIG. 5B, which is a schematic diagram of the internal components of the isolated pixel IP according to the embodiment of the invention. The isolated pixel IP also includes a transistor M2, a storage capacitor Cs2, and a liquid crystal capacitor Clc2 electrically connected to each other. Wherein, the transistor M2 is electrically connected to the interconnection line IL and the gate line GL, and determines whether to conduct according to the level of the gate control signal GL. If the transistor M2 is turned on, the isolated data voltage is conducted to the storage capacitor Cs2 through the interconnection line IL, and then the storage capacitor Cs2 is charged by the isolated data voltage. In addition, the brightness of the liquid crystal capacitor Clc1 varies according to the charge stored in the storage capacitor Cs1.

Comparing the co-connected pixel JP in Figure 5A with the isolated pixel IP in Figure 5B, it can be seen that the co-connected pixel JP can charge the storage capacitor Cs1 via the common data voltage transmitted by the data line DL; the isolated pixel IP is connected via interconnection The isolated data voltage transmitted by IL charges the storage capacitor Cs2. In addition, the types of the liquid crystal capacitors Clc1 and Clc2 and their corresponding colors on the color filter are not limited.

Please refer to FIG. 5C, which is a schematic diagram of the connection mode of driving the pixel transistors on the panel in a bidirectional manner according to the present invention. This diagram further takes several pixels P located in the upper left corner in Figure 4 as an example (where m=1~2, n=1~2, q=1~4) to illustrate the liquid crystal capacitor Clc in the pixel P , The connection between the transistor and the storage capacitor Cs.

In this figure, each pixel P(m, q) (where m=1~M, q=1~Q) includes a liquid crystal capacitor Clc, a transistor, and a storage capacitor Cs that are interconnected with each other. Wherein, the other end of the storage capacitor Cs is connected to the common level (COM), and the gate of the transistor is connected to the gate line GL[n] corresponding to the position of the pixel P(m,q). According to the position of the pixel position P(m,q), a part of the transistor (For example, the transistors in pixels P(2,1) and P(1,3)) The other end may be connected to the data line DL[m] on the left side of the pixel P(m,q); a part of the transistor (For example, the transistors in pixels P(2,2), P(1,4)) may be connected to the data line DL[m+1] on the right side of the pixel P(m,q); there are other Some transistors (for example, the transistors in pixels P(1,1), P(1,2), P(2,3), P(2,4)) are not connected to any Data line DL.

The transistors in the pixels P(1,1), P(1,2), P(2,3), P(2,4) that are not connected to any data line DL will be connected to the same row but spaced apart One column of pixels P. For example, the transistor in the pixel P(1,1) is electrically connected to the transistor and the storage capacitor Cs in the pixel (1,3) through the interconnection line IL13a; The connecting line IL24a is electrically connected to the transistor and the storage capacitor Cs in the pixel (1,4); the transistor in the pixel P(2,3) is electrically connected to the pixel P(2,5) through the interconnection line IL35a The transistor (not shown) and the storage capacitor Cs (not shown); and, the transistor in the pixel P(2,4) is electrically connected to the capacitor in the pixel P(2,6) through the interconnection line IL46a Crystal (not shown) and storage capacitor Cs (not shown).

Please refer to FIG. 6A, which is a schematic diagram of the arrangement and connection of pixels P on a display panel according to another embodiment of the present invention. In this figure, the configuration of the pixel P(m,q) is similar to that of Figure 4 but slightly different. That is, the connection method of pixels P(m,q) located in odd rows (where m=1,3,5) in Figure 6A is similar to that in even rows in Figure 4 (where m=2,4,6 ) The connection mode of the pixel P; the connection mode of the pixel P(m,q) in the even row (where m=2,4,6) in Figure 6 is similar to the connection mode in the odd row in Figure 4 (where m =1,3,5) the connection mode of the pixel P(m,q). In addition, in FIG. 6A, the structure of the common pixel JP in FIG. 5A and the structure of the isolated pixel IP in FIG. 5B can also be applied.

Based on the similarity of this connection relationship, the connection method of Figure 6A is not specifically described here. However, the aforementioned connection between each pixel P and each gate line GL and data line DL, as well as the connection method of the interconnection line IL between each column of pixels P, will be because the pixel P(m,q) is located Odd-numbered rows may be different from even-numbered rows. The connection relationship of the pixels P in this part can be analogized to the description of Figure 4 above, and will not be detailed here.

According to the concept of the present invention, the way in which the isolated pixel IP and the common pixel JP located in another column are connected through the interconnection line IL may also be different. FIG. 6B is another embodiment illustrating the connection method of the isolated pixel IP and the common pixel JP.

Please refer to FIG. 6B, which is a schematic diagram of the arrangement and connection of pixels on a display panel according to another embodiment of the present invention. Although in this embodiment, the way in which the isolated pixel IP is connected to the common pixel JP through the interconnection line IL is slightly different from that in Figure 4, the control method of the isolated pixel IP receiving the data voltage through the common pixel JP is roughly similar. .

In Figure 6B, the pixels P(1,1), P(3,1), P(5, 1) Connected to the pixels P(1,4), P(3,4), P(5,4) located in the same row and located in the fourth column (where q=4) through the interconnection line IL. The pixels P(1,2), P(3,2), P(5,2) located in odd rows (where m=1,3,5) and located in the second column (where q=2) pass through each other The connecting lines IL are respectively connected to the pixels P(1,3), P(3,3), P(5,3) located in the same row and located in the third column (where q=3). In other words, among Q pixels P located in odd-numbered rows (where m=1, 3, 5), the common pixel JP connected to even-numbered gate line GL[n] (where n=2, 4) is An interconnection line IL is provided between the isolated pixels IP in the same row but connected to the gate line GL[n-1].

In Figure 6B, the pixels P(2,1), P(4,1), P(6, 1) The interconnection line IL is floating; the pixels P(2,2) and P(4,2) located in the even rows (where m=2,4,6) and located in the second column (q=2) The interconnection IL of P(6,2) is floating. The pixels P(2,3), P(4,3), P(6,3) located in the even rows (where m=2,4,6) and located in the third column (where q=3) pass through each other The connecting lines IL are respectively connected to pixels P(2,6), P(4,6), and P(6,6) located in the same row and located in the sixth column (where q=6). Pixels P(2,4), P(4,4), P(6,4) located in even rows (where m=2,4,6) and located in the fourth column (q=4) are interconnected IL and are located at the same The pixels P(2,5), P(4,5), and P(6,5) in the fifth column (where q=5) are connected. In other words, among the Q pixels P located in odd rows (where m=1, 3, 5), the common pixel JP connected to the odd gate line GL[n] (where n=1, 3) and An interconnection line IL is provided between isolated pixels IP located in the same row but connected to the gate line GL[n-1].

In the pixel P located in the first row (where m=1), the pixels P(1,3), P(1,7) are connected to the data line DL[1]; the pixels P(1,4), P(1 ,8) is connected to the data line DL[2]; there are some pixels P(1,1), P(1,2), P(1,5), P(1,6) that are not connected to any Data line DL. The connection mode between the other pixels P located in odd rows (ie, m=3, 5) and the data line DL is similar to the connection mode of the pixels P located in the first row. It can be inferred from Fig. 4 that in the pixel P of each odd-numbered row (where m=1, 3, 5), the Q connected to the even-numbered gate line GL[n] (where n=2, 4) /2 pixels P, among them, those in the q=n*2-1th column are connected to the data line DL[m] in the mth row; those in the q=n*2th column are connected to the (m+1)th row The data line DL[m+1] is connected. On the other hand, Q/2 pixels located in odd rows (where m=1, 3, 5) and connected to odd gate lines GL[n] (where n=1, 3) are isolated pixels IP, Not connected to data line DL.

Similarly, in the pixel P located in the second row (where m=2), the pixels P(2,1) and P(2,5) are connected to the data line DL[2]; the pixel P(2,2) , P(2,6) is connected to data line DL[3]; pixel P(2,3), P(2,4), P(2,7), P(2,8) are not connected to any data line DL. The connection between the other pixels P located in the even rows (where m=4, 6) and the data line DL is similar to the connection between the pixels P located in the second row. It can be inferred from Figure 4 that the alignment is in Q pixels in each even-numbered row (where m=2,4,6), and is connected to odd-numbered gate control line GL[n] (where n=1,3) For Q/2 pixels P, those in the q=n*2-1th row are connected to the data line DL[m]; those in the q=n*2th row are connected to the data line DL[m+1]. On the other hand, Q/2 pixels P located in the even-numbered rows (where m=2,4,6) and connected to the even-numbered gate line GL[n] (where n=2,4) are isolated pixels IP , Is not connected to any data line DL.

Further observing the pixels P that are not connected to the data line DL, the following relationship can be summarized according to the number of rows where the pixels P are located. That is, in pixels P located in odd rows (where m=1, 3, 5), pixels P connected to odd gate lines GL[n] (where n=1, 3) are not directly electrically connected to Any data line DL; and, in pixels P located in even-numbered rows (where m=2, 4, 6), pixels P connected to even-numbered gate lines GL[n] (where n=2, 4) are also It is not directly electrically connected to any data line DL.

Please refer to FIG. 7, which is a schematic diagram of two types of pixel pairs PP according to the characteristics of pixels P on the display panel. In order to further illustrate the influence of the waveform change of the gate line GL on the pixels, two adjacent pixels P are further defined as a pixel pair (PP for short). Fig. 7 is based on the pixel arrangement of Fig. 4, and the correspondence between the arrangement of pixels P in Figs. 6A and 6B and the pixel pair PP will not be described in detail here.

For ease of description, the display panel shown in FIG. 7 does not draw the data line DL, and it is assumed here that M=4, Q=10, and N=5. Among them, the pixel pair PP refers to two pixels P located on the same row, adjacent to each other, and connected to the same gate line GL. For example, in Figure 7, the pixel P(1,1) and the pixel P(1,2) correspond to the pixel pair PP(1,1). The correspondence between the remaining pixel pairs PP and the pixel P can be derived by analogy, and will not be described in detail here.

The pixels P on the left side of FIG. 7 are drawn on the display panel; these pixels P can correspond to the pixel pairs PP drawn in the middle of FIG. 7. Further, the display panel in the middle of FIG. 7 can be simplified to the drawing on the right side of FIG. 7. That is, the pixel pair PP(1,1), PP(2,1), PP(3,1), PP(4,1), PP(1,2), PP(2,2), PP(3 ,2), PP(4,2) present the connection relationship on the display panel.

Based on the aforementioned connection mode of the pixel P, the pixel pair PP can also be divided into two types according to the connection mode of the pixel P contained therein. One is an isolated pixel pair that is not connected to any data line DL (isolated pixel pair, referred to as IPP), and the other is a jointly connected pixel pair (JPP) connected to the data line DL. Here, the dotted mesh bottom represents isolated pixels For IPP, a box without the bottom of the screen represents the shared pixel pair JPP. It can be seen from the figure that the two types of pixel pairs PP are staggered and arranged on the display panel.

This definition of the isolated pixel pair IPP and the shared pixel pair JPP can also be applied to the display panels shown in Figures 6A and 6B. Accordingly, the pixels P on the display panel of FIG. 4 and FIG. 6A can be represented by pixel pairs PP. Table 2 sorts out the pixel pair PP on the display panel of Fig. 4 and Fig. 6A and Fig. 6B depending on the position and determines the type of the pixel pair PP to which they belong.

For the display panel in Figure 4, when n is an odd number (ie, n=1,3), the pixel pair located in odd rows (ie, m=1,3) is an isolated pixel pair IPP; , M=2,4,6) the pixel pair JPP. On the other hand, when n is an even number (i.e., n=2,4), the pixel pair PP located in odd-numbered rows (i.e., m=1,3) is the common pixel pair JPP; located in even-numbered rows (i.e., m= The pixel pairs of 2,4,6) are isolated pixel pairs IPP. For the display panel in Figure 6, when n is an odd number (ie, n=1,3), the pixel pair PP located in odd rows (ie, m=1,3) is the common pixel pair JPP; The pixel pair PP of the row (ie, m=2, 4, 6) is an isolated pixel pair IPP. On the other hand, when n is even (ie, When n=2,4), the pixel pair PP located in odd-numbered rows (ie, m=1,3) is an isolated pixel pair IPP; pixel pairs PP located in even-numbered rows (ie, m=2,4,6) are common Connect the pixel pair JPP.

If the pixel pair PP located in the mth row and the nth column is represented as PP(m,n), the pixel pair PP(m,n) includes two pixels P, and the positions of the two pixels P on the panel can be Expressed as P(m,2*n-1), P(m,2*n). When the pixel pair PP(m,n) is an isolated pixel pair IPP, the pixels P(m,2*n-1), P(m,2*n) cannot be separated from the data lines DL[m], DL[m+1 ] Directly receive data voltage. The data voltages transmitted from the data lines DL[m] and DL[m+1] will first be transmitted to P(m,2*n+1), P(m,2*(n+1)). After that, the transistors in P(m,2*n+1) and P(m,2*(n+1)) are turned on and transmitted to the pixels P(m,2*n-1), P (m,2*n). When the pixel pair PP(m,n) is the shared pixel pair JPP, the pixel pair PP(m,n) is electrically connected to the data lines DL[m], DL[m+1], and the gate line GL[n] . At this time, the pixels P(m, 2*n-1) and P(m, 2*n) can directly receive the data voltage transmitted by the data line DL through the data lines DL[m] and DL[m+1], respectively. In addition, the pixels P(m,2*n-1) and P(m,2*n) not only receive the data voltage from the data lines DL[m], DL[m+1], they are also turned on by the internal transistors And transfer to the pixels P(m,2*(n-1)-1), P(m,2*(n-1)).

In order to further explain the control method of the display panel shown in FIGS. 4 and 6A and 6B, the state of the pixel P in the pixel pair PP is defined as the four states shown in Table 3 below. Among them, two pixels P belonging to the same pixel pair PP have the same state transition.

State A means that the pixel pair PP has not been charged or received the data voltage during the unit period; State B means the pixel pair PP is charged during the unit period, but the data voltage provided by the data line DL is not for the pixel pair PP (this A situation where the data voltage does not correspond to the pixel pair PP but the storage capacitor Cs of the pixel pair PP is still charged, which can be regarded as pre-charging the storage capacitor Cs of the pixel pair PP); state C represents that the pixel pair PP is charged during the unit period Charging, and the data voltage provided by the data line DL indeed corresponds to the pixel pair PP; and, the state D represents that the pixel pair PP has been written with the correct data voltage, and the storage capacitor Cs of the pixel pair PP has been previously charged, so The storage capacitor Cs of the pixel pair PP does not need to be charged during the unit period. In this article, state A is defined as the first preliminary state; state B is defined as the second preliminary state; state C is defined as the update state; and state D is defined as the display state. Among them, when the pixel pair PP is in the state D, it means that the pixel pair PP can display the pixel data normally. Accordingly, when each pixel pair PP on the display panel is in the state D, the display panel can display a complete picture normally.

For the convenience of description, the following only uses the example in FIG. 4 to explain how the display panel changes the state of the pixel pair PP in response to the change of the gate line GL. Regarding the control methods of Figures 6A and 6B, those skilled in the technical field to which this case belongs can make slight modifications and apply them, which will not be detailed here.

Please refer to FIG. 8, which is a schematic diagram of the state change of the pixel pair in the display panel according to the embodiment of the present invention. Regardless of the display panels in Figures 4, 6A, and 6B, when the pixel pair PP belongs to the common pixel pair JPP, there are five stages of state changes; when the pixel pair PP belongs to the isolated pixel pair IPP, there are two stages of state changes Variety.

According to the concept of the present invention, those belonging to the shared pixel pair JPP have their state changes in order of state B, state A, state B, state C, and state D; those belonging to the isolated pixel pair IPP have their state changes in order of state C , State D. Among them, the state change process and period of the shared pixel pair JPP located in the same column are consistent with each other, and the isolated pixel pair IPP located in the same column, the state change The process and period are consistent with each other. For ease of description, the following description will continue the labeling in Figure 7. How the pixel pair PP has different state changes according to the type (IPP or JPP) to which it belongs, will be further explained in Figures 9A, 9B, and 10A~10N.

Please refer to Figure 9A, which is a waveform diagram of the signals related to the display panel control shown in Figure 8. For ease of description, here are defined time points t1 to t13 along the time axis, and multiple unit periods T1 to T13 divided according to time points t1 to t13. The length of each unit period T1~T13 is equal to each other. From top to bottom along the vertical axis are gate control signals GL[1]~GL[5].

It can be seen from Fig. 9A that the waveform change of each gate control signal GL[n] (where n=1~5) has the following pattern in Fig. 9B. When the display panel is used to display a screen data, the gate control signals GL[1]~GL[5] on the display panel will generate the waveform shown in Figure 9B in turn. When the display panel displays the next screen data, the gate control signals GL[1]~GL[5] on the display panel will again generate the waveform as shown in Figure 9B. That is, for the gate control signals GL[1] to GL[5], the generation frequency of the waveform in Figure 9B corresponds to the update frequency of the display screen.

First, the gate control signal GL[n] is at the low level (L) first, and secondly, the gate control signal GL[n] is raised to the high level (H) during the precharge period Tpc. After the pre-charge period Tpc is the waiting period Twt, the gate control signal GL[n] returns to the low level (L) at this time. After the waiting period Twt ends, there is a first data update period Tup1 and a second data update period Tup2. At this time, the gate control signal GL[n] is at a high level (L). After the second data update period Tup2 ends, the gate control signal GL[n] will drop to the low level (L) again, and continue to be maintained at the low level (L).

Among them, the precharge period Tpc, the waiting period Twt, the first data update period Tup1 and the second data update period Tup2 all correspond to a unit period. In addition, there is a time difference of two unit periods between adjacent gate lines GL[n] and GL[n+1]. For example, the precharge period Tpc of the gate control signal GL[1] is the unit period T1; the precharge period Tpc of the gate control signal GL[2] is the unit period T3. Therefore, the precharge period Tpc of the gate control signal GL[2] corresponds to the gate The first data update period Tup1 of the gate control signal GL[1], and the waiting period Twt of the gate control signal GL[2] corresponds to the second data update period Tup2 of the gate control signal GL[1].

Please refer to Figures 10A to 10N, which are schematic diagrams of the state of the pixel pair PP on the display panel when the display panel of Figure 8 is combined with the signal waveform of Figure 9A. Hereinafter, along the time axis of FIG. 9A, the influence of the changes in the levels of the gate control signals GL[1] to GL[5] on the pixels will be explained one by one. In addition, in response to this change in the control method, the timing controller will adjust the data voltage transmission sequence accordingly. Regarding the data voltage switching generated by the timing controller, it can be modified by those skilled in the art to which this case belongs based on the connection method of the pixel P, the color of the pixel P, the change of the gate line GL, and other parameters, so there is no special description here.

For ease of description, in the figures 10A to 10N, the pixel pair PP marked with a bold frame line represents that the state of the pixel P in the pixel pair PP changes during the unit period. And, using the circled selection of the dashed curve, it means that the pixels P in the PP are directly/indirectly charged according to the data voltage during the unit period. Among them, the thicker line represents that the gate control signal GL is at a high level; the thinner line represents that the gate control signal GL is at a low level. The behavior of the pixel pair PP mentioned below also refers to the behavior of the two pixels P in the pixel pair PP.

For example, if it is mentioned that the pixel pair PP is charged, it means that the transistors included in the two pixels P in the pixel pair PP are turned on, and the storage capacitors Cs included in the two pixels P in the pixel pair PP are turned on through the transistors. Receive data voltage and charge. In addition, to further distinguish the charging method of the pixel pair PP, it can be different according to the type of the pixel pair PP. If it is a shared pixel pair JPP, the charging method is to directly receive the data voltage from the data line DL and charge directly (hereinafter referred to as direct charging); if it is an isolated pixel pair IPP, the charging method is through the next gate The common-connected pixel pair JPP connected to the line GL and the interconnection line IL between the common-connected pixel pair JPP indirectly receive the data voltage (hereinafter referred to as indirect charging).

Figure 10A shows the display panel at time t1. At this time, the display panel has not yet started to operate. Therefore, the gate lines GL[1]~GL[5] are all low level (L).

Figure 10B shows the state of each pixel pair PP in the unit period T1 of the display panel controlled by the gate control signals GL1~GL[5]. Please refer to the unit period T1 in Figure 9A and Figure 10B at the same time. At this time, the level of the gate control signal is GL[1]=H, and GL[2]=GL[3]=GL[4]=GL[5]=L. It can be seen from FIG. 9A that the unit period T1 corresponds to the precharge period Tpc of the gate line GL[1]. At the same time, the shared pixel pair JPP (ie, the pixel pair PP(2,1), PP(4,1)) connected to the gate line GL[1] directly receives the data voltage from the data line DL and charges it. According to the concept of the present invention, the data voltage transmitted by the data line DL at this time is not the data voltage corresponding to the display of the pixel pair PP(2,1), PP(4,1). Therefore, in Figure 10B, the pixel pair PP(2,1) and PP(4,1) are in the state B.

On the other hand, the isolated pixel pair IPP (ie, the pixel pair PP(1,1), PP(3,1)) connected to the gate line GL[1] does not receive the data voltage, so it remains in the non-acting state . It can be seen from the circled location of the dashed curve that only the pixels charge PP(2,1) and PP(4,1) directly.

Figure 10C shows the state of the pixel pair PP during the unit period T2 of the display panel controlled by the gate lines GL1~GL[5]. Please refer to the unit period T2 in Figure 9A and Figure 10C at the same time. At this time, the level of the gate control signal is GL[1]=GL[2]=GL[3]=GL[4]=GL[5]=L. It can be seen from FIG. 9A that the unit period T2 corresponds to the waiting period Twt of the gate line GL[1]. During the unit period T2, no pixel is charged to PP. Therefore, the common pixel pair JPP connected to the gate line GL[1] transitions from the original state B to the state A, while the isolated pixel pair IPP connected to the gate line GL[1] and the pixel pairs PP in other columns Still remained inactive.

FIG. 10D shows the state of the pixel pair PP during the unit period T3 of the display panel controlled by the gate lines GL1~GL[5]. Please refer to the unit period T3 and 10D in Figure 9A at the same time. At this time, the level of the gate control signal is GL[1]=GL[2]=H, and GL[3]=GL[4]=GL[5]=L. It can be seen from FIG. 9A that the unit period T3 simultaneously corresponds to the first data update period Tup1 of the gate line GL[1] and the precharge period Tpc of the gate line GL[2].

At the same time, the shared pixel pair JPP (ie, the pixel pair PP(2,1), PP(4,1)) connected to the gate line GL[1] is directly charged. On the other hand, the isolated pixel pair IPP (ie, the pixel pair PP(1,1), PP(3,1)) connected to the gate line GL[1] does not receive the data voltage for charging. Furthermore, the common pixel pair JPP (ie, PP(1,2), PP(3,2)) connected to the gate line GL[2] is directly charged, and the gate line GL[ 1] The connected isolated pixels indirectly charge the IPP (ie, the pixel pair PP(1,1), PP(3,1)) through the data voltage transmitted by the interconnection line IL. According to the concept of the present invention, the data voltage on the data line DL at this time corresponds to the display data of the pixel pair PP(1,1), PP(3,1), and the pixel pair PP(1,2), PP(3, 2) Although the data voltage is directly received during this unit period, the data voltage used to charge the pixel pair PP(1,2) and PP(3,2) does not correspond to it.

Accordingly, in the unit period T3, the common pixel pair JPP connected to the gate line GL[1] (that is, the pixel pair PP(2,1), PP(4,1)) transition from the original state A to the state B. At the same time, the isolated pixel pair (ie, the pixel pair PP(1,1), PP(3,1)) connected to the gate line GL[1] receives the correct data voltage and is charged, so it is in state C . At the same time, the common pixel pair JPP (ie, the pixel pair PP(1,2), PP(3,2)) connected to the gate line GL[2] is also connected to the isolated pixel pair (ie, the pixel pair). PP(1,1), PP(3,1)) corresponding to the data voltage charging. Since the data voltage does not correspond to the commonly connected pixel pair JPP, the commonly connected pixel pair JPP is in state B.

Because the pixel pair PP(1,2), PP(3,2) has been charged by the corresponding data voltage during the unit period T3, after the unit period T3 ends (that is, at time t4), the pixel pair PP(1,2) Pixels in PP(3,2) can display pixel data normally.

Moreover, it can be seen from the circled location of the dashed curve that all pixel pairs connected to the gate line GL[1] and the common pixel pair JPP connected to the gate line GL[2] are all charged. This Among the charged pixel pairs PP, those belonging to the shared pixels directly charge the JPP and are in state B, and those belonging to the isolated pixels are indirectly charging the IPP and are in state C.

Figure 10E shows the state of the pixel pair in the unit period T4 of the display panel controlled by the gate lines GL1~GL[5]. Please refer to the unit period T4 and 10E in Figure 9A at the same time. At this time, the level of the gate control signal is GL[1]=H, and GL[2]=GL[3]=GL[4]=GL[5]=L. It can be seen from FIG. 9A that the unit period T4 simultaneously corresponds to the second data update period Tup2 of the gate line GL[1] and the waiting period Twt of the gate line GL[2].

In the unit period T4, the isolated pixel pair IPP (ie, the pixel pair PP(1,1), PP(3,1)) connected to the gate line GL[1] has received the corresponding data voltage before the time point t4 And complete charging, the pixel pair PP(1,1), PP(3,1) will transition from state C to state D.

At this time, the common pixel pair JPP (ie, the pixel pair PP(2,1), PP(4,1)) connected to the gate line GL[1] will be directly charged in the unit period T4. Moreover, the pixel pair PP(2,1), PP(4,1) is charged with the data voltage directly corresponding to it. Therefore, the pixel pair PP(2,1) and PP(4,1) are in the state C during the unit period T4. After the unit period T4 ends (ie, time t5), the common pixel pair JPP connected to the gate line GL[1] starts to display pixel data normally.

On the other hand, in the unit period T4, because the gate line GL[2] is at a low level (GL[2]=L), all pixel pairs connected to the gate line GL[2] (ie, the pixel pair PP(1) ,1), PP(1,2), PP(3,1), PP(3,2)) are not charged. However, the common-connected pixel pair JPP (ie, PP(1,2), PP(3,2)) connected to the gate line GL[2] is because the unit period T3 has been charged for a period of time. Therefore, the pixel pair PP(1,2) and PP(3,2) are in the state A during the unit period T4.

In addition, it can be seen from the circled location of the dashed curve that the common pixel pair JPP connected to the gate line GL[1] is charged and is in state C, and the common pixel pair connected to the gate line GL[2] The JPP is not charged and is in state A. Because the pixel pair PP(2,1), PP(4,1) has been charged by the corresponding data voltage during the unit period T4, after the unit period T4 ends (ie, at time t5), the pixel pair PP(2,1) and PP(4,1) start to display pixel data normally. In other words, starting from time t5, the pixel pair PP in the first row can display pixel data normally.

Figure 10F shows the state of the pixel pair PP in the unit period T5 of the display panel controlled by the gate lines GL1~GL[5]. Please refer to the unit period T5 and 10F in Figure 9A at the same time. At this time, the level of the gate control signal is GL[1]=GL[4]=GL[5]=L, and GL[2]=GL[3]=L. It can be seen from FIG. 9A that the unit period T5 corresponds to the first data update period Tup1 of the gate line GL[2] and the precharge period Tpc of the gate line GL[3] at the same time.

At the same time, the common pixel pair JPP connected to the gate line GL[2] (ie, the pixel pair PP(1,2), PP(3,2)) is directly charged. On the other hand, the isolated pixel pair IPP (ie, the pixel pair PP(2,2), PP(4,2)) connected to the gate line GL[2] does not receive the high level GL[2]. Furthermore, the shared pixel pair JPP (ie, PP(2,3), PP(4,3)) connected to the gate line GL[3] is directly charged, and the one connected to the gate line GL[2] The isolated pixel pair IPP (ie, the pixel pair PP(2,2), PP(4,2)) is indirectly charged. According to the concept of the present invention, the data voltage transmitted by the data line DL at this time corresponds to the display data of the pixel pair PP(2,2), PP(4,2), and the pixel pair PP(2,3), PP(4, 3) Although it is directly charged during this unit period, the data voltage used to charge the pixel pair PP(2,3) and PP(4,3) does not correspond to it.

According to this, in the unit period T5, the shared pixel pair JPP connected to the gate line GL[2] (ie, the pixel pair PP(1,2), PP(3,2)) transitions from the original state A to the state B. At the same time, the isolated pixel pair IPP (ie, the pixel pair PP(2,2), PP(4,2)) connected to the gate line GL[2] receives the corresponding data voltage and is charged, so State C. In addition, the shared pixel pair JPP (ie, the pixel pair PP(2,3), PP(4,3)) connected to the gate line GL[3] is charged with a data voltage that does not belong to itself, so it is in state B.

Because the pixel pair PP(2,2) and PP(4,2) have been charged by the corresponding data voltage during the unit period T5, after the unit period T5 ends (ie, time t6), the pixel pair PP(2,2) 、PP(4,2), you can start to display pixel data normally.

Moreover, it can be seen from the circled location of the dashed curve that all pixel pairs connected to the gate line GL[2] and the common pixel pair JPP connected to the gate line GL[3] are all charged. Among the charged pixel pairs PP, those belonging to the shared pixel pair JPP are directly charged and are in the state B, and those belonging to the isolated pixel pair IPP are indirectly charged and are in the state C.

Figure 10G shows the state of the pixel pair PP in the unit period T6 of the display panel controlled by the gate lines GL1~GL[5]. Please refer to the unit period T6 and 10G in Figure 9A at the same time. At this time, the level of the gate control signal is GL[1]=GL[3]=GL[4]=GL[5]=L, and GL[2]=H. It can be seen from FIG. 9A that the unit period T6 corresponds to the second data update period Tup2 of the gate line GL[2] and the waiting period Twt of the gate line GL[3] at the same time.

In the unit period T6, the isolated pixel pair IPP (ie, the pixel pair PP(2,2), PP(4,2)) connected to the gate line GL[2] has received the corresponding data voltage before the time t6 And complete charging, the pixel pair PP(2,2), PP(4,2) transition from state C to state D.

At this time, the common pixel pair JPP connected to the gate line GL[2] (that is, the pixel pair PP(1,2), PP(3,2)) is directly charged in the unit period T6. Moreover, the pixel pairs PP(1,2) and PP(3,2) are charged with the data voltage directly corresponding to them. Therefore, the pixel pair PP(1,2), PP(3,2) is in the state C during the unit period T6. After the unit period T6 ends (ie, time t7), the common pixel pair JPP connected to the gate line GL[2] can start to display pixel data normally.

It can be seen from the circled location of the dashed curve that the common pixel pair JPP connected to the gate line GL[2] is charged and in state C, and the common pixel pair JPP connected to the gate line GL[3] Not being charged and in state A. Because the pixel pair PP(1,2), PP(3,2) has been charged by the corresponding data voltage during the unit period T6, after the unit period T6 ends (that is, at time t7), the pixel pair PP(1, 2), PP(3,2) displays pixel data normally. In other words, starting from the time point t7, the pixel pair PP in the second row normally displays pixel data.

Figures 10H~10N show the state of the pixel pair PP in the unit period T7~T13 for the display panel controlled by the gate lines GL1~GL[5]. Regarding the operation of the 10th to 10N pictures, the foregoing description can be analogized without detailed description.

Continuing from the above, the isolated pixel pair IPP and the common pixel pair JPP connected to the gate line GL[1] start to display pixel data from time t4 and t5 respectively; the isolated pixel pair IPP connected to the gate line GL[2] and The shared pixel pair JPP starts to display pixel data normally from time t6 and t7; the isolated pixel pair IPP connected to the gate line GL[3] and the shared pixel pair JPP start to display pixels normally from time t8 and t9 respectively Data; the isolated pixel pair IPP connected to the gate line GL[4] and the common pixel pair JPP start to display pixel data normally from time points t10 and t11, respectively; and, the isolated pixel pair connected to the gate line GL[5] The IPP and the shared pixel pair JPP start to display pixel data normally after the time points t12 and t13, respectively.

In addition, without considering the boundary between the first column and the Nth column, it can be seen that in the odd numbered unit period T3, T5, T7, T9, there is a total of M*3/2. Each pixel pair PP is charged (equivalent to M*3 pixels being charged); and, in even-numbered unit periods T2, T4, T6, T8, a total of M/2 pixel pairs PP are charged (equivalent to M The pixels are charged).

According to Figure 7, among the pixel pairs PP connected to the gate line GL[n] (n is an odd number), the pixel pairs located in odd rows are isolated pixel pairs IPP; the pixel pairs PP located in even rows are common pixel pairs. JPP. In the pixel pair PP connected to the gate line GL[n] (n is an even number), the pixel pair PP in the odd-numbered row is the common pixel pair JPP; the pixel pair PP in the even-numbered row is the isolated pixel pair IPP. Among them, regarding the state change of the common connected pixel pair JPP and the isolated pixel pair IPP, please refer to the table in Figure 8. In addition, the state changes of the isolated pixel pair IPP and the shared pixel pair JPP described in the display panel in Figure 7 and Figure 8 are combined with the waveforms in Figure 9A and the gate control signals shown in Figures 10A to 10H. The waveform changes of GL[1]~GL[3] and the change process of pixels to PP can be further summarized in the table in Figure 11.

Please refer to Figure 11, which is based on Figures 10A to 10H, a schematic diagram of the level changes of the integrated gate control signals GL[1], GL[2], GL[3] relative to the state of the pixel pair PP. This table lists parameters such as the gate line GL connected to the pixel pair PP, the position of the pixel pair PP in the display panel, and each unit period. It can be seen that the state changes and comparisons between the pixel pairs PP in different columns are shown. For ease of reference, Figure 11 uses a bold frame to indicate the pixel pair PP that received its corresponding data voltage during the unit period (ie, the pixel pair PP in state C), and a bold dashed line indicates that the isolated pixel pair IPP passes through The interconnection line IL and the common pixel indirectly charge the JPP.

It can be seen from the bold frame in Figure 11 that since the unit period T3, each unit period has a row of one of the pixel pairs PP that can receive the correct data voltage. Among them, the pixel pair PP that receives the correct data voltage during the unit period T3, T5, and T7 is an isolated pixel pair IPP, which will be provided by the pixel pair PP across the columns. The pixel pair PP that receives the correct data voltage during the unit period T2, T4, and T6 is the common pixel pair JPP that can directly receive the correct data voltage.

Figure 11 can represent the state change of the pixel pair PP connected to the gate lines GL[n-1], GL[n], GL[n+1] in the case of n=2. The relationship summarized from this represents not only the case where n is an even number in Figure 4, but also the case where n is an odd number in Figure 6A. Furthermore, from the perspective of the type of the pixel pair PP, the behavior of the pixel pair PP on the display panel can be roughly summarized as follows for the different periods of the gate control signal GL[n]. As mentioned above, a change period of the gate control signal GL[n] includes the precharge period Tpc, the waiting period Twt, the first data update period Tup1, and the second data update period Tup2.

During the precharge period Tpc of the gate line GL[n], the gate control signal GL[n] is at a high level. At this time, the isolated pixel pair IPP located in the nth column but not connected to the gate line GL[n] is not charged. On the other hand, the common pixel pair also located in the nth column and also connected to the gate control signal GL[n] Although the JPP is directly charged, the data voltage represents the data voltage of the isolated pixel in the (n-1)th column and connected to the gate line GL[n-1] to the IPP. That is, during the precharge period Tpc of the gate line GL[n], the common pixel pair JPP connected to the gate line GL[n] is the isolated pixel pair IPP connected to the gate line G[n-1] The data voltage is precharged for the first time.

Secondly, during the waiting period Twt of the gate line GL[n], the pixel pairs (including the isolated pixel pair IPP and the shared pixel pair JPP) located in the nth column and connected to the gate line GL[n] are not charged. At this time, the shared pixel pair JPP located in the (n-1)th column and connected to the gate line GL[n-1] column is charged.

Next, during the first data update period Tup1 of the gate line GL[n], the isolated pixel pair IPP located in the nth column and connected to the gate line GL[n] will pass through the (n+1)th column and The shared pixel pair JPP connected to the gate line GL[n+1] is indirectly charged. At the same time, the shared pixel pair JPP located in the nth column and connected to the gate line GL[n] will also receive the data voltage on the DL because the gate control signal GL[n] is at a high level. However, at this time, the data line DL transmits the data voltage corresponding to the isolated pixel pair IPP located in the nth row and connected to the gate line GL[n]. Therefore, the common-connected pixel located in the nth column and connected to the gate line GL[n] precharges the JPP for the second time during the first data update period Tup1.

Finally, during the second data update period Tup2 of the gate line GL[n], the shared pixel pair JPP located in the nth row and connected to the gate line GL[n] directly receives the data voltage corresponding to the pixel pair JPP from the data line DL. As mentioned above, the common-connected pixel on the nth column and connected to the gate line GL[n] has previously precharged the JPP for the first time during the precharge period Tpc, and has also been precharged during the first data update period Tup1. Precharge for the second time. Accordingly, the shared pixel pair JPP located in the nth column and connected to the gate line GL[n] can be charged to the level corresponding to the pixel data faster.

As mentioned above, the display panel according to the embodiment of the present invention can be electrically connected to the gate driving circuit through n GLs and electrically connected to the source driving circuit through (M+1) data lines DL. Among them, the source drive circuit outputs (M+1) pieces according to the control of the timing controller Data voltage, and the gate driving circuit symmetrically arranges a plurality of shift registers SR on both sides of the display panel, and outputs N gate control signals GL following the control of the timing controller. On the display panel, the pixel pairs PP connected to the two adjacent gate lines GL are related to each other. For example, the isolated pixels connected to the gate line GL[2] control IPP and the common pixels connected to the gate line GL[3] control JPP; on the other hand, it is related to the gate line GL[3] The control of IPP by the connected isolated pixels is related to the control of JPP by the common pixels connected to the gate line GL[4].

Assume that the two shift registers SR (located on both sides of the display panel) connected to the gate line GL[n] synchronously generate the gate control signal GL[n], which is connected to the gate line GL[n+1] The two connected shift registers SR (located on both sides of the display panel) synchronously generate gate control signals GL[n+1]. According to the foregoing, there are a total of M/2 common pixel pairs JPP and M/2 isolated pixel IPP pairs electrically connected to the gate line GL(n+1); and, a total of M/2 common pixel pairs JPP and M/ The two isolated pixel pairs IPP are electrically connected to the gate line GL(n+1). Among them, the M/2 isolated pixel pairs IPP connected to the gate line GL[n] are alternately arranged along the column direction with the M/2 common pixel pairs JPP connected to the gate line GL[n+1]; and The M/2 common pixel pairs JPP connected to the gate line GL[n] are alternately arranged with the isolated pixel pairs IPP connected to the gate line GL[n+1].

In addition, between the M/2 isolated pixel pairs IPP connected to the gate line GL[n] and the M/2 common pixel pairs JPP connected to the gate line GL[n+1], a total of M interconnection wires IL. Through the interconnection line IL, the M isolated pixels IP connected to the gate line GL[n] are electrically connected to the common pixel JP connected to the gate line GL[n+1].

In the embodiment of the present invention, symmetrical shift registers SR are arranged on the left and right sides of the display panel. The gate control signal GL can be simultaneously transmitted to the display panel through the two symmetrical shift registers SR, and the display panel has a pre-charging function, so the aforementioned embodiment has good driving capability. Furthermore, since each shift register SR corresponds to two columns of pixels P, it represents the shift register SR The usable length (in the row direction) is longer, and the required width (in the column direction) can be reduced. Therefore, the foregoing embodiment also meets the requirement of a narrow frame.

In summary, the display panel provided by the embodiment of the present invention has good driving capability, and the gate driving circuit requires a small width, which is suitable for providing a narrow frame. Therefore, the display panel of the present invention can meet the requirements of both driving capability and small area. Take the application of virtual reality (VR for short) as an example. Pixels Per Inch (PPI for short) needs to reach 800~2000, and due to the high resolution of the VR device and the high frequency of screen switching Characteristics. For VR applications, the display panel needs strong driving capability. Furthermore, for wearable applications of VR devices, there is an urgent need to use a narrow frame design. Therefore, the display panel of the present invention can be used in VR devices or other applications that need to take into account the driving ability and reduce the frame range.

The foregoing description is mainly based on the level change of the gate control signal GL. On the other hand, the data voltage transmitted by the data line DL can be different with the display and planning of the pixel P. Since the present invention changes the connection mode of pixels on the display panel, the main influence is the control of the gate line GL. The data voltage transmitted by the data line DL can be adjusted by the timing controller according to the different arrangement of the pixels P. Table 4 is used to illustrate the correspondence between the data voltages transmitted by the data lines DL[1] ˜DL[5] during the unit period T3 ˜T10 and the pixel P in the foregoing embodiment.

In addition, for ease of description, it can be seen from the foregoing figures that each pixel pair PP includes two pixels P. Here, of the two pixels P included in each pixel pair PP, the one located above is defined as the first pixel P1 of the pixel pair; and, among the two pixels P included in each pixel pair PP, it is located The lower one is defined as the second pixel P2 of the pixel pair PP.

Here, only the unit period T3 in Table 4 is taken as an example to illustrate how the data line DL transmits the data voltage. In the unit period T3, the data line DL[1] transmits the data voltage to the first pixel P1 of the pixel pair PP(1,1); the data line DL[2] transmits the data voltage to the pixel pair PP(1,1) The data line DL[3] transmits the data voltage to the first pixel P1 of the pixel pair PP(3,1); the data line DL[4] transmits the data voltage to the pixel pair PP(3, 1) The second pixel P2; the data line DL[5] does not transmit a data voltage. The description of how the data line DL transmits the data voltage during other unit periods will not be detailed here.

Furthermore, in order to save the number of pins of the timing controller, the timing controller can also cooperate with the demultiplexing signal generated by the demultiplexer to generate the data voltage. The following is an example of controlling the voltage change of the data line DL in response to the demultiplexing signal.

Please refer to FIG. 12, which is a schematic diagram of a display panel according to an embodiment of the present invention further equipped with a demultiplexer control. In this figure, it is assumed that the source drive circuit 50 includes a source Drive 51, 52. Among them, the source driver 51 connected to the data lines DL[1]~DL[6] includes switches a1, a2, b1, b2, c1, c2; the source connected to the data lines DL[7]~DL[12] The driver 52 includes switches a3, a4, b3, b4, c3, and c4. Switches a1, a2, a3, and a4 are turned on by the switch control signal SWa; switches b1, b2, b3, and b4 are turned on by the switch control signal SWb; switches c1, c2, c3, and c4 are turned on by the switch control signal SWc . The switch control signals SWa, SWb, and SWc are demultiplexed signals generated by the timing controller in conjunction with a demultiplexer, and the switch control signals SWa, SWb, and SWc take turns at high levels. Since the control modes of the source driver 51 and the source driver 52 are similar to each other, the following only takes the source driver as an example to describe the related control signals and operation modes.

Please refer to FIG. 13, which is a waveform diagram of signals related to the control of the first source driver in the display panel shown in FIG. 12. The waveforms of this figure are gate lines GL[1], GL[2], GL[3] from top to bottom; switch control signals SWa, SWb, SWc; dynamic data lines IC[1], IC[2 ] The voltage of the transmitted data; and, the voltage of the data transmitted by the data lines DL[1], DL[2], DL[3], DL[4], DL[5], DL[6]. Since the changes of the gate lines GL[1], GL[2], and GL[3] are the same as those described in Figures 9A and 9B, they will not be described again.

For ease of description, Figure 13 defines six unit periods TM1, TM2, TM3, TM4, TM5, and TM6. Among them, the unit periods TM3, TM4, TM5, and TM6 each include five sub-unit periods. Among the five sub-unit periods, the first and last sub-unit periods are used to prevent misoperation, and are not specifically described here. In addition, the second subunit period corresponds to the period during which the switch control signal SWa is at a high level, the third subunit period corresponds to the period during which the switch control signal SWb is at a high level, and the fourth subunit period corresponds to the period during which the switch control signal SWc is at a high level. Period. For example, in the unit period TM3, the period during which the switch control signal SWa is at a high level is defined as the sub-unit period TM3a, and the period during which the switch control signal SWb is at a high level is defined as the sub-unit period. The unit period TM3b and the period during which the switch control signal SWc is at a high level are defined as the sub-unit period TM3c, and the labels of the remaining sub-unit periods can be derived by analogy and will not be described in detail.

The dynamic data lines IC[1] and ÍC[2] receive the data voltage to be transmitted to the display panel from the timing controller during the unit period TM3, TM4, TM5, and TM6. As shown in Figure 13, during each sub-unit period, the voltages of the dynamic data lines IC[1] and ÍC[2] also change alternately according to the period when the switch control signals SWa, SWb, and SWc are at high levels. As the switch control signals SWa, SWb, and SWc are turned on in turn, the dynamic data line IC[1] transmits the data voltage to one of the data lines DL[1], DL[3], and DL[5] in turn. As the switch control signals SWa, SWb, and SWc are turned on in turn, the dynamic data line IC[2] transmits the data voltage to one of the data lines DL[2], DL[4], and DL[6] in turn.

Therefore, in the second subsection (TM3a) of the unit period TM3, the switch a1 will be turned on as the switch control signal SWa is at a high level. Accordingly, the dynamic data line IC[1] transmits the data voltage to the data line DL[1] in TM3a. The other waveforms also have a similar relationship, which will not be detailed here.

In the following, when the demultiplexing architecture is adopted, in the unit periods TM3, TM4, TM5, and TM6, the switch control signals SWa, SWb, SWc are used to determine the data transmission voltage of the data lines DL[1]~DL[6]. The switching method allows the pixels on the display panel to receive the data voltage normally. For ease of description, in the following figures, thicker lines represent the data line DL receiving the data voltage from the dynamic data lines IC[1] and IC[2], and the gate line GL with a high level.

Since the gate control signals GL[1]~GL[3] in TM3 in Figure 13 are similar to the gate control signals GL[1]~GL[3] in the unit period T3 in Figure 9A, The pixel pair corresponding to the gate state in the unit period T3 and the corresponding relationship can be directly applied to the unit period TM3. In the same way, the aforementioned state of the pixel pairs in the unit periods T4, T5, and T6 can be directly applied to the unit periods TM4, TM5, and TM6.

Please refer to Figures 14A, 14B, and 14C, which are the changes in the TM3 of the pixels associated with the first source driver in the display panel during the unit period. Among them, Figure 14A corresponds to the sub-unit Period TM3a; Figure 14B corresponds to the sub-unit period TM3b; Figure 14C corresponds to the sub-unit period TM3c. At this time, the common pixel JP connected to the gate line GL[1] and the common pixel JP connected to the gate line GL[2] both directly receive the data voltage from the data line DL. In addition, the isolated pixel IP connected to the gate line GL[1] will also indirectly receive the data voltage from the data line DL via the common pixel JP connected to the gate line GL[2]. At this time, as the data line DL that transmits the data voltage is different, the common pixels connected to the gate lines GL[1] and GL[2] and the isolated pixels IP connected to the gate line GL[1] will also take turns The data voltage is received. Please refer to Figures 14A, 14B, 14C and Table 5 together.

In Figure 14A, data lines DL[1] and DL[2] receive data voltages from dynamic data lines IC[1] and IC[2], respectively. During the sub-unit period TM3a, the common pixel P(2,1) connected to the gate line GL[1] will directly use the data voltage transmitted by DL[2] for precharging; the one connected to the gate line GL[1] The isolated pixel P(1,1) indirectly receives the data voltage transmitted by the data line DL[1] through the common pixel P(1,3) connected to the gate line GL[2]; it is connected to the gate line GL[1] The isolated pixels P(1,2) indirectly receive the data voltage transmitted by the data line DL[2] through the common pixel P(1,4) connected to the gate line GL[2]; and, with the gate line GL[ 2] The connected common pixels P(1,3) and P(1,4) directly use the data voltage transmitted by the data lines DL[1] and DL[2] for precharging. In short, in the sub-unit period TM3a, although a total of five pixels are charged in the sub-unit period TM3a, the pixels P(2,1), P(1,3), and P(1,4) are only For precharge, the voltage value of the data voltage must still correspond to the isolated pixel. Therefore, in the sub-unit period TM3a, the data voltage transmitted from the dynamic data line IC[1] to the data line DL[1] corresponds to the isolated pixel P(1,1), which is transmitted to the data by the dynamic data line IC[2] The data voltage of the line DL[2] corresponds to the isolated pixel P(1,2).

In Figure 14B, data lines DL[3] and DL[4] receive data voltages from dynamic data lines IC[1] and IC[2], respectively. During the sub-unit period TM3b, the common pixels P(2,2) and P(4,1) connected to the gate line GL[1] directly use the data voltages transmitted by the data lines DL[3] and DL[4], respectively Pre-charge; the isolated pixel P(3,1) connected to the gate line GL[1] through the common connection image connected to the gate line GL[2] The pixel P(3,3) receives the data voltage transmitted by the data line DL[3]; the isolated pixel P(3,2) receives the data line through the common pixel P(3,4) connected to the gate line GL[2] The data voltage transmitted by DL[4]; and the common pixels P(3,3) and P(3,4) connected to the gate line GL[2] directly use the data lines DL[3], DL[4] The transmitted data voltage is precharged. In short, although a total of 6 pixels are charged during the sub-unit period TM3b, the pixels P(2,2), P(3,3), P(3,4), P(4,1) are only For precharging, the voltage value of the data voltage must still correspond to the isolated pixel IP. Therefore, in the sub-unit period TM3b, the data voltage transmitted from the dynamic data line IC[1] to the data line DL[3] corresponds to the isolated pixel P(3,1), which is transmitted to the data by the dynamic data line IC[2] The data voltage of the line DL[4] corresponds to the isolated pixel P(3, 2).

In Figure 14C, data lines DL[5] and DL[6] receive data voltages from dynamic data lines IC[1] and IC[2], respectively. During the sub-unit period TM3c, the common pixels P(4,2) and P(6,1) connected to the gate line GL[1] directly use the data voltages transmitted by the data lines DL[5] and DL[6]. Precharge; the isolated pixel P(5,1) connected to the gate line GL[1] receives the data line DL[5] through the common pixel P(5,3) connected to the gate line GL[2] Data voltage; the isolated pixel P(5,2) receives the data voltage transmitted by the data line DL[6] through the common pixel P(5,4) connected to the gate line GL[2]; and the gate line GL[2 ] The connected common pixels P(5,3) and P(5,4) directly use the data voltage transmitted by the data lines DL[5] and DL[6] for precharging. In short, although there are a total of 6 pixels P that will be charged during the sub-unit period TM5b, the pixels P(4,2), P(5,3), P(5,4), P(6,1) Only pre-charging is performed, and the value of the data voltage must still correspond to the isolated pixel IP. Therefore, in the sub-unit period TM3c, the data voltage transmitted from the dynamic data line IC[1] to the data line DL[5] corresponds to the isolated pixel P(5,1), and the dynamic data line IC[2] is transmitted to the data line DL The data voltage of [6] corresponds to the isolated pixel P(5, 2).

In the unit period TM3, the common pixel pairs P(2,1), P(2,2), P(4,1), P(4,2), P(6) connected to the gate line GL[1] ,1) are in state B; isolated pixels P(1,1), P(1,2), P(3,1), P(3,2), P() connected to the gate line GL[1] 5,1), P(5,2) are in state C; the common pixels P(1,3), P(1,4), P(3,3), P(3,4), P(5,3), P(5,4) are in state B. In Figures 14A, 14B, and 14C, the common pixel JP in the state B is selected with a thin dashed circle, and the isolated pixel IP in the state C is selected with a thick dashed circle. Accordingly, the isolated pixels P(1,1), P(1,2), P(3,1), P(3,2), P(5,1), P(5,2) can display pixel data normally after the unit period TM3 ends.

Please refer to FIGS. 15A, 15B, and 15C, which are the changes of the pixel P related to the first source driver in the unit period TM4 in the display panel. Among them, Figure 15A corresponds to the sub-unit period TM4a; Figure 15B corresponds to the sub-unit period TM4b; and Figure 15C corresponds to the sub-unit period TM4c. At this time, the common pixel JP connected to the gate line GL[1] will directly receive the data voltage from the data line DL. As the data line DL for transmitting the data voltage is different, the common pixels connected to the gate line GL[1] will receive the data voltage in turn. Please refer to Figures 15A, 15B, 15C and Table 6 together.

In Figure 15A, the data lines DL[1] and DL[2] receive data voltages from the dynamic data lines IC[1] and IC[2] during the sub-unit period TM4a, respectively. In the sub-unit period TM4a, the common pixel P(2,1) connected to the gate line GL[1] is directly charged with the data voltage transmitted by the data line DL[2]. Therefore, in the sub-unit period TM4a, the data voltage transmitted from the dynamic data line IC[1] to the data line DL[1] does not correspond to any pixel P (or, the dynamic data line IC[1] suspends the data voltage transmission) , The data voltage sent from the dynamic data line IC[2] to the data line DL[2] corresponds to the pixel P(2,1).

In FIG. 15B, the data lines DL[3] and DL[4] receive data voltages from the dynamic data lines IC[1] and IC[2] during the sub-unit period TM3b, respectively. During the sub-unit period TM4b, the common pixels P(2,2) and P(4,1) connected to the gate line GL[1] directly use the data voltages transmitted by the data lines DL[3] and DL[4], respectively Recharge. Therefore, in the sub-unit period TM4b, the data voltage transmitted from the dynamic data line IC[1] to the data line DL[3] corresponds to the pixel P(2,2), and the dynamic data line IC[2] is transmitted to the data line DL[ The data voltage of 4] corresponds to the pixel P(4,1).

In Figure 15C, the data lines DL[5] and DL[6] receive data voltages from the dynamic data lines IC[1] and IC[2] during the sub-unit period TM3c, respectively. During the sub-unit period TM4c, and the gate line The common pixels P(4,2) and P(6,1) connected to GL[1] are directly charged by the data voltage transmitted by the data lines DL[5] and DL[6]. Therefore, in the sub-unit period TM4c, the data voltage transmitted from the dynamic data line IC[1] to the data line DL[5] corresponds to the pixel P(4,2), and the dynamic data line IC[2] is transmitted to the data line DL[ The data voltage of 6] corresponds to the pixel P(6,1).

In the unit period TM4, the common pixel pairs P(2,1), P(2,2), P(4,1), P(4,2), P(6) connected to the gate line GL[1] ,1) are in state C. Accordingly, the common pixel pairs P(2,1), P(2,2), P(4,1), P(4,2), P(6,1) connected to the gate line GL[1] ) After the unit period TM4 ends, the pixel data can be displayed normally.

Please refer to Figures 16A, 16B, and 16C, which are the changes of TM5 in the unit period of the pixels related to the first source driver in the display panel. Among them, Figure 16A corresponds to the sub-unit period TM5a; Figure 16B corresponds to the sub-unit period TM5b; Figure 16C corresponds to the sub-unit period TM5c. At this time, the common pixel JP connected to the gate line GL[2] and the common pixel JP connected to the gate line GL[3] both directly receive the data voltage from the data line DL. In addition, the isolated pixel IP connected to the gate line GL[2] will also indirectly receive the data voltage from the data line DL via the common pixel JP connected to the gate line GL[3]. At this time, as the data line DL that transmits the data voltage is different, the common pixel connected to the gate line GL[2] and the gate line GL[3] and the isolated pixel IP connected to the gate line GL[2], The data voltage will also be received in turn. Please refer to Figures 16A, 16B, 16C and Table 7 together.

In FIG. 16A, the data lines DL[1] and DL[2] receive data voltages from the dynamic data lines IC[1] and IC[2] during the sub-unit period TM5a, respectively. During the sub-unit period TM5a, the common pixels P(1,3) and P(1,4) connected to the gate line GL[2] directly use the data voltages transmitted by the data lines DL[1] and DL[2]. Precharge; the isolated pixel P(2,3) connected to the gate line GL[2] indirectly receives the data sent by DL[2] through the common pixel P(2,5) connected to the gate line GL[3] Voltage; with gate line The common pixel P(2,5) connected to GL[3] directly uses the data voltage transmitted by the data line DL[2] for precharging. In short, although there are a total of five pixels P charged during the sub-unit period TM5b, the common pixels P(1,3), P(1,4), and P(2,6) are only precharged. The data voltage The voltage value of must still correspond to the isolated pixel IP. Therefore, in the sub-unit period TM5a, the data voltage transmitted to the data line DL[1] via the dynamic data line IC[1] corresponds to the isolated pixel P(1,1), and is transmitted to the data via the dynamic data line IC[2] The data voltage of the line DL[2] corresponds to the isolated pixel P(1,2).

In Figure 16B, data lines DL[3] and DL[4] receive data voltages from dynamic data lines IC[1] and IC[2], respectively. During the sub-unit period TM5b, the common pixels P(3,3) and P(3,4) connected to the gate line GL[2] directly use the data voltages transmitted by the data lines DL[3] and DL[4], respectively Pre-charge; the isolated pixel P(2,4) connected to the gate line GL[2] receives the data line DL[3] transmission through the common pixel P(2,6) connected to the gate line GL[3] The data voltage; the isolated pixel P(4,3) connected to the gate line GL[2] indirectly receives the data line DL[4] through the common pixel P(4,5) connected to the gate line GL[3] ] The voltage of the transmitted data. In short, although there are a total of five pixels P that are charged during the sub-unit period TM5b, the pixels (3,3), P(3,4), and P(2,6) that are connected in common are only precharged, and the voltage of the data voltage The value must still correspond to the isolated pixel IP. Therefore, in the sub-unit period TM5b, the data voltage transmitted to the data line DL[3] via the dynamic data line IC[1] corresponds to the pixel P(3,1), and is transmitted to the data line via the dynamic data line IC[2] The data voltage of DL[4] corresponds to the pixel P(3, 2).

In Figure 16C, data lines DL[5] and DL[6] receive data voltages from dynamic data lines IC[1] and IC[2], respectively. During the sub-unit period TM5c, the common pixels P(5,3) and P(5,4) connected to the gate line GL[1] directly use the data voltages transmitted by the data lines DL[5] and DL[6]. Precharge; the isolated pixel P(4,4) connected to the gate line GL[2] receives the data line DL[5] through the common pixel P(4,6) connected to the gate line GL[3] Data voltage; the isolated pixel P(6,3) connected to the gate line GL[2] receives the data line DL[6] through the common pixel P(6,5) connected to the gate line GL[3] Data voltage. In short, although a total of four pixels are charged during the sub-unit period TM5c, a total of The pixels P(5,3) and P(5,4) are only precharged, and the voltage value of the data voltage must still correspond to the isolated pixel. Therefore, in the sub-unit period TM5c, the data voltage transmitted from the dynamic data line IC[1] to the data line DL[5] corresponds to the pixel P(4,4), and is transmitted from the dynamic data line IC[2] to the data line The data voltage of DL[6] corresponds to the pixel P(6,3).

In the unit period TM5, the common pixel pairs P(2,1), P(2,2), P(4,1), P(4,2), P(6) connected to the gate line GL[1] ,1) are in state B; isolated pixels P(1,1), P(1,2), P(3,1), P(3,2), P() connected to the gate line GL[1] 5,1), P(5,2) are in state C; the common pixels P(1,3), P(1,4), P(3,3), P(3,4), P(5,3), P(5,4) are all in state B. In Figures 16A, 16B, and 16C, the common pixel JP in the state B is selected with a thin dashed circle, and the isolated pixel IP in the state C is selected with a thick dashed circle. Accordingly, the isolated pixels P(2,3), P(4,3), P(2,4), P(6,3), P(4,4) connected to the gate line GL[2] After the unit period TM5 ends, the pixel data can be displayed normally.

Please refer to Figures 17A, 17B, and 17C, which are the changes of TM6 in the unit period of the pixels related to the first source driver in the display panel. Among them, Figure 17A corresponds to the sub-unit period TM6a; Figure 17B corresponds to the sub-unit period TM6b; Figure 17C corresponds to the sub-unit period TM6c. Please refer to Figures 17A, 17B, 17C and Table 8 together.

In Figure 17A, the data lines DL[1] and DL[2] receive data voltages from the dynamic data lines IC[1] and IC[2] during the sub-unit period TM6a, respectively. During the sub-unit period TM6a, the common pixel P(1,3) connected to the gate line GL[1] is directly charged with the data voltage transmitted by the data line DL[2]; the common pixel connected to the gate line GL[2] The connected pixel P (1, 4) is directly charged with the data voltage transmitted by the data line DL[2]. Therefore, in the sub-unit period TM6b, the data voltage transmitted from the dynamic data line IC[1] to the data line DL[3] corresponds to the common pixel P(1,3), which is transmitted from the dynamic data line IC[2] to The data voltage of the data line DL[4] corresponds to the commonly connected pixel P(1, 4).

In FIG. 17B, the data lines DL[3] and DL[4] receive data voltages from the dynamic data lines IC[1] and IC[2] during the sub-unit period TM6b, respectively. During the sub-unit period TM6b, the common pixels P(3,3) and P(3,4) connected to the gate line GL[1] are respectively charged by the data voltage transmitted by the data lines DL[3] and DL[4] . Therefore, in the sub-unit period TM6b, the data voltage transmitted from the dynamic data line IC[1] to the data line DL[3] corresponds to the common pixel P(3,3), which is transmitted from the dynamic data line IC[2] to The data voltage of the data line DL[4] corresponds to the commonly connected pixel P(3, 4).

In Figure 17C, the data lines DL[5] and DL[6] receive data voltages from the dynamic data line IC[1] and the dynamic data line IC[2] during the sub-unit period TM6c. During the sub-unit period TM6c, the common pixels P(5,3) and P(5,4) connected to the gate line GL[2] are directly charged with the data voltage transmitted by the data lines DL[5] and DL[6] . Therefore, in the sub-unit period TM6c, the data voltage transmitted from the dynamic data line IC[1] to the data line DL[5] corresponds to the common pixel P(5,3), which is transmitted from the dynamic data line IC[2] to The data voltage of the data line DL[6] corresponds to the common connection pixel P(5, 4).

In the unit period TM6, the common pixels P(1,3), P(1,4), P(3,3), P(3,4), P(5, 3), P(5,4) are in state C. Accordingly, the common pixels P(1,3), P(1,4), P(3,3), P(3,4), P(5,3) connected to the gate line GL[2] , P(5,4) After the unit period TM6 ends, the pixel data can be displayed normally.

The foregoing embodiment illustrates that this solution can achieve the effect of improving the driving capability and reducing the frame width by connecting the connection of the shared pixel JPP and the isolated pixel IPP and the bidirectional driving method. In addition, the present invention can also be used with a demultiplexer to reduce the wiring required by the timing controller to control the source drive circuit. It should also be noted that the design of the present invention is independent of the color corresponding to the pixel P. In other words, the color corresponding to the liquid crystal capacitor Clc contained in the isolated pixel IP and the common pixel JP does not affect the design of the connection between the common pixel JP and the isolated pixel IP in this case.

On the display panel, the color of the filter layer can be arranged in different ways based on different considerations. The color arrangement of the filter layer that two pixels P may correspond to are listed below. For convenience Note that the vertical stripe represents the liquid crystal capacitor Clc in the pixel P corresponding to the red R filter layer: the horizontal stripe represents the liquid crystal capacitor Clc in the pixel P corresponds to the blue B filter layer: and the pairs from top right to bottom left The angular stripes represent that the liquid crystal capacitor Clc in the pixel P corresponds to the green G filter layer.

Next, the corresponding relationship between the pixel P on the display panel and the color setting will be described. In Figures 18 and 19, the pixel unit PU(1,1) corresponds to the pixels P(1,1), P(2,1), P(3,1); the pixel unit PU(1,2) corresponds to Pixels P(1,2), P(2,2), P(3,2); pixel unit PU(2,1) corresponds to pixels P(4,1), P(5,1), P(6 ,1). The rest can be deduced by analogy. The arrangement of the color pixels P included in each pixel unit may be different (for example, FIG. 18) or the same (for example, FIG. 19).

In Figure 18, one type of pixel unit PU (for example, the pixel unit PU(1,1)) includes pixels P corresponding to the red R, green G, and blue B filter layers from left to right. The liquid crystal capacitor Clc, another type of pixel unit (for example, the pixel unit PU(1, 2)) includes the pixel P, from left to right includes the liquid crystal capacitor Clc corresponding to the green G, blue B, and red R filter layers.

In Figure 19, it is assumed that the pixels P in each pixel unit have the same color arrangement. That is, from left to right, the pixels P in each pixel unit include liquid crystal capacitors Clc corresponding to the green G filter layer, the red R filter layer, and the blue B filter layer. It should be noted that the correspondence between the pixel P and the color of the filter layer corresponding to the liquid crystal capacitor Clc shown in FIGS. 18 and 19 is only used as an example, and is not intended to limit the present invention.

As mentioned above, the present invention can change the connection mode of the display panel to meet the requirements of driving capability and narrow frame. In addition, the design of the present invention can also arbitrarily match the color arrangement of the filter layer corresponding to the pixel P. Therefore, the display panel designed based on the concept of the present invention provides a fairly flexible method to achieve the effect of improving the driving capability and reducing the area of the gate driving circuit. Further, if the current drive capability of the shift register is relatively strong, the present invention can further Reduce the number of shift registers to be used, for example, only set the shift register on the left side of the display panel, or set the shift register only on the right side of the display panel.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those who have ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

3: display device

30: timing controller

32: Source drive circuit

33: Gate drive circuit

33a, 33b: buffer

35: display panel

35a, 35b: pixels

351: Active Area

353: Inactive Area

SR[1], SR[2], SR[N-1], SR[N], SR[1'], SR[2'], SR[(N-1)'], SR[N']: Shift register

GL[1], GL[2], GL[N-1], GL[N]: gate line

Claims (17)

A display panel is electrically connected to a gate drive circuit, wherein the gate drive circuit includes a first shift register and a second shift register, wherein the first shift register generates a The nth gate control signal, and the second shift register generates an (n+1)th gate control signal, wherein the display panel includes: (M+1) data lines parallel to a row direction; An nth gate line, parallel to a column direction, receives the nth gate control signal; an (n+1)th gate line, parallel to the column direction, receives the (n+1)th gate Control signal; M common pixel pairs electrically connected to the data lines, including: M/2 first common pixel pairs electrically connected to the nth gate line; and M/2 second Commonly connected pixel pairs, electrically connected to the (n+1)th gate line; and M isolated pixel pairs, including: M/2 first isolated pixel pairs, electrically connected to the nth gate line, They are arranged alternately with the first common pixel pairs along the row direction; and, M/2 second isolated pixel pairs are electrically connected to the (n+1)th gate line along the row The direction is alternately arranged with the second common-connected pixel pairs, and M interconnecting wires are electrically connected between the first isolated pixel pairs and the second common-connected pixel pairs, wherein each first isolated pixel pair The position of the pixel pair along the column direction corresponds to the position of each second common pixel pair along the column direction, and each of the first isolated pixel pairs is electrically connected to each second common pixel pair, where M Is an even number and n is a positive integer. According to the display panel described in claim 1, wherein each of the first common pixel pairs includes a first first common pixel and a second first common pixel; each of the second common pixel pairs Each of the first isolated pixel pairs includes a first first isolated pixel and a second first isolated pixel; and each of the second The isolated pixel pair includes a first second isolated pixel and a second second isolated pixel. The display panel described in item 2 of the scope of patent application, wherein the nth gate line includes a first part and a second part that are parallel to each other, and the (n+1)th gate line It includes a first part and a second part that are parallel to each other, wherein the first part of the nth gate line is electrically connected to the first common-connected pixels and the first The first isolated pixel; the second part of the nth gate line is electrically connected to the second first common-connected pixels and the second first isolated pixels; the (n+1)th gate The first part of the electrode line is electrically connected to the first and second common pixels and the first and second isolated pixels; and, the second part of the (n+1)th gate line The second second co-connected pixels and the second second isolated pixels are electrically connected. The display panel described in item 2 of the scope of patent application, wherein Each of the first and second co-connected pixels is electrically connected to each of the first first isolated pixels through M/2 of the interconnection lines; and each of the second and second co-connected pixels is It is electrically connected to each of the second and first isolated pixels through the other M/2 of the interconnection lines. The display panel described in item 2 of the scope of patent application, wherein each of the first first co-connected pixels, each of the second first co-connected pixels, each of the first and second co-connected pixels, and each of the second and second co-connected pixels The two common connected pixels, each of the first first isolated pixel, each of the second first isolated pixel, each of the first second isolated pixel, and each of the second second isolated pixel all include a liquid crystal capacitor and a transistor And a storage capacitor, wherein the liquid crystal capacitor, the transistor and the storage capacitor are electrically connected to each other. The display panel according to claim 5, wherein the storage capacitor of the first first isolated pixel is through the transistor of the first and second co-connected pixels and the first isolated pixel The transistor is turned on and charged; the storage capacitor of the second first isolated pixel is charged through the conduction of the transistor of the second second common pixel and the transistor of the second first isolated pixel; the first The storage capacitor of the second co-connected pixel is charged through the transistor of the first and second co-connected pixels; and the storage capacitor of the second second co-connected pixel is charged through the second second co-connected pixel The transistor is turned on and charged. According to the display panel described in item 2 of the scope of patent application, each of the first common-connected pixels is electrically connected to an even number of the data lines; Each of the second second common-connected pixels is electrically connected to an even number of the data lines; each of the second first common-connected pixels is electrically connected to the third to the third of the data lines. An odd number of data lines in the (N+1)th data line; and, each of the first and second common-connected pixels is electrically connected to the first to the first (N-1) of the data lines. ) An odd number of data lines among the data lines, where N is a positive integer greater than or equal to 2, and n is less than or equal to N. For the display panel described in item 2 of the scope of patent application, each of the first common-connected pixels is electrically connected to the first to the (N-1) data line of the data lines Each of the second and first common-connected pixels is electrically connected to an even-numbered data line of the data line; each of the first and second common-connected pixels is electrically connected to the data line Each of the second and second co-connected pixels is electrically connected to an odd number of data lines from a third to a (N+1) data line among the data lines, where N Is a positive integer greater than or equal to 2, and n is less than or equal to N. For the display panel described in claim 1, wherein the first shift register and the second shift register are located on one side of the display panel, and the first shift register Are electrically connected to the first part and the second part of the nth gate line at the same time, and the second shift register is electrically connected to the (n+1)th gate line at the same time The first part and the second part. For the display panel described in item 1 of the scope of patent application, wherein the nth gate control signal and the (n+1) gate control signal both include a precharge period, a waiting period, a first update period and a The second update period, wherein the pre-charge period, the waiting period, the first update period and the second update period have the same length. The display panel according to claim 10, wherein the first update period of the nth gate control signal corresponds to the precharge period of the (n+1)th gate control signal; and The second update period of the nth gate control signal corresponds to the waiting period of the (n+1)th gate control signal. The display panel according to claim 10, wherein the nth gate control signal and the (n+1) gate control signal are in the precharge period, the first update period, and the second update period Both are a first level; and the nth gate control signal and the (n+1) gate control signal are at a second level during the waiting period. For the display panel described in item 10 of the scope of patent application, wherein the first common pixel pairs and the second common pixel pairs are in a first ready state, a second ready state, an update state, and a One of the display states; and, the first isolated pixel pairs and the second isolated pixel pairs are in one of the update state and the display state. The display panel described in item 13 of the scope of patent application, in which, During the precharge period of the (n+1)th gate control signal, the first isolated pixel pairs are in the update state, and the first common pixel pairs and the second common pixel pairs are In the second standby state; during the waiting period of the (n+1)th gate control signal, the first isolated pixel pairs are in the display state, and the first common pixel pairs are in the update state , And the second common-connected pixel pairs are in the first ready state; during the first update period of the (n+1)th gate control signal, the first isolated pixel pairs are in the same The connected pixel pairs are in the display state, the second common pixel pairs are in the second standby state, and the second isolated pixel pairs are in the update state; and at the (n+1)th gate During the second update period of the control signal, the first isolated pixel pairs, the first common pixel pairs, and the second isolated pixel pairs are in the display state, and the second common pixel pairs are in the display state The update status. For example, the display panel described in item 13 of the scope of patent application, wherein when the second common-connected pixel pairs are in the first ready state, they are disconnected from the data lines; when the second common-connected pixels When the pair is in the second standby state, it receives M first isolated data voltages corresponding to the first isolated pixel pairs through the data lines, and the first isolated pixel pairs pass through the second isolated pixel pairs. The common-connected pixel pairs receive the first isolated data voltages; and, when the second common-connected pixel pairs are in the update state, they receive the data corresponding to the second common-connected pixel pairs through the data lines M second common connection data voltage; When the second common-connected pixel pairs are in the display state, the brightness is determined according to the second common-connected data voltage. For example, in the display panel described in item 13 of the scope of patent application, when the first and isolated pixel pairs are in the update state, they receive the first isolated pixel pairs through the second common pixel pairs. M first isolated data voltages corresponding to the pixel pairs; and, when the first isolated pixel pairs are in the display state, the brightness is determined according to the first isolated data voltages. A display device includes: a source drive circuit that outputs (M+1) data voltages; a gate drive circuit that includes: a first shift register that generates an nth gate control signal; And a second shift register for generating an (n+1)th gate control signal; and a display panel, electrically connected to the source driving circuit and the gate driving circuit, including: (M+1) Data lines are electrically connected to the source driving circuit and parallel to the row direction, wherein each of the data lines receives each of the data voltages; an nth gate line is electrically connected to the first shift register Parallel to a row direction, which receives the nth gate control signal; an (n+1)th gate line, electrically connected to the second shift register and parallel to the row direction, which receives The (n+1)th gate control signal; M commonly connected pixel pairs, electrically connected to the data lines, include: M/2 first common pixel pairs are electrically connected to the nth gate line; and M/2 second common pixel pairs are electrically connected to the (n+1)th gate line; And M isolated pixel pairs, including: M/2 first isolated pixel pairs electrically connected to the nth gate line, which are alternately arranged with the first common pixel pairs along the column direction; and, M/2 isolated pixel pairs are electrically connected to the (n+1)th gate line, which are alternately arranged with the second common pixel pairs along the column direction, wherein each of the first isolated pixel pairs is The position in the column direction corresponds to the position of each second common pixel pair along the column direction, and each first isolated pixel pair is electrically connected to each second common pixel pair, where M is an even number and n is a positive integer.

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