TWI699581B - Pixel array substrate - Google Patents

Abstract

A pixel array substrate including a substrate, a first signal line, a first pixel, an insulation layer, an organic layer and a light shielding pattern is provided. The first pixel includes a first active device and a first pixel electrode electrically connected to each other. The first active device is electrically connected to the first signal line. The insulation layer has a first opening overlapped with the first signal line. The first signal line has a first surface defining the first opening. The organic layer has a second opening communicated with the first opening, a bottom surface defining the first opening and a sidewall defining the second opening. The light shielding pattern covers the first surface, the sidewall and the bottom surface and has a first portion located in the first opening and a second portion located in the second opening. The second portion protrudes from the organic layer. The first portion and the second portion respectively have a first width and a second width, and the first width is larger than the second width.

Description

Pixel array substrate

The present invention relates to a display panel, and particularly relates to a pixel array substrate.

With the vigorous development of the technology industry, display devices such as mobile phones, tablet computers, or eBooks have been widely used in daily life. Especially in recent years, with the emergence of multimedia applications such as stereoscopic display and virtual reality, in order to provide stunning visual effects, the demand for display panels with ultra-high resolution has gradually increased.

However, as the resolution of the display panel continues to increase, the layout space of the driving circuit is inevitably insufficient, which in turn causes the pixel aperture ratio to decrease. Therefore, how to maintain the existing cost advantage while improving the display panel resolution and pixel aperture ratio is one of the problems that relevant manufacturers are committed to overcome.

The present invention provides a pixel array substrate with a higher pixel aperture ratio.

The pixel array substrate of the present invention includes a substrate, a first signal line, a first pixel, an insulating layer, an organic layer, and a light-shielding pattern. The first signal line and the first pixel are arranged on the substrate. The first pixel includes a first active element and a first pixel electrode electrically connected to each other. The first active element is electrically connected to the first signal line. The insulating layer covers the substrate and has a first opening overlapping the first signal line. The first signal line has a first upper surface defining a first opening. The organic layer is disposed on the insulating layer and has a second opening connected to the first opening. The organic layer has a bottom surface defining the first opening and a side wall defining the second opening, and the bottom surface is connected to the side wall. The light-shielding pattern covers the first upper surface of the first signal line and the sidewall and bottom surface of the organic layer, and has a first portion located in the first opening and a second portion located in the second opening and protruding from the organic layer. The first part and the second part respectively have a first width and a second width, and the first width is greater than the second width.

In an embodiment of the present invention, the material of the first part and the second part of the light shielding pattern of the aforementioned pixel array substrate is the same.

In an embodiment of the present invention, the aforementioned pixel array substrate further includes spacers provided on the substrate. There is a first height between the first top surface of the light shielding pattern and the upper surface of the substrate. There is a second height between the spacer and the upper surface of the substrate, and the first height is smaller than the second height.

In an embodiment of the present invention, the light-shielding pattern and the spacer of the aforementioned pixel array substrate belong to the same film layer.

In an embodiment of the present invention, the organic layer of the aforementioned pixel array substrate is a stacked structure of a color filter layer and an organic insulating layer. The organic insulating layer covers the color filter layer and is provided with sidewalls defining the second opening.

In an embodiment of the present invention, the insulating layer of the above-mentioned pixel array substrate is a laminated structure of the first sub-insulating layer and the second sub-insulating layer. The first sub-insulating layer is located between the substrate and the first signal line. The second sub-insulating layer is located between the first signal line and the organic layer, and the first opening penetrates the second sub-insulating layer.

In an embodiment of the present invention, the first opening of the aforementioned pixel array substrate further penetrates the first sub-insulating layer. The first signal line further has a first lower surface defining the first opening and a first side surface connecting the first upper surface and the first lower surface, and the shading pattern further covers the first lower surface and the first side surface of the first signal line.

In an embodiment of the present invention, the aforementioned pixel array substrate further includes a second signal line and a second pixel. The second signal line is adjacent to the first signal line and is arranged in parallel on the substrate. The second signal line has a second upper surface defining the first opening, and the shading pattern further covers the second upper surface of the second signal line. The second pixel includes a second active element and a second pixel electrode electrically connected to each other. The second active element is electrically connected to the second signal line. The first signal line and the second signal line are located between the first pixel and the second pixel, and the shading pattern is located between the first signal line and the second signal line.

In an embodiment of the present invention, the insulating layer of the above-mentioned pixel array substrate is a laminated structure of the first sub-insulating layer and the second sub-insulating layer. The first sub-insulating layer is located between the substrate and the first signal line. The second sub-insulating layer is located between the first signal line and the organic layer, and the first opening penetrates the second sub-insulating layer.

In an embodiment of the present invention, the first opening of the aforementioned pixel array substrate further penetrates the first sub-insulating layer. The first signal line also has a first lower surface defining the first opening and a first side surface connecting the first upper surface and the first lower surface. The second signal line further has a second lower surface defining the first opening and a second side surface connecting the second upper surface and the second lower surface, and the light shielding pattern further covers the first lower surface and the first side surface of the first signal line and The second lower surface and the second side surface of the second signal line.

In an embodiment of the present invention, the organic layer of the aforementioned pixel array substrate is a color filter layer.

Based on the foregoing, in the pixel array substrate of an embodiment of the present invention, the insulating layer and the organic layer respectively have a first opening and a second opening that are connected to each other, and are electrically connected to the first signal line and the first signal line of the active element of the pixel. The two openings overlap. The width of the second portion of the light-shielding pattern located in the second opening is smaller than the width of the first portion of the light-shielding pattern located in the first opening, which can increase the layout space of the pixel electrode of the pixel and help increase the aperture ratio of the pixel. Ratio, AR).

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

As used herein, "approximately", "approximately", "essentially", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account all The measurement in question and the specific number of errors associated with the measurement (ie, the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or, for example, within ±30%, ±20%, ±15%, ±10%, ±5%. Furthermore, the "approximate", "approximate", "essential", or "substantially" used herein can be based on measurement properties, cutting properties, or other properties to select a more acceptable range of deviation or standard deviation, and Not one standard deviation applies to all properties.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connection" can refer to physical and/or electrical connection. Furthermore, "electrical connection" can mean that there are other components between the two components.

In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship between one element and another element, as shown in the figure. It should be understood that relative terms are intended to include different orientations of the device other than those shown in the figures. For example, if the device in one figure is turned over, elements described as being on the "lower" side of other elements will be oriented on the "upper" side of the other elements. Therefore, the exemplary term "lower" may include an orientation of "lower" and "upper", depending on the specific orientation of the drawing. Similarly, if the device in one figure is turned over, elements described as "below" or "below" other elements will be oriented "above" the other elements. Thus, the exemplary terms "above" or "below" can include an orientation of above and below.

Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.

FIG. 1 is a top view of a pixel array substrate according to a first embodiment of the invention. 2A to 2E are cross-sectional views of the manufacturing process of the pixel array substrate of FIG. 1. Fig. 2E corresponds to the section line A-A' of Fig. 1. 2F is a cross-sectional view of a display panel using the pixel array substrate of FIG. 2E. For clarity of presentation, FIG. 1 omits the illustration of the insulating layer 110, the organic insulating layer 122, the light shielding pattern 130, and the spacer 135 in FIG. 2E. In particular, the pixel array substrate 10 of FIG. 2E can be applied to the display panel 1 (as shown in FIG. 2F).

1 and 2E, the pixel array substrate 10 includes a substrate 101, a plurality of signal lines, and a plurality of pixels PX. In this embodiment, the multiple signal lines include multiple scan lines SL and multiple data lines DL. Multiple scan lines SL intersect multiple data lines DL and define multiple pixel regions. A plurality of pixels PX are respectively arranged in these pixel regions, and each is electrically connected to a corresponding scan line SL and a corresponding data line DL. For example, a plurality of data lines DL are arranged on the substrate 101 along the direction X and extend in the direction Y, wherein the direction X can be substantially perpendicular to the direction Y. A plurality of scan lines SL are arranged on the substrate 101 along the direction Y and extend in the direction X. In this embodiment, a pixel PX can be provided between any two adjacent data lines DL, and this pixel PX can be electrically connected to one of the two adjacent data lines DL, but the present invention Not limited to this.

In this embodiment, the pixel array substrate 10 may also optionally include a plurality of common lines CL. For example, these common lines CL may be arranged on the substrate 101 along the direction Y and extend in the direction X. That is, the common line CL can be selectively parallel to the scan line SL. Based on the consideration of conductivity, the data line DL, the scan line SL, and the common line CL are generally made of metal materials. However, the present invention is not limited to this. According to other embodiments, the data line DL, the scan line SL, and the common line CL may also use other conductive materials, such as alloys, nitrides of metallic materials, oxides of metallic materials, and metallic materials. Oxynitride, or other suitable materials, or stacked layers of metal materials and other conductive materials. It should be noted that the present invention does not limit the number of data lines DL, scan lines SL, and common lines CL without showing the content in figures. In some embodiments, the numbers of data lines DL, scan lines SL, and common lines CL It can be adjusted according to the actual number of pixels PX (ie the resolution of the display panel).

Furthermore, the pixel PX includes an insulating layer 110, an active device T, and a pixel electrode PE. The insulating layer 110 includes a first sub-insulating layer 111 and a second sub-insulating layer 112. The first sub-insulating layer 111 covers the scan line SL, and the second sub-insulating layer 112 covers part of the surface of the first sub-insulating layer 111 and the data line DL. And active component T. In this embodiment, the first sub-insulating layer 111 and the second sub-insulating layer 112 can be one or more than two inorganic insulating layers. The material of the inorganic insulating layer includes silicon oxide (SiO ₂ ) and silicon nitride (SiNx). , Silicon oxynitride (SiOxNy; x>y), silicon oxynitride (SiNxOy; x>y), or other suitable inorganic insulating materials.

For example, the method of forming the active device T may include the following steps: sequentially forming a gate electrode G, a first sub-insulating layer 111, a semiconductor pattern SC, an ohmic contact layer OC, a source electrode S and a drain electrode D on the substrate 101, The source S and the drain D are respectively electrically connected to two different regions of the semiconductor pattern SC through the ohmic contact layer OC (for example, two ohmic contact patterns). The source S and the drain D of the active device T are electrically connected to the data line DL and the pixel electrode PE, respectively. In this embodiment, the gate G of the active device T can be selectively arranged below the semiconductor pattern SC, that is, the gate G is located between the semiconductor pattern SC and the substrate 101 to form a bottom gate type thin film transistor (bottom gate). -gate TFT), but the present invention is not limited to this. According to other embodiments, the gate G of the active device can also be arranged above the semiconductor pattern SC to form a top-gate TFT.

On the other hand, the material of the semiconductor pattern SC is, for example, an amorphous silicon semiconductor (amorphous silicon semiconductor) material, that is, the active device T may be an amorphous silicon thin film transistor (a-Si TFT). However, the present invention is not limited to this. In other embodiments, the active device may also be a low-temperature polysilicon thin film transistor (LTPS TFT), a micro-Si TFT or a metal oxide transistor (Metal Oxide). Transistor). In this embodiment, the material of the ohmic contact layer OC may include metal oxide semiconductor materials containing dopants, polysilicon containing dopants, amorphous silicon containing dopants, or other suitable dopants containing Impurity semiconductor materials, or other suitable materials, or a combination of the above.

In this embodiment, the materials of the source S and the drain D of the active device T and the data line DL can be selectively the same, and the materials of the gate G and the scan line SL of the active device T can be selectively the same. In other words, the source S and drain D of the active device T and the data line DL can be formed on the same film layer, and the gate G and the scan line SL of the active device T can be formed on the same film layer. The pixel electrode PE can optionally be a penetrating electrode. The material of the penetrating electrode includes metal oxide, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or other suitable , Or a stacked layer of at least two of the above. However, the present invention is not limited to this. In other embodiments, the pixel electrode PE may also be a reflective electrode. The material of the reflective electrode includes metals, alloys, nitrides of metallic materials, oxides of metallic materials, and metallic materials. Oxynitride, or other suitable materials, or stacked layers of metal materials and other conductive materials.

The pixel array substrate 10 further includes an organic layer 120 and a light shielding pattern 130. The organic layer 120 is disposed on the insulating layer 110, and the light shielding pattern 130 overlaps the data line DL in the normal direction of the substrate 101. In other words, the light shielding pattern 130 may be located between two adjacent pixels PX arranged along the direction X. In this embodiment, the light shielding pattern 130 can selectively penetrate the organic layer 120 and the insulating layer 110 to cover the data line DL and a portion of the upper surface 101 s of the substrate 101. Accordingly, the optical density (OD) of the light shielding pattern 130 in the normal direction of the substrate 101 can be increased, which helps to reduce the reflection of the data line DL to ambient light, thereby improving the display panel’s performance Dark state performance. On the other hand, the pixel electrode PE of the pixel PX may be disposed on the organic layer 120 and penetrate the organic layer 120 and the second sub-insulating layer 112 to electrically connect to the drain D of the active device T. For example, the organic insulating layer 122 and the second sub-insulating layer 112 may be provided with a contact window 115, and the pixel electrode PE extends into the opening 121b of the color filter layer 121 and passes through the contact window 115 and the drain of the active device T.极 D electrical connection.

Furthermore, the insulating layer 110 and the organic layer 120 respectively have a first opening 110a and a second opening 120a overlapping the data line DL. The light shielding pattern 130 is disposed in the first opening 110a and the second opening 120a, and covers the upper surface DLa, the lower surface DLb, and the side surface DLc of the data line DL. The upper surface DLa is opposite to the lower surface DLb, and the side surface DLc is connected to the upper surface Between DLa and the lower surface DLb. From another point of view, the light shielding pattern 130 has a first portion 131 located in the first opening 110 a and a second portion 132 located in the second opening 120 a and protruding from the organic layer 120. The first portion 131 and the second portion 132 of the light shielding pattern 130 respectively have a first width W1 and a second width W2 in the direction perpendicular to the normal line of the substrate 101, and the first width W1 of the first portion 131 is greater than the first width W1 of the second portion 132. Two width W2.

It is worth mentioning that the configuration relationship between the first portion 131 and the data line DL (for example, in the direction perpendicular to the normal line of the substrate 101, the width of the first portion 131 is greater than the width of the data line DL), the light shielding pattern 130 can be ensured The light-shielding effect (for example, in the normal direction of the substrate 101, a plurality of liquid crystal molecules located in the overlapping area of the pixel electrode PE and the data line DL are generated by the configuration of the second part 132 on the surface of the organic layer 120 Light leakage caused by poor alignment). Therefore, the second width W2 of the second portion 132 of the light-shielding pattern 130 can be effectively reduced, which helps increase the layout space of the pixel electrode PE, thereby increasing the aperture ratio (AR) of the pixel PX.

The manufacturing process of the light shielding pattern 130 will be exemplarily described below. First, referring to FIGS. 2A and 2B, after the organic insulating material layer 122M is formed, an etching step is performed to remove a portion of the organic insulating material layer 122M overlapping the data line DL to form the organic insulating layer 122 of the pixel array substrate 10 , And the organic insulating layer 122 is provided with a second opening 120a. In this embodiment, the organic layer 120 may be a stacked structure of the color filter layer 121 and the organic insulating layer 122. However, the present invention is not limited to this. According to other embodiments, the organic layer may only be the color filter layer 121 (that is, the organic layer may not include the organic insulating layer 122).

In this embodiment, the material of the organic insulating layer 122 may be a polymer or other suitable materials, where the polymer includes acrylic resin, photosensitive resin, Polyimide, or composite material with the above-mentioned materials as the main component, or other suitable materials, or a combination of the above. On the other hand, the color filter layer 121 may have a plurality of color filter patterns, and the color filter patterns are separated from each other and arranged on the substrate 101 along the direction X (as shown in FIG. 1 ). In other words, the color filter layer 121 has a slot 121a between any two adjacent color filter patterns (for example, the first color filter pattern 1211 and the second color filter pattern 1212), and the slot 121a is The normal direction of the substrate 101 overlaps the data line DL and the second opening 120a.

2B and 2C, after the organic insulating layer 122 is formed, another etching step is performed to remove the insulating layer 110 that overlaps the data line DL in the normal direction of the substrate 101 to form the first insulating layer 110 Opening 110a. In this embodiment, the first opening 110a of the insulating layer 110 can expose the upper surface DLa, the lower surface DLb, and the side surface DLc of the data line DL, but the invention is not limited thereto.

For example, the etching step here may be a dry etching process, such as: using a reactive gas (etching gas) or ions or radicals to perform the portion of the insulating layer 110 exposed by the second opening 120a Etching, and the etching gas here has a relatively high selection for the material of the insulating layer 110 and the material of the organic layer 120. In other words, during the etching process of the insulating layer 110, the organic layer 120 is less likely to be etched by the etching gas. However, the present invention is not limited to this. According to other embodiments, the etching step of the insulating layer 110 may also be performed in a wet etching manner.

During the etching process of the insulating layer 110, the etching gas system penetrates the second opening 120a of the organic layer 120 to contact the insulating layer 110 and generate an etching reaction. Therefore, the first opening 110 a etched in the insulating layer 110 is connected to the second opening 120 a of the organic layer 120. In particular, the vertical projection area on the substrate 101 occupied by the first opening 110a of the insulating layer 110 is larger than the vertical projection area on the substrate 101 occupied by the second opening 120a of the organic layer 120.

2D, after the etching step of the insulating layer 110 is completed, a light-shielding material layer 130M is formed on the organic layer 120, and the light-shielding material layer 130M fills the first opening 110a of the insulating layer 110 and the second opening 110a of the organic layer 120 Opening 120a. Specifically, the organic layer 120 has a bottom surface 120s2 defining the first opening 110a and a sidewall 120s1 defining the second opening 120a and connected to the bottom surface 120s2, and the light-shielding material layer 130M fills the first opening 110a and the second opening 120a, Cover the sidewall 120s1 and bottom surface 120s2 of the organic layer 120 and the upper surface DLa, lower surface DLb and side surfaces DLc of the data line DL. In this embodiment, the material of the light-shielding material layer 130M may include a black resin material.

Next, a photolithographic etching process is performed on the light-shielding material layer 130M to form a light-shielding pattern 130, as shown in FIG. 2E. For example, in the step of forming the light-shielding pattern 130, spacers 135 overlapped on the active device T can also be formed at the same time. That is, the light shielding pattern 130 and the spacer 135 may belong to the same film layer. Specifically, the photolithography process here can selectively use a half-tone mask for exposure, where the half-tone area overlaps the data line DL, and the width of the half-tone area is slightly smaller than the data line DL However, the present invention is not limited to this. Here, the light-shielding pattern 130 of this embodiment is completed.

It should be noted that the present invention does not limit the manufacturing method of the light shielding pattern 130 based on the contents disclosed in FIGS. 2A to 2E. Those skilled in the art to which the present invention pertains should understand that the light shielding pattern 130 of this embodiment can also be formed through a relatively complicated manufacturing process. For example: after the insulating layer 110 is formed, the first part 131 of the light-shielding pattern 130 is first made, and the first part 131 penetrates the insulating layer 110 and covers the lower surface DLb of the data line DL; then, a second opening 120a is formed The organic layer 120 forms the second portion 132 of the light shielding pattern 130 in the second opening 120a, and the material of the first portion 131 and the second portion 132 connected to each other can be the same. However, the present invention is not limited to this. In other embodiments, the material of the first part of the shading pattern may be different from the material of the second part.

In this embodiment, the pixel array substrate 10 includes a substrate 101, a data line DL, a pixel PX, an insulating layer 110, an organic layer 120, and a light shielding pattern 130. The data line DL and the pixel PX are arranged on the substrate 101. The pixel PX includes an active device T and a pixel electrode PE electrically connected to each other, and the active device T is electrically connected to the data line DL. The insulating layer 110 has a first opening 110a overlapping the data line DL. The data line DL has an upper surface DLa defining the first opening 110a. The organic layer 120 is disposed on the insulating layer 110 and has a second opening 120a connected to the first opening 110a, a bottom surface 120s2 defining the first opening 110a, and a sidewall 120s1 defining the second opening 120a. The side wall 120s1 is connected to the bottom surface 120s2. The light-shielding pattern 130 covers the upper surface DLa of the data line DL and the sidewalls 120s1 and bottom surface 120s2 of the organic layer 120, and has a first portion 131 located in the first opening 110a and a second portion located in the second opening 120a and protruding from the organic layer 120 132. The first portion 131 and the second portion 132 have a first width W1 and a second width W2, respectively, and the first width W1 is greater than the second width W2.

In particular, in this embodiment, the area occupied by the second opening 120a of the organic layer 120 can completely overlap the data line DL in the normal direction of the substrate 101, and the first opening 110a is a mirror image with respect to the data line DL Symmetrical, but the present invention is not limited to this. In other embodiments, the area occupied by the second opening 120a of the organic layer 120 may partially overlap one side of the data line DL, and the first part of the light shielding pattern only covers one side DLc of the data line DL. It should be noted that the present invention is not limited to the content of the drawings. According to other embodiments, the first part of the light shielding pattern (or the first opening of the insulating layer) may also overlap the scan line SL or the common line CL.

For example, as shown in FIG. 1, a plurality of signal lines (such as two data lines DL, one scan line SL, and a common line CL) defining the opening area of a pixel PX and the pixels of this pixel PX The area where the electrodes PE are adjacent or overlapped can be the place where the light shielding pattern is set. And the width of the second part of the light-shielding pattern in the second opening is smaller than the width of the first part of the light-shielding pattern in the first opening, which can increase the layout space of the pixel electrode of the pixel and help increase the aperture ratio of the pixel PX (Aperture Ratio, AR).

Furthermore, the pixel array substrate 10 can be applied to the display panel 1, as shown in FIG. 2F. The display panel 1 further includes a substrate 201, driving electrodes 210, and a display medium layer DM. The substrate 201 and the pixel array substrate 10 are arranged opposite to each other, and the driving electrode 210 is arranged on a surface of the substrate 201 facing the pixel array substrate 10. The display medium layer DM is sandwiched between the driving electrode 210 and the pixel array substrate 10. In this embodiment, the display medium layer DM may include a plurality of liquid crystal molecules. That is, the display panel 1 is, for example, a liquid crystal display panel (LCD Panel). For example, in this embodiment, the driving electrode 210 is, for example, a common electrode, and has a ground potential. When the pixel electrode PE is activated to have a high potential, the electric field formed by the potential difference between the driving electrode 210 and the pixel electrode PE can drive the liquid crystal molecules to rotate. In this way, the light intensity of the backlight (not shown) after passing through the pixel PX can be controlled to achieve the effect of displaying the picture. In particular, the spacer 135 sandwiched between the substrate 201 and the pixel array substrate 10 can be used to control the thickness of the display medium layer DM in the normal direction of the substrate 101 to a set value.

Other embodiments will be listed below to describe the disclosure in detail, wherein the same components will be marked with the same symbols, and the description of the same technical content will be omitted. For the omitted parts, please refer to the foregoing embodiments, and will not be repeated below. In particular, the pixel array substrates of the following embodiments can be used to replace the pixel array substrate 10 in the display panel 1 described above.

3 is a cross-sectional view of the pixel array substrate of the second embodiment of the invention. Referring to FIG. 3, the main difference between the pixel array substrate 11 of this embodiment and the pixel array substrate 10 of FIG. 2E is that the configuration of the light shielding pattern is different. In this embodiment, the light shielding pattern 130A (or the second portion 132A) and the spacer 135 have a top surface 130As and a top surface 135s, respectively. There is a first height H1 between the top surface 130As of the light-shielding pattern 130A and the upper surface 101s of the substrate 101, the top surface 135s of the spacer 135 and the upper surface 101s of the substrate 101 have a second height H2, and the first height H1 is less than The second height H2.

It is worth mentioning that when the light-shielding material layer is formed, since the insulating layer 110 and the organic layer 120 are respectively provided with the first opening 110a and the second opening 120a, part of the film surface of the light-shielding material layer overlapping the second opening 120a can be recessed in Other parts of the membrane surface. Thereby, during the patterning process of the light-shielding material layer, the height difference between the light-shielding pattern 130A and the spacer 135 can be formed without using a half-tone mask for exposure. More specifically, in this embodiment, the light shielding pattern 130A may also have a function of auxiliary spacers. That is, through the height difference between the shading pattern 130A and the spacer 135, the thickness uniformity of the display medium layer can be improved, and the process latitude of the display panel can be increased, which helps to improve the production yield of the display panel .

4 is a cross-sectional view of the pixel array substrate of the third embodiment of the present invention. Referring to FIG. 4, the main difference between the pixel array substrate 12 of this embodiment and the pixel array substrate 10 of FIG. 2E is that the configuration of the light shielding pattern is different. In this embodiment, the first opening 110a-1 only penetrates the second sub-insulating layer 112, and the first portion 131 of the light shielding pattern 130B only covers the upper surface DLa of the data line DL. In other words, the first width W1' of the first portion 131A of the light shielding pattern 130B is smaller than the first width W1 of the first portion 131 of the light shielding pattern 130 of the pixel array substrate 10, but is still greater than the second width W2 of the second portion 132. Accordingly, without compromising the light-shielding effect of the light-shielding pattern 130B, the second width W2 of the second portion 132 of the light-shielding pattern 130B can be effectively reduced, which helps increase the layout space of the pixel electrode PE, thereby improving the picture Aperture Ratio (AR) of prime PX.

Fig. 5 is a top view of a pixel array substrate according to a fourth embodiment of the present invention. FIG. 6 is a cross-sectional view of the pixel array substrate of FIG. 5. 5 and 6, the main difference between the pixel array substrate 20 of this embodiment and the pixel array substrate 10 of FIG. 1 lies in the difference in the arrangement relationship between the signal lines and the pixels and the structure of the first part of the light shielding pattern. Different types. In this embodiment, two adjacent pixels (for example, the first pixel PX1 and the second pixel PX2) arranged in the direction X may be provided with two signal lines, namely the first data line DL1 and the second pixel Two data lines DL2, where the first data line DL1 and the second data line DL2 are adjacent and arranged in parallel on the substrate 101. The first pixel PX1 and the second pixel PX2 are electrically connected to the first data line DL1 and the second data line DL2, respectively.

In this embodiment, the first portion 131B of the light shielding pattern 130C simultaneously covers the upper surface DL1a, the lower surface DL1b, and the side surface DL1c of the first data line DL1, and the upper surface DL2a, the lower surface DL2b, and the side surface DL2c of the second data line DL2. . In other words, the light shielding pattern 130C is disposed in the area between the first data line DL1 and the second data line DL2. The first part 131B covers part of the first data line DL1, part of the second data line DL2, and the area between the two data lines, which can block the backlight from emitting from the area between the two data lines to cause light leakage, and By shortening the width of the second portion 132 in the direction perpendicular to the normal line of the substrate 101, the layout space of the pixel electrode can be increased, thereby increasing the aperture ratio (AR) of the pixel.

On the other hand, the pixel electrode of each pixel of this embodiment can be divided into a first sub-part PEa and a second sub-part PEb, and the active device T'can have two drains, namely a drain D1 and a drain D2, where the first sub-part PEa and the second sub-part PEb of the pixel electrode are electrically connected to the drain D1 and the drain D2 of the active device T′, but the invention is not limited thereto.

FIG. 7 is a cross-sectional view of the pixel array substrate of the fifth embodiment of the present invention. Please refer to FIG. 7, the main difference between the pixel array substrate 21 of this embodiment and the pixel array substrate 20 of FIG. 6 is that the composition of the organic layer is different. In this embodiment, the organic layer 120 only includes the color filter layer 121, and an inorganic insulating layer 140 is provided between the spacer 135 (or pixel electrode) and the color filter layer 121. More specifically, the groove 121a of the color filter layer 121 can define the second opening 120a-1 of the organic layer 120A, and the width of the second portion 132B of the light shielding pattern 130D in the normal direction perpendicular to the substrate 101 is increased from the first The inside of the two openings 120a-1 gradually shrinks toward the top surface 130Ds of the light shielding pattern 130D. In particular, since the bottom of the second opening 120a-1 located on the side of the insulating layer 110 has a larger diameter, during the etching process of the insulating layer 110, the reaction time can be shortened and the etching efficiency can be improved. In this embodiment, the material of the inorganic insulating layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a stacked layer of at least two of the foregoing materials.

To sum up, in the pixel array substrate of an embodiment of the present invention, the insulating layer and the organic layer respectively have a first opening and a second opening that are connected to each other, and are electrically connected to the first signal of the active element of the pixel The line overlaps the two openings. The width of the first part of the light-shielding pattern in the first opening is greater than the width of the second part of the light-shielding pattern in the second opening, which can increase the layout space of the pixel electrode of the pixel and help increase the aperture ratio of the pixel (Aperture Ratio, AR).

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

1: display panel

10, 11, 12, 20, 21: pixel array substrate

101, 201: substrate

101s: upper surface

110: insulating layer

110a, 110a-1: first opening

111: first sub-insulating layer

112: second sub-insulation layer

115: contact window

120: organic layer

120a, 120a-1: second opening

120s1: sidewall

120s2: bottom surface

121: Color filter layer

121a: Slotting

121b: opening

1211, 1212: color filter pattern

122: organic insulating layer

122M: organic insulating material layer

130, 130A, 130B, 130C, 130D: shading pattern

130As, 130Ds, 135s: top surface

130M: shading material layer

131, 131A, 131B: Part One

132, 132A, 132B: Part Two

135: Interstitial Object

210: drive electrode

CL: Common line

D, D1, D2: drain

DL, DL1, DL2: data line

DLa, DL1a, DL2a: upper surface

DLb, DL1b, DL2b: bottom surface

DLc, DL1c, DL2c: side

DM: display medium layer

G: Gate

H1: first height

H2: second height

OC: Ohmic contact layer

PE: pixel electrode

PEa: First subsection

PEb: Second subsection

PX, PX1, PX2: pixels

S: source

SC: Semiconductor pattern

SL: scan line

T, T’: Active component

W1, W’: first width

W2: second width

X, Y: direction

A-A’, B-B’, C-C’: cut line

FIG. 1 is a top view of a pixel array substrate according to a first embodiment of the invention. 2A to 2E are cross-sectional views of the manufacturing process of the pixel array substrate of FIG. 1. 2F is a cross-sectional view of a display panel using the pixel array substrate of FIG. 2E. 3 is a cross-sectional view of the pixel array substrate of the second embodiment of the invention. 4 is a cross-sectional view of the pixel array substrate of the third embodiment of the present invention. Fig. 5 is a top view of a pixel array substrate according to a fourth embodiment of the present invention. FIG. 6 is a cross-sectional view of the pixel array substrate of FIG. 5. FIG. 7 is a cross-sectional view of the pixel array substrate of the fifth embodiment of the present invention.

10: Pixel array substrate

101: substrate

101s: upper surface

110: insulating layer

110a: first opening

111: first sub-insulating layer

112: second sub-insulation layer

120: organic layer

120a: second opening

120s1: sidewall

120s2: bottom surface

121: Color filter layer

1211, 1212: color filter pattern

122: organic insulating layer

130: shading pattern

131: Part One

132: Part Two

135: Interstitial Object

CL: Common line

D: Dip pole

DL: Data line

DLa: upper surface

DLb: bottom surface

DLc: side

G: Gate

OC: Ohmic contact layer

PE: pixel electrode

PX: pixel

S: source

SC: Semiconductor pattern

SL: scan line

T: Active component

W1: first width

W2: second width

A-A’: Cut line

Claims (9)

A pixel array substrate includes: a substrate; a first signal line arranged on the substrate; a first pixel arranged on the substrate, the first pixel including: a first active element, electrical Connected to the first signal line; and a first pixel electrode electrically connected to the first active device; an insulating layer covering the substrate, the insulating layer having a first opening overlapping the first signal line, wherein The first signal line has a first upper surface that defines the first opening; an organic layer is disposed on the insulating layer, the organic layer has a second opening connected to the first opening, and the organic layer has A bottom surface defining the first opening and a side wall defining the second opening, and the bottom surface is connected to the side wall; a shading pattern covering the first upper surface of the first signal line and the side wall and the organic layer The bottom surface has a first portion located at the first opening and a second portion located at the second opening and protruding from the organic layer, wherein the first portion and the second portion respectively have a first width and a A second width, and the first width is greater than the second width; and a spacer is disposed on the substrate, wherein there is a first height between a first top surface of the shading pattern and an upper surface of the substrate There is a second height between a second top surface of the spacer and the upper surface of the substrate, and the first height is smaller than the second height, and the shading pattern and the spacer belong to the same film layer. According to the pixel array substrate described in claim 1, wherein the material of the first part and the second part of the light shielding pattern is the same. The pixel array substrate according to item 1 of the scope of patent application, wherein the organic layer is a stacked structure of a color filter layer and an organic insulating layer, the organic insulating layer covers the color filter layer and has a definition The side wall of the second opening. According to the pixel array substrate described in claim 1, wherein the insulating layer is a laminated structure of a first sub-insulating layer and a second sub-insulating layer, and the first sub-insulating layer is located between the substrate and the second sub-insulating layer. Between a signal line, the second sub-insulating layer is located between the first signal line and the organic layer, and the first opening penetrates the second sub-insulating layer. The pixel array substrate according to claim 4, wherein the first opening further penetrates the first sub-insulation layer, the first signal line further has a first lower surface defining the first opening and connecting the A first side surface of the first upper surface and the first lower surface, and the shading pattern further covers the first lower surface and the first side surface of the first signal line. The pixel array substrate described in claim 1 further includes: a second signal line adjacent to the first signal line and arranged in parallel on the substrate, wherein the second signal line defines the first signal line A second upper surface of an opening, and the shading pattern further covers the second upper surface of the second signal line; and a second pixel disposed on the substrate, the second pixel including: a second An active element electrically connected to the second signal line; and a second pixel electrode electrically connected to the second active element, The first signal line and the second signal line are located between the first pixel and the second pixel, and the shading pattern is located between the first signal line and the second signal line. According to the pixel array substrate described in claim 6, wherein the insulating layer is a laminated structure of a first sub-insulating layer and a second sub-insulating layer, and the first sub-insulating layer is located between the substrate and the second sub-insulating layer. Between a signal line, the second sub-insulating layer is located between the first signal line and the organic layer, and the first opening penetrates the second sub-insulating layer. The pixel array substrate according to claim 7, wherein the first opening further penetrates the first sub-insulating layer, and the first signal line further has a first lower surface defining the first opening and connecting the A first side surface of the first upper surface and the first lower surface, the second signal line further has a second lower surface defining the first opening and a first connecting the second upper surface and the second lower surface Two side surfaces, and the shading pattern further covers the first lower surface and the first side surface of the first signal line and the second lower surface and the second side surface of the second signal line. According to the pixel array substrate described in item 1 of the scope of patent application, the organic layer is a color filter layer.

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