TWI698833B - Graphics processor system - Google Patents

Abstract

The present invention provides a graphics processor system, the graphics processor system comprising: a central processing unit, a plurality of graphics processors communicatively coupled to the central processing unit, a bus communication protocol switch, and the plurality of graphics processor is connected to implement mutual communication between the graphics processors, a management board is separately connected to the bus communication protocol exchange for managing the bus communication protocol switch. The invention provides a bus bar communication protocol switch, which can maximize and equalize the peer-to-peer network communication bandwidth between the graphics processors, and the theoretical maximum bidirectional bandwidth can reach 300 GB/s, and can further expand an eight-graphic processing. The system forms a sixteen graphics processor system that enables peer-to-peer network communication of any two graphics processors.

Description

Graphics processor system

The invention belongs to the technical field of data processing, and relates to a data processing system, in particular to a graphics processor system.

With the rapid development of virtual reality and artificial intelligence technologies, the demand for systems with massive data computing and processing capabilities has gradually increased. Graphics Processing Unit (GPU) is known for its high computing performance and has become extremely popular in recent years.

GPU, also known as display core, visual processor, and display chip, is a microprocessor that performs image operations on personal computers, workstations, game consoles, and some mobile devices (such as tablet computers, smart phones, etc.). The purpose of GPU is to convert and drive the display information required by the computer system, and to provide line scan signals to the display to control the correct display of the display. It is an important component for connecting the display to the motherboard of a personal computer, and it is also an important part of "human-machine dialogue". One of the equipment.

In practical applications, the use of multi-GPU systems to enhance graphics processing capabilities is a common method. However, due to the limitations of the communication interface between GPU and CPU and the limitation of the communication bandwidth between GPUs and GPUs, the graphics processing capabilities of multi-GPU systems are also Limited, and can not show the effect of exponential enhancement as the number of GPUs increases.

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a graphics processor system for solving the problem of low communication rate of the existing multi-GPU system.

In order to achieve the above-mentioned objects and other related objects, the present invention provides a graphics processor system. The graphics processor system includes: a central processing unit; a plurality of graphics processing units connected in communication with the central processing unit; and a bus communication A protocol switch, connected to the plurality of graphics processors, and used to implement mutual communication between the graphics processors; a management board, respectively, communicatively connected to the bus communication protocol switch, and used to communicate with the bus Agreement switch for management.

In an embodiment of the present invention, the bus communication protocol switch includes: at least one bus communication protocol switching module; the bus communication protocol switching module includes 6 bus communication protocol switching modules; each bus The communication protocol exchange module is equipped with 16 sets of bus communication protocol ports; each set of bus communication protocol ports of each bus communication protocol exchange module is used to connect a graphics processor or expansion; the bus communication protocol management module, and The bus communication protocol exchange modules are connected, and are used to manage the communication between each group of bus communication protocol ports of each bus communication protocol exchange module.

In an embodiment of the present invention, the 8 sets of bus communication protocol ports in the bus communication protocol switching module are used to connect 8 graphics processors in a one-to-one correspondence, and each bus communication protocol switching module is The remaining 8 sets of bus communication protocol ports are used for expansion.

In an embodiment of the present invention, the graphics processor system further includes: a high-speed serial computer expansion bus standard switch group, which is connected to the central processing unit and a plurality of graphics processing units, respectively, for expanding the The high-speed serial computer expansion bus standard port of the central processing unit realizes the mutual communication between the graphics processor and the central processing unit; a high-speed serial computer expansion bus standard expansion module is connected to the high-speed serial computer Column computer extended bus standard switch group, said bus communication protocol The management module and the management board are respectively connected in communication; the management board expands the bus standard switch group and the bus communication protocol to the high-speed serial computer through the high-speed serial computer expansion bus standard expansion module The switch is managed.

In an embodiment of the present invention, the high-speed serial computer expansion bus standard switch group includes: a first high-speed serial computer expansion bus standard switch connected to the central processing unit; and a second high-speed serial computer expansion bus standard switch The computer expansion bus standard switch is connected to the first high-speed serial computer expansion bus standard switch; the second high-speed serial computer expansion bus standard switch is downstream connected to a plurality of graphics processors; a third high-speed serial The computer expansion bus standard switch is connected to the first high-speed serial computer expansion bus standard switch; the third high-speed serial computer expansion bus standard switch is connected downstream to a plurality of graphics processors; the management board is connected to the The first high-speed serial computer expansion bus standard switch, the second high-speed serial computer expansion bus standard switch, and the third high-speed serial computer expansion bus standard switch are respectively connected to the first high-speed serial computer The expansion bus standard switch, the second high-speed serial computer expansion bus standard switch and the third high-speed serial computer expansion bus standard switch for management settings.

In an embodiment of the present invention, the first high-speed serial computer expansion bus standard switch includes: at least one first host port for communicating with the central processing unit; at least two first optical fiber communication ports , Used to respectively communicate with the second high-speed serial computer expansion bus standard switch and the third high-speed serial computer expansion bus standard switch; at least one first uplink port is used to communicate with the management board Connected.

In an embodiment of the present invention, the second high-speed serial computer expansion bus standard switch includes: at least one second optical fiber communication port for communicating with one of the first high-speed serial computer expansion bus standard switch The first optical fiber communication port is communicatively connected; at least one second uplink port is used to communicate with the tube The management board is connected in communication; at least one second downstream port is used to communicate with the graphics processor.

In an embodiment of the present invention, the third high-speed serial computer expansion bus standard switch includes: at least one third optical fiber communication port for connecting to another standard switch of the first high-speed serial computer expansion bus A first optical fiber communication port is used for communication connection; at least one third uplink port is used for communication connection with the management board; at least one third downlink port is used for communication connection with a graphics processor.

In an embodiment of the present invention, a second downstream port of the second high-speed serial computer expansion bus standard switch is used to connect a network card or a solid state drive; or/and the third high-speed serial computer expansion bus A third downstream port of the standard switch is used to connect a network card or a solid state drive.

In an embodiment of the present invention, the first high-speed serial computer expansion bus standard switch, the second high-speed serial computer expansion bus standard switch, and the third high-speed serial computer expansion bus standard switch all work in virtual Mode; The management board dynamically manages the first high-speed serial computer expansion bus standard switch, the second high-speed serial computer expansion bus standard switch and the third high-speed serial computer expansion bus standard switch.

As mentioned above, the graphics processor system of the present invention has the following beneficial effects:

The present invention proposes a bus communication protocol switch, which can maximize and equalize the communication bandwidth of the peer-to-peer network between graphics processors. The theoretical maximum two-way bandwidth can reach 300GB/s, and it can also expand an eight graphics processing The processor system constitutes a sixteen graphics processor system, which can realize peer-to-peer network communication between any two graphics processors.

100: Graphics processor system

110: central processing unit

120: graphics processor

130: Bus communication protocol switch

131: Bus communication protocol exchange module

1311: Bus communication protocol exchange module

132: Bus communication protocol management module

140: Management Board

150: High-speed serial computer expansion bus standard switch group

151: The first high-speed serial computer expansion bus standard switch

1511: First host port

1512: The first optical fiber communication port

1513: first uplink port

152: The second high-speed serial computer expansion bus standard switch

1521: Second fiber optic communication port

1522: second upstream port

1523: second downstream port

153: The third high-speed serial computer expansion bus standard switch

1531: Third fiber optic communication port

1532: third upstream port

1533: third downstream port

160: High-speed serial computer expansion bus standard expansion module

FIG. 1 shows a schematic diagram of an exemplary implementation structure of a graphics processor system according to an embodiment of the present invention.

Fig. 2 is a schematic diagram showing an exemplary implementation structure of the bus communication protocol switch of the graphics processor system according to the embodiment of the present invention.

FIG. 3 is a schematic diagram of an exemplary communication structure of the bus communication protocol switch of the graphics processor system according to the embodiment of the present invention.

FIG. 4 is a schematic diagram showing another exemplary implementation structure of the graphics processor system according to the embodiment of the present invention.

FIG. 5A is a schematic diagram showing an exemplary port structure of the first high-speed serial computer expansion bus standard switch of the graphics processor system according to an embodiment of the present invention.

5B is a schematic diagram showing an exemplary port structure of the second high-speed serial computer expansion bus standard switch of the graphics processor system according to the embodiment of the present invention.

5C is a schematic diagram showing an exemplary port structure of the third high-speed serial computer expansion bus standard switch of the graphics processor system according to the embodiment of the present invention.

6A and 6B are schematic diagrams showing a specific implementation structure of a graphics processor system according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of another specific implementation structure of the graphics processor system according to the embodiment of the present invention.

The following describes the implementation of the present invention through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and the features in the embodiments can be combined with each other if there is no conflict.

It should be noted that the illustrations provided in the following embodiments only illustrate the basic idea of the present invention in a schematic manner. The figures only show the components related to the present invention instead of the number, shape, and number of components in actual implementation. For the size drawing, the type, number, and ratio of each component can be changed at will during actual implementation, and the component layout type may be more complicated.

A multi-graphics processing unit (GPU) system not only requires high bandwidth performance between the GPU and the central processing unit (CPU), but also requires high bandwidth capabilities between the GPUs. That is, the Peer to Peer (Peer to Peer) bandwidth. In order to increase the bandwidth of a multi-GPU system, the present invention provides a graphics processor system. As shown in FIG. 1, the graphics processor system 100 includes: a central processing unit (CPU) 110, a plurality of graphics processors 120, The bus communication protocol switch 130, or/and a management board 140. The plurality of graphics processors 120 are connected to the central processing unit 110 in communication. The bus communication protocol switch 130 is connected to the plurality of graphics processors 120, and is used to implement mutual communication between the graphics processors. The management board 140 is respectively communicatively connected with the bus communication protocol switch 130, and is used to manage the bus communication protocol switch.

In the present invention, NVLink is a bus and its communication protocol developed and launched by NVIDIA. NVLink adopts a point-to-point structure and serial transmission, which is used for the connection between GPU and GPU, and can also be used for connection between CPU and GPU. The NVLink port is a point-to-point communication port between GPU and GPU or between CPU and GPU. The bus communication protocol switch 130 is an NVLink switch.

Referring to FIG. 2, in an embodiment of the present invention, the bus communication protocol switch 130 includes: at least one bus communication protocol switching module 131, and a bus communication protocol management module 132; The bus communication protocol exchange module 131 includes 6 bus communication protocol exchange modules 1311; each bus communication protocol exchange module 1311 is provided with 16 sets of bus communication protocol ports; each bus communication protocol exchange module Each set of bus communication protocol ports is used to connect a graphics processor or an extension; the bus communication protocol management module 132 is connected to each bus communication protocol exchange module 1311 for managing each bus communication protocol exchange module Communication between the bus communication protocol ports of each group in the group.

Referring to FIG. 3, in an embodiment of the present invention, the 8 sets of bus communication protocol ports in the bus communication protocol switch module 1311 are used to connect 8 graphics processors in a one-to-one correspondence, and each bus The remaining 8 sets of bus communication protocol ports in the communication protocol exchange module are used for expansion.

Referring to FIG. 4, in an embodiment of the present invention, the graphics processor system 100 further includes: a high-speed serial computer expansion bus standard switch group 150, or/and a high-speed serial computer expansion bus standard expansion Module 160. The high-speed serial computer expansion bus standard switch group 150 is respectively connected to the central processing unit 110 and a plurality of graphics processors 120, and is used to expand the high-speed serial computer expansion bus standard port of the central processing unit to realize The mutual communication between the graphics processor and the central processing unit. The high-speed serial computer expansion bus standard expansion module 160 is respectively communicatively connected with the high-speed serial computer expansion bus standard switch group 150, the bus communication protocol management module 132 and the management board 140. The management board 140 manages the high-speed serial computer expansion bus standard switch group 150 and the bus communication protocol switch 130 through the high-speed serial computer expansion bus standard expansion module 160.

Referring to FIG. 4, in an embodiment of the present invention, the high-speed serial computer expansion bus standard switch group 150 includes: a first high-speed serial computer expansion bus standard switch 151, and a second high-speed serial computer An extended bus standard switch 152, or/and a third high-speed serial computer extended bus standard switch 153. The first high-speed serial computer expansion bus standard switch 151 and The central processing unit 110 is connected. The second high-speed serial computer expansion bus standard switch 152 is connected to the first high-speed serial computer expansion bus standard switch 151; the second high-speed serial computer expansion bus standard switch 152 is downstream connected to a plurality of graphics The processor 120. The third high-speed serial computer expansion bus standard switch 153 is connected to the first high-speed serial computer expansion bus standard switch 151; the third high-speed serial computer expansion bus standard switch 153 is connected downstream with a plurality of graphics The processor 120. The management board 140 is connected to the first high-speed serial computer expansion bus standard switch 151, the second high-speed serial computer expansion bus standard switch 152, and the third high-speed serial computer expansion bus standard switch 153, respectively. The first high-speed serial computer expansion bus standard switch 151, the second high-speed serial computer expansion bus standard switch 152, and the third high-speed serial computer expansion bus standard switch 153 are managed.

Further, the first high-speed serial computer expansion bus standard switch 151, the second high-speed serial computer expansion bus standard switch 152, and the third high-speed serial computer expansion bus standard switch 153 all work in a virtual mode; The management board 140 dynamically manages the first high-speed serial computer expansion bus standard switch 151, the second high-speed serial computer expansion bus standard switch 152, and the third high-speed serial computer expansion bus standard switch 153.

Referring to FIG. 5A, in an embodiment of the present invention, the first high-speed serial computer expansion bus standard switch 151 includes: at least one first host port 1511, at least two first optical fiber communication ports 1512, and at least one The first uplink port 1513. The at least one first host port 1511 is used to communicate with the central processing unit; the at least two first optical fiber communication ports 1512 are used to communicate with the second high-speed serial computer expansion bus standard switch 152 and The third high-speed serial computer expansion bus standard switch 153 is communicatively connected; the at least one first uplink port 1513 is used to communicatively connect to the management board.

Referring to FIG. 5B, in an embodiment of the present invention, the second high-speed serial computer expansion bus standard switch 152 includes: at least one second optical fiber communication port 1521, at least one second uplink port 1522, and at least one second The second downstream port is 1523. The at least one second optical fiber communication port 1521 is used to communicate with a first optical fiber communication port 1512 of the first high-speed serial computer expansion bus standard switch; the at least one second uplink port 1522 is used to communicate with all The management board 140 is communicatively connected; the at least one second downlink port 1523 is used for communicatively connected to the graphics processor 120. A second downstream port of the second high-speed serial computer expansion bus standard switch 152 is used to connect a network card or a solid state drive.

Referring to FIG. 5C, in an embodiment of the present invention, the third high-speed serial computer expansion bus standard switch 153 includes: at least one third optical fiber communication port 1531, at least one third uplink port 1532, and at least one Three downstream ports 1533. The at least one third optical fiber communication port 1531 is used to communicate with another first optical fiber communication port of the first high-speed serial computer expansion bus standard switch; the at least one third uplink port 1532 is used to communicate with all The management board is communicatively connected; the at least one third downstream port 1533 is used for communicative connection with the graphics processor. A third downstream port of the third high-speed serial computer expansion bus standard switch 153 is used to connect a network card or a solid state drive.

With the progress of the times, customers’ demands for GPU system performance continue to increase. At the same time, the technology of GPU vendors has also been improving, and we need to design an excellent architecture to give full play to the high performance of GPU products in order to provide The customer's product is competent for the corresponding business.

The original SXM2 GPU system uses a three-switch architecture to extend the PCIE port of the CPU to the GPU. Among them, the first-level switch adopts virtual mode to support dual X16 PCIE to the CPU, providing sufficient bandwidth for the communication between the CPU and GPU. It can still be used in the new generation SXM3 GPU system of the present invention; for the mutual communication between GPUs, NVLink interconnection is used to provide a direct peer-to-peer network (Peer to Peer) communication, the other part is realized by the optical fiber communication mode of the PCIE switch (PCIE switch), as shown in Figures 6A and 6B. However, the communication of this part of the GPU peer-to-peer network still uses the PCIE protocol, with a maximum speed of 8Gbps, which is much lower than the 25Gbps interconnection speed of NVLink. Therefore, in the SXM3 GPU system, the use of a bus communication protocol switch (NVLink switch) can realize that all communications between GPUs use the NVLink protocol, which can maximize the peer-to-peer network bandwidth between any GPUs. The system topology is shown in Figure 7. Shown.

In the topology diagram of the SXM3 GPU system shown in Figure 7, the communication part between the CPU and GPU still uses the structure of three PCIE switches (PEX9797). The first switch is the virtual mode (virtual mode) working mode, and the internal is divided into two Virtual bridges VS0 and VS1, the two virtual bridges respectively connect a set of X16 PCIE to the CPU to achieve the communication bandwidth of 32 PCIE lanes between GPU and CPU; because NVLink optical fiber communication requires a set of X4 PCIEs for NV-Switch management , The second switch is connected to a PEX8749 as a PCIE expansion, and it works in virtual mode as well. One of the virtual bridges VS0 is used to manage and expand NVLink optical fiber communication. A set of X16 PCIE network cards and SSDs are used; the other virtual bridge VS1 For PCIE switch optical fiber communication management, the downstream is connected to three PEX9797 management ports, which are X1 PCIE, and the upstream is connected to the management board through HD mini SAS, which is X4 PCIE. The downstream control port is reserved for PCIE switch optical fiber. The communication expansion is X1 PCIE. The peer-to-peer network communication between GPU and GPU uses NVLink optical fiber communication structure. Each SXM3 GPU has six sets of NVLink ports, and each set of NVLink ports is connected to an NV-Switch (bus communication protocol switch module), a total of 8×6 NVLink; each NV-Switch has sixteen sets of NVLink ports, In addition to the eight groups interconnected with the internal GPU, there are eight groups used as the expansion of NVLink optical fiber communication, that is, the 16 GPU system. When two GPUs need to communicate, such as GPU1 and GPU2, since each GPU has a set of NVLink ports to connect to the NV-Switch, the host can manage six NV-Switches through PEX8725, Make the NVLink of GPU1 and GPU2 communicate, so that there can be six groups of NVLink jobs at the same time to provide data transmission between GPUs. Each group of NVLink can provide a two-way bandwidth of about 50GB/s, and the total bandwidth can reach 300GB/s.

The topology of the SXM3 GPU system is improved from the SXM2 GPU system. In addition to the original advantages, it also has the following advantages:

The optical fiber communication mode of the PCIE switch of the present invention is mainly used for multi-switch networking, and the dynamic management of the switch by the management port can realize flexible communication between multiple hosts (CPU) and multiple terminals (GPU).

The present invention can solve the problem of low frequency bandwidth of peer-to-peer network communication between GPUs, and can provide high frequency bandwidth between GPU and CPU.

After the second-level PCIE switch is connected to the network through the network card, the present invention can realize the direct exchange of data between different GPU systems in the same network without passing through the CPU and its memory, which greatly improves the communication between GPU systems. Data exchange capability.

In addition, the present invention maximizes and equalizes the communication bandwidth of the peer-to-peer network between GPUs. The theoretical maximum two-way bandwidth can reach 300GB/s, and an eight-GPU system can be expanded to form a sixteen-GPU system. The peer-to-peer network communication of any two GPUs; the present invention combines the optical fiber communication of PCIE switch (high-speed serial computer expansion bus standard switch group 150) and the optical fiber communication management link of NVLink switch into one switch (PEX8749 in the figure, high-speed In the serial computer expansion bus standard expansion module), the board structure is simplified.

In summary, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial value.

The above-mentioned embodiments only exemplarily illustrate the principles and effects of the present invention, and are not intended to limit The invention is made. Anyone familiar with this technology can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

100 Graphics processor system 110 Central processor 120 Graphics processor 130 Bus communication protocol switch 140 Management board

Claims (9)

A graphics processor system, comprising: a central processing unit; a plurality of graphics processing units, which are connected in communication with the central processing unit; a bus communication protocol switch, which is connected to the graphics processing units and used to implement each of the graphics processing units A management board, which is respectively connected to the bus communication protocol switch and used to manage the bus communication protocol switch, wherein the bus communication protocol switch includes: at least one bus communication protocol switch module Group, the bus communication protocol switching module includes 6 bus communication protocol switching modules; each of the bus communication protocol switching modules is equipped with 16 sets of bus communication protocol ports; each of the bus communication protocol switching modules Each of these sets of bus communication protocol ports is used to connect a graphics processor or an extension; a bus communication protocol management module is connected to each of the bus communication protocol switching modules for managing each of the buses Communication between the groups of bus communication protocol ports of the communication protocol exchange module. For the graphics processor system according to claim 1, the 8 sets of bus communication protocol ports in the bus communication protocol switching modules are used to connect 8 graphics processors one by one, each of the bus communication protocols The remaining 8 sets of these bus communication protocol ports in the switch module are used for expansion. The graphics processor system according to claim 1, the graphics processor system further comprising: A high-speed serial computer expansion bus standard switch group is respectively connected to the central processing unit and a plurality of graphics processors, and a high-speed serial computer expansion bus standard port used to expand the central processing unit to realize the graphics processing The mutual communication between the processor and the central processor; a high-speed serial computer expansion bus standard expansion module, and the high-speed serial computer expansion bus standard switch group, the bus communication protocol management module and the management board They are respectively connected by communication; the management board manages the high-speed serial computer expansion bus standard switch group and the bus communication protocol switch through the high-speed serial computer expansion bus standard expansion module. The graphics processor system according to claim 3, wherein the high-speed serial computer expansion bus standard switch group includes: a first high-speed serial computer expansion bus standard switch connected to the central processing unit; and a second high-speed serial computer expansion bus standard switch The serial computer expansion bus standard switch is connected to the first high-speed serial computer expansion bus standard switch; the second high-speed serial computer expansion bus standard switch is connected downstream to a plurality of graphics processors; a third high-speed serial The computer expansion bus standard switch is connected to the first high-speed serial computer expansion bus standard switch; the third high-speed serial computer expansion bus standard switch is connected downstream to a plurality of graphics processors; the management board is connected to the first high-speed The serial computer expansion bus standard switch, the second high-speed serial computer expansion bus standard switch and the third high-speed serial computer expansion bus standard switch are respectively connected for the first high-speed serial computer expansion bus The standard switch, the second high-speed serial computer expansion bus standard switch and the third high-speed serial computer expansion bus standard switch perform management settings. The graphics processor system according to claim 4, wherein the first high-speed serial computer expansion bus standard switch includes: at least one first host port for communicating with the central processing unit; and at least two first optical fibers The communication ports are used to communicate with the second high-speed serial computer expansion bus standard switch and the third high-speed serial computer expansion bus standard switch respectively; at least one first uplink port is used to communicate with the management board . The graphics processor system according to claim 5, wherein the second high-speed serial computer expansion bus standard switch includes: at least one second optical fiber communication port for communicating with the first high-speed serial computer expansion bus standard switch At least one second uplink port is used to communicate with the management board; at least one second downlink port is used to communicate with the graphics processor. The graphics processor system according to claim 6, wherein the third high-speed serial computer expansion bus standard switch includes: at least one third optical fiber communication port for communicating with the first high-speed serial computer expansion bus standard switch At least one third uplink port is used to communicate with the management board; at least one third downlink port is used to communicate with the graphics processor. The graphics processor system according to claim 7, wherein a second downstream port of the second high-speed serial computer expansion bus standard switch is used for connecting a network card or a solid state drive; or the third high-speed serial computer A third downstream port of the extended bus standard switch is used to connect a network card or a solid state drive. The graphics processor system according to claim 4, wherein the first high-speed serial computer expansion bus standard switch, the second high-speed serial computer expansion bus standard switch, and the third high-speed serial computer expansion bus standard The switches all work in virtual mode; the management board performs operations on the first high-speed serial computer expansion bus standard switch, the second high-speed serial computer expansion bus standard switch, and the third high-speed serial computer expansion bus standard switch Dynamic management.

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