TWI696180B - Solid state storage device using prediction function - Google Patents

Abstract

AThe present invention is a solid state storage device using a prediction function. In the solid state storage device, the controller generates a plurality of collection read operations, temporarily stores the collection read operations in the command queue, and transmits the collection read operations to the non-volatile memory. The non-volatile memory outputs a corresponding encoded read data to the controller according to each of the collection read operations. Then, the ECC circuit performs a decode operation on the encoded read data to generate a decoded content, and a first corresponding number of the decoded content is transmitted to a first register of the register set. After all the encoded read data is decoded, the value stored in the first register is a first parameter, and the first parameter is input to a prediction function in the function storage circuit.

Description

Solid-state storage device using predictive equation

The present invention relates to a solid-state storage device, and in particular to a solid-state storage device using predictive equations.

As we all know, Solid State Storage Device (SSD) has been widely used in various electronic products, such as SD cards, solid state drives, etc. The solid-state storage device includes a non-volatile memory (non-volatile memory). After the data is written to the non-volatile memory, once the power of the solid-state storage device is turned off, the data can still be stored in the non-volatile memory.

US Patent No. 9,922,706 discloses a solid-state storage device using a state prediction method. It uses a prediction function to predict the state of the non-volatile memory in the solid-state storage device at a future point in time, and predicts an appropriate decoding process or provides an appropriate read voltage.

Please refer to FIG. 1, which is a schematic diagram of a conventional solid-state storage device. The solid-state storage device 100 is connected to a host 110 via an external bus 115. The external bus 115 may be a USB bus, a SATA bus, a PCIe bus, an M.2 bus, or a U.2 bus, etc.

The solid-state storage device 100 includes a controller 120, a buffer 130, and a non-volatile memory 150. The controller 120 is connected to the non-volatile memory 150 and the buffer 130. The non-volatile memory 150 is composed of a plurality of dies 11-14, and these dies 11-14 can be NAND flash die. In addition, the buffer 130 may be a dynamic random access memory (DRAM).

The controller 120 further includes an error correction code circuit (ECC circuit) 124, an equation storage circuit 126, and a command queue 128. The command queue 128 may temporarily store a plurality of operation commands (operation commands), such as program operations, read operations, and erase operations. In addition, the controller 120 may transfer the operation instructions in the instruction queue 128 to the non-volatile memory 150.

For example, when the host 110 issues a write command and writes data, the controller 120 generates a program operation according to the write command and temporarily stores it in the command queue 128. Furthermore, the ECC circuit 124 performs an ECC encoding operation on the write data to become encoded write data and temporarily stores it in the buffer 130. Finally, the controller 120 transfers the programming operation and the encoded write data to the non-volatile memory 150, so that the encoded write data is stored in the non-volatile memory 150.

When the host 110 issues a read command, the controller 120 generates a read operation according to the read command and temporarily stores the read operation in the command queue 128. After the controller 120 transfers the read operation to the non-volatile memory 150, the non-volatile memory 150 transmits the encoded read data to the controller 120. Next, the ECC circuit 124 decodes the encoded read data to generate read data (read date) and temporarily stores it in the buffer 130. Finally, the read data is transferred to the host 110.

Basically, the controller 120 can store the encoded write data in the specific dies 11-14 using programming operations, or distribute the encoded write data in all the dies 11-14. In addition, the controller 120 may also use the reading operation to obtain the encoded reading data from the specific dies 11-14 or all the dies 11-14.

Of course, the controller 120 may also generate an erase operation at an appropriate timing and temporarily store it in the command queue 128. When the erase operation is transferred to the non-volatile memory 150, the data in the specific blocks in the specific dies 11-14 in the non-volatile memory 150 is erased, or the specific blocks in all the dies 11-14 The information inside is erased.

Generally speaking, after the solid-state storage device 100 is shipped from the factory and the non-volatile memory 150 has been programmed, read, and erased many times, the characteristics of the non-volatile memory 150 are deteriorated, which may cause data loss. At this time, the encoded read data obtained from the non-volatile memory 150 cannot pass the decoding operation, nor can it generate correct read data and pass it to the host, and cause read failure (read fail).

In order to prevent the solid-state storage device 100 from failing to read, a plurality of prediction functions are stored in the function storage circuit 126 in the controller 120. The prediction equation can predict the state of the non-volatile memory 150 after a period of time (for example, three days, one week, or one month) according to various parameters of the non-volatile memory 150. If the prediction equation determines that the state of the non-volatile memory 150 may affect the performance of the solid-state storage device 100 after a period of time in the future, the controller 120 may make corrections in advance. For example, modify the decoding process in the decoding action, modify the reading voltage, and move the data in the block that is predicted to be damaged to another block.

In other words, after the solid-state storage device 100 is shipped from the factory, during operation, the controller 120 continuously collects a plurality of parameters of each block in the non-volatile memory 150, and inputs these parameters into the prediction equation and obtains the corresponding forecast result. The parameters of the non-volatile memory 150 can be the number of error bits of the block, program time, erase time, and real-time decoding process (such as hard decoding or soft decoding) Process), the operating temperature of the non-volatile memory 150, read voltage shift, etc.

In order to collect the parameters of the non-volatile memory 150, the controller 120 will automatically generate a read operation and temporarily store it in the command queue 128. After the non-volatile memory 150 transfers the encoded read data to the controller 120 according to the read operation, the ECC circuit 124 performs a decoding operation on the encoded read data, and the decoding that occurs during the decoding operation The content is temporarily stored in the buffer 130. Furthermore, the controller 120 reads all the decoded contents in the buffer 130 and calculates the parameters required for the prediction equation. After that, the controller 120 inputs the calculated parameters into the prediction equation and obtains the corresponding prediction result. Basically, the decoding content may include, but is not limited to: the number of erroneous bits, programming time, erasing time, instant decoding process or operating temperature, etc.

Please refer to FIG. 2, which is a schematic diagram of a conventional command queue. The controller 120 can generate a corresponding host read operation (Host read operation) according to the read command of the host 110 and temporarily store it in the command queue 128. In addition, in order to collect the information of the non-volatile memory 150, the controller 120 may also generate a collection read operation (Collection read operation) and temporarily store it in the command queue 128.

Basically, the controller 120 does not sequentially transfer the read operation to the non-volatile memory 150. The controller 120 transfers the read operation to the non-volatile memory 150 in an out of order according to whether the dies 11-14 are busy. For example, when the die 11 is busy, the controller 120 does not transfer the read operation about the die 11 to the non-volatile memory 150. When the die 13 is not busy or idle, the controller 120 transfers the read operation about the die 13 from the command queue 128 to the non-volatile memory 150. Of course, the programming operation and the erasing operation can also be temporarily stored in the instruction queue 128.

The controller 120 transfers the read operation to the non-volatile memory 150 in an out of order manner. Therefore, the controller 120 must also distinguish whether the content returned by the non-volatile memory 150 is the encoded read data belonging to the host 110 or the encoded read data for collection. After performing the decoding operation and generating the read data, the read data requested by the host 100 can be transferred to the host 100.

Furthermore, the collected reading data does not need to be transferred to the host 100, and the controller 120 temporarily stores the decoded content that appears during the decoding operation in the buffer 130.

For example, assume that one block in the non-volatile memory 150 has 1024 pages, and each page has 4 ECC codewords. In order to collect the decoded content of a block, the controller 120 must generate 4096 (1024×4) collection read operations to the command queue 128 and pass them to the non-volatile memory 150 for reading 4096 ECC codes Word (ECC codeword). Furthermore, after the non-volatile memory 150 decodes each ECC codeword, 4 bytes of decoded content will be generated. In other words, the controller 120 receives 16384 (4096×4 byte) bytes of decoded content and temporarily stores it in the buffer 130.

Obviously, in order to predict the state of a block, the controller 120 needs to set a space of 16384 bytes in the buffer 130 to temporarily store the decoded content. If the controller 120 needs to predict the status of multiple blocks, it will occupy most of the buffer 130 space.

In addition, the controller 120 must also read all the decoded content in the buffer 130 multiple times and calculate the parameters required for the prediction equation. Therefore, the overall performance of the solid-state storage device 100 will decrease.

The present invention is a solid-state storage device, including: a non-volatile memory, including a plurality of dies; a buffer; a controller, connected to the non-volatile memory and the buffer, the controller includes an error correction A code circuit, a program storage circuit, a register group, and a command queue; wherein, the controller generates a plurality of read operations for collection, temporarily stores in the command queue, and passes it to the non-volatile memory; The non-volatile memory generates a corresponding coded reading data corresponding to each collection reading operation to the controller; wherein, the error correction code circuit performs a decoding operation on the coded reading data to generate a decoding Content, and a first corresponding number in the decoded content is transferred to a first register in the register group; wherein, when the encoded read data is decoded, the first register A stored value is a first parameter, and a predictive equation in the equation storage circuit is input.

In order to have a better understanding of the above and other aspects of the present invention, the embodiments are specifically described below and described in detail in conjunction with the accompanying drawings.

In order to improve the problem that the performance of the conventional solid-state storage device in order to calculate the parameters required for predicting the equation reduces the performance of the solid-state storage device, the present invention proposes a solid-state storage device that creates multiple setting fields in the reading operation to control the corresponding temporary The operation of the memory.

Please refer to FIG. 3, which is a schematic diagram of the solid-state storage device of the present invention. The solid-state storage device 300 is connected to the host 110 via an external bus 115. The external bus 115 may be a USB bus, a SATA bus, a PCIe bus, an M.2 bus, or a U.2 bus, etc.

The solid-state storage device 300 includes a controller 320, a buffer 130, and a non-volatile memory 150. The controller 320 is connected to the non-volatile memory 150 and the buffer 130. The non-volatile memory 150 is composed of a plurality of dies 11-14, and these dies 11-14 can be NAND flash die. In addition, the buffer 130 may be a dynamic random access memory (DRAM).

The controller 320 further includes a register set 330, an error correction code circuit (ECC circuit) 124, an equation storage circuit 126, and a command queue 328. The command queue 328 may temporarily store a plurality of operation commands (operation commands), such as program operations, read operations, and erase operations. In addition, the controller 320 may transfer the operation instructions in the instruction queue 328 to the non-volatile memory 150.

Similarly, when the host 110 issues a write command or a read command, the controller 320 may correspondingly generate a program operation or a read operation and temporarily store it in the command queue 328. The controller 320 may transfer the programming operation or the reading operation in the command queue 328 to the non-volatile memory 150. Its detailed operation will not be repeated here.

Basically, the controller 320 can store the encoded write data in the specific dies 11-14 by programming operations, or distribute the encoded write data in all the dies 11-14. In addition, the controller 320 may also use the reading operation to obtain the encoded reading data from the specific dies 11-14 or all the dies 11-14.

Of course, the controller 320 may also generate an erase operation at an appropriate timing and temporarily store it in the command queue 328. When the erase operation is transferred to the non-volatile memory 150, the data in the specific blocks in the specific dies 11-14 in the non-volatile memory 150 is erased, or the specific blocks in all the dies 11-14 The information inside is erased.

After the solid-state storage device 300 is shipped from the factory, during operation, the controller 320 will continuously collect multiple parameters of each block in the non-volatile memory 150, and input these parameters into the prediction equation and obtain the corresponding prediction result. The parameters of the non-volatile memory 150 can be the number of error bits of the block, program time, erase time, and real-time decoding process (such as hard decoding or soft decoding) Process), the operating temperature of the non-volatile memory 150, read voltage shift, etc.

According to an embodiment of the present invention, a plurality of setting fields are added to the read operation generated by the controller 320, and at least one register in the register group is used to continuously record the decoded content, and can also be paused or Reset the contents of the register.

Please refer to FIG. 4, which illustrates a first embodiment of the operation relationship between the read operation and the register in the command queue of the present invention. Basically, the controller 320 generates a corresponding host read operation (Host read operation) according to the read command of the host 110 and temporarily stores it in the command queue 328. In addition, in order to collect the information of the non-volatile memory 150, the controller 320 may also generate a collection read operation (Collection read operation) and temporarily store it in the command queue 328.

As shown in FIG. 4, the read operation generated by the controller 320 further includes two bits. One bit represents the reset enable field, and the other bit represents the collection enable ( collection enable) field. When the reset enable field and the collection enable field are set to "1", it means enable (enable); when the reset enable field and the collection enable field are set to "0", it means disable (disable ).

For example, if the controller 320 wants to use the error bit count of a particular block as a parameter of the non-volatile memory 150 and input the prediction equation, the controller can use the An accumulator resistor 330a is used to obtain the total number of error bits. The detailed operation process is described below.

Suppose a block in the non-volatile memory 150 has 1024 pages, and each page has 4 ECC codewords. In order to collect the total number of erroneous bits of a block, the controller 320 generates 4096 (1024×4) collection read operations to the command queue 328 and passes them to the non-volatile memory 150 for reading 4096 ECC Codeword (ECC codeword).

As shown in FIG. 4, the instruction queue 328 includes a read operation for collection and a read operation for the host. Among them, in the read operation for collection of index 1 (index 1), the reset enable field is set to "1" and the collect enable field is set to "1", which means that the accumulation register 330a is reset (reset) ), and start to accumulate error bits. Therefore, according to the reading operation of the index 1 for collection, after the ECC circuit decodes the ECC codeword returned from the non-volatile memory 150, its decoding content including 38 error bits will be recorded in The accumulation register 330a. At this time, the value recorded in the accumulation register 330a is 38.

In addition, in the read operation for collection of index 2 (index 2), the reset enable field is set to "0" and the collect enable field is set to "1", indicating that the accumulation register 330a will not be reset Set and continue to accumulate error bits. Therefore, according to the reading operation of the index 2 for collection, after the ECC circuit decodes the ECC codeword returned from the non-volatile memory 150, its decoding content includes 36 error bits, which are accumulated in The accumulation register 330a. At this time, the value recorded in the accumulation register 330a is 74.

In addition, in the index 3 (index 3) host read operation, the reset enable field is set to "0" and the collection enable field is set to "0", indicating that the accumulation register 330a will not be reset Will not accumulate error bits. Therefore, according to the read operation of the host at index 3, after the ECC circuit decodes the ECC codeword returned from the non-volatile memory 150, no matter how many error bits there are in the decoded content, it will not be accumulated in the accumulation In the temporary storage 330a. At this time, the value recorded in the accumulation register 330a is maintained at 74. In the same way, the subsequent index 4~6 hosts use the read operation, and the value recorded in the accumulation register 330a is also maintained at 74.

In addition, in the read operation for the collection of index 7 (index 7), the reset enable field is set to "0" and the collect enable field is set to "1", indicating that the accumulation register 330a will not be reset Set and continue to accumulate error bits. Therefore, according to the read operation of the index 7 for collection, after the ECC circuit decodes the ECC codeword returned from the non-volatile memory 150, the decoded content includes 31 error bits, which are accumulated in The accumulation register 330a. At this time, the value recorded in the accumulation register 330a is 105.

By analogy, after the 4096 collection read operations generated by the controller 320 are transferred from the command queue 328 to the non-volatile memory 150, the value recorded in the accumulation register 330a is the error bit of the block The total number of yuan. The controller 320 directly reads the value in the accumulation register 330a and inputs the prediction equation as a parameter of the prediction equation.

As shown in FIG. 5, it is a flowchart of parameter calculation of the first embodiment of the solid-state storage device of the present invention. First, the controller 320 starts after a specific time (step S502), which may be, for example, 10 hours, or one day. That is, after the solid-state storage device 300 is operated for 10 hours, the state of the non-volatile memory 150 is predicted using the prediction equation.

Next, multiple read operations for collection are generated, temporarily stored in the command queue, and transferred to the non-volatile memory 150 (step S504). Then, the non-volatile memory 150 returns the encoded read data corresponding to each collected read operation to the controller 320 (step S506).

Then, the ECC circuit 124 in the controller 320 decodes each encoded read data to generate a decoded content, and a first corresponding number of the decoded content is transferred to a first in the register group Scratchpad (step S508). As in the example of FIG. 4, the decoding content includes the number of error bits, and the number of error bits is transferred to the accumulation register 330a.

After that, after all the encoded read data are decoded, a value stored in the first register is a first parameter, and a predictive equation in the equation storage circuit is input (step S510). As shown in the example in FIG. 4, after all the error bits in the decoded content are transferred to the accumulation register 330a, the value recorded in the accumulation register 330a is the total number of error bits in the block. The controller 320 directly reads the value in the accumulation register 330a and inputs the prediction equation as a parameter of the prediction equation.

According to the above description, in the solid-state storage device 300 of the present invention, the controller 320 does not need to set a specific space in the buffer 130 to temporarily store the decoded content, nor does it need to read and calculate the decoded content in the buffer 130 The parameters of the prediction equation can be obtained. Therefore, the performance of the solid-state storage device 300 can be greatly improved.

The above parameters are described by taking the total number of error bits as an example, but the present invention is not limited to this. Using the same register control method, a register selection field can be added to the read operation to use the multiple registers in the register group 330 to collect various parameters.

Please refer to FIG. 6, which illustrates a second embodiment of the operation relationship between the read operation and the register in the command queue of the present invention. The read operation generated by the controller 320 further includes seven bits, one bit represents the reset enable field, one bit represents the collection enable field, and the other five Each bit is a register selection field (register selection) used to select a specific register in the register group 330.

For example, the register group 330 includes at least five registers, and each register can calculate different parameters according to the decoded content. As shown in Figure 6, register a can be used to calculate the total error bit count (error bit count), register b can be used to calculate the error bit variance (error bit variance), and register c can be used to calculate The total number of decoding failures (decide fail count), the register d can calculate the total busy time (busy time), and the register e can calculate the total number of ECC codewords (ECC codeword count).

It is assumed that the parameters to be input by the prediction equation selected by the controller 320 include the total number of erroneous bits, the number of erroneous bit variations, and the total number of ECC code words. Then, the controller 320 may set the register selection field in the reading operation to "11001". That is, the register a, the register b, and the register e are operated, and the register c and the register d are not operated. The detailed operation process is described below.

As shown in Figure 6, in the read operation for the collection of index 1 (index 1), the reset enable field is set to "1", the collect enable field is set to "1" and the register selection field Set to "11001". Therefore, the register a, the register b, and the register e operate. In addition, the register a, the register b, and the register e are reset, and the number of erroneous bits, the number of variability of the erroneous bits, and the number of ECC codewords are separately collected. In addition, the controller 320 may transfer the number of erroneous bits to the register a according to the decoded content, the variability of the error bit to the register b, and the number of ECC codewords to the register d.

In addition, in the read operation for collection of index 2 (index 1), the reset enable field is set to "0", the collect enable field is set to "1" and the register selection field is set to "11001" . Therefore, the register a, the register b, and the register e continue to collect the number of erroneous bits, the variability of the erroneous bits, and the number of ECC codewords.

In addition, in the read operation of the host for index 3~index 6 (index 3~index 6), the reset enable field is set to "0", the collection enable field is set to "0", and the register selection The field is set to "00000", which means that register a, register b and register e will not collect the corresponding number of erroneous bits, the number of erroneous bits and the number of ECC codewords.

Furthermore, in the read operation for the index 7 (index 7) collection, the reset enable field is set to "0", the collect enable field is set to "1" and the register selection field is set to "11001" ". Therefore, the register a, the register b, and the register e continue to collect the number of error bits, the number of variations of the error bits, and the number of ECC codewords.

By analogy, when the 4096 read operations generated by the controller 320 are transferred from the command queue 328 to the non-volatile memory 150, the value of the register a is the total number of error bits, and the register b The value of is the number of variations of the error bit, and the value of the register e is the total number of ECC codewords. In other words, the controller 320 directly reads the values of the register a, the register b, and the register e, and inputs the prediction equation as three parameters of the prediction equation.

In other words, the second embodiment can set multiple registers to receive multiple corresponding numbers in the decoded content, such as the number of error bits, the number of error bit errors, and the number of ECC codewords, and obtain the prediction equation Multiple parameters.

Of course, the above-mentioned second embodiment can also add a one-bit collection and end field (collection end), and become the third embodiment of the present invention. Please refer to FIG. 7, which illustrates a third embodiment of the operation relationship between the read operation and the register in the command queue of the present invention. Among them, when the collection end field is set ("1"), it means that the collection read operation is the last collection read operation. When the collection end field is not set ("0"), it means that the collection read operation is not the last collection read operation.

As shown in FIG. 7, assuming that the total number of erroneous bits of a block is collected, the controller 320 generates 4096 (1024×4) collection read operations to the instruction queue 328, and the last collection read operation is stored in Of the command queue 328 at index 5000. Therefore, for the collection operation at the index 5000 position, the collection end field is set to "1", and for the collection operation before the index 5000 position, the collection end field is set to "0".

According to the third embodiment of the present invention, when the read operation for collecting is set to "1" in the collecting end field and transferred to the non-volatile memory, the controller 320 will also be notified that the command queue 328 has passed 4096 Read operation for collection. At this time, the value of the register a is the total number of error bits, the value of the register b is the variation number of the error bit, and the value of the register e is the total number of ECC codewords. In other words, the controller 320 directly reads the values of the register a, the register b, and the register e, and inputs the prediction equation as three parameters of the prediction equation.

Using the same register control method, a group selection field can be added to the read operation to use the specific register group in the register group 330 to collect various types of specific die parameter.

Please refer to FIG. 8, which illustrates a fourth embodiment of the operation relationship between the read operation and the register in the command queue of the present invention. The read operation generated by the controller 320 further includes nine bits, one bit represents the reset enable field, one bit represents the collection enable field, and five The bit is a register selection field (register selection), and the other two bits are a group selection field (group selection), used to select a specific group of registers in the register group 330.

For example, the register group 330 includes twenty registers, five registers form a group, and there are four register groups in total. As shown in Figure 6, the (00) register group includes register a0, register b0, register c0, register d0, register e0; (01) register group Including the temporary register a1, temporary register b1, temporary register c1, temporary register d1, temporary register e1; the (10) temporary register group includes temporary register a2, temporary register b2, temporary register c2, register d2, register e2; the (11) register group includes register a3, register b3, register c3, register d3, register e3.

In addition, registers a0~a3 can be used to calculate the total error bit count (error bit count), registers b0~b3 can be used to calculate the error bit variance (error bit variance), temporary Register c0 ~ register c3 can be used to calculate the total number of decoding failure (decide fail count), register d0 ~ register d3 can calculate the total busy time (busy time), register e0 ~ register e3 The total number of ECC codewords can be calculated.

According to an embodiment of the present invention, the controller 320 may use different register groups to calculate parameters of different die. For example, the (00)th register group is used to collect the parameters of the die 11, the (11)th register group is used to collect the parameters of the die 12, and so on.

For example, the controller 320 selects the (10)th register group to collect the total number of erroneous bits, the number of erroneous bit variations, and the total number of ECC codewords for a specific block in a specific die. Therefore, the controller 320 sets the register selection field in the reading operation to "11001" and sets the group selection field to "10". That is, the register a2, the register b2, and the register e2 in the (10)th register group are operated, and the register c2 and the register d2 are not operated. The detailed operation process is described below.

With the same operation principle, in the index 1 (index 1), index 2 (index 1) and index 7 (index 7) of FIG. 7 are collected for reading operation, the controller 320 can determine the number of erroneous bits according to the decoded content It is transferred to the register a2, the variability of the error bit is transferred to the register b2, and the number of ECC codewords is transferred to the register e2.

In addition, in the read operation of the index 3~index 6 (index 3~index 6), the register a2, the register b2 and the register e2 will not collect the corresponding number of error bits and error bits The number of variations and the number of ECC codewords.

By analogy, after the 4096 collection read operations generated by the controller 320 are transferred from the command queue 328 to the non-volatile memory 150, the value of the register a2 is the total number of error bits, and the value of the register b2 The value is the number of variations of the error bit, and the value of the register e2 is the total number of ECC code words. In other words, the controller 320 directly reads the values of the register a2, the register b2, and the register e2, and inputs the prediction equation as three parameters of the prediction equation.

According to the above description, in the solid-state storage device 300 of the present invention, the controller 320 does not need to set a specific space in the buffer 130 to temporarily store the decoded content, nor does it need to read and calculate the decoded content in the buffer 130 The parameters of the prediction equation can be obtained. Therefore, the performance of the solid-state storage device 300 can be greatly improved.

In summary, although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be deemed as defined by the scope of the attached patent application.

11~14: grain 100, 300: solid state storage devices 110: host 115: External bus 120, 320: controller 124: ECC circuit 126: Equation storage circuit 128, 328: command queue 130: buffer 150: Non-volatile memory 330: register group

Figure 1 is a schematic diagram of a conventional solid-state storage device. Figure 2 is a schematic diagram of a conventional command queue. FIG. 3 is a schematic diagram of the solid-state storage device of the present invention. FIG. 4 is a first embodiment of the operation relationship between the read operation and the register in the command queue of the present invention. FIG. 5 is a flowchart of parameter calculation of the first embodiment of the solid-state storage device of the present invention. FIG. 6 is a second embodiment of the operation relationship between the read operation and the register in the command queue of the present invention. FIG. 7 is a third embodiment of the operation relationship between the read operation and the register in the command queue of the present invention. FIG. 8 is a fourth embodiment of the operation relationship between the read operation and the register in the command queue of the present invention.

11~14: grain

110: host

115: External bus

124: ECC circuit

126: Equation storage circuit

130: buffer

150: Non-volatile memory

300: solid state storage device

320: controller

328: Command Queue

330: register group

Claims (8)

A solid-state storage device, including: A non-volatile memory, including multiple grains; A buffer A controller connected to the non-volatile memory and the buffer, the controller includes an error correction code circuit, a program storage circuit, a register group and a command queue; Wherein, the controller generates a plurality of read operations for collection, temporarily stores them in the command queue, and transmits them to the non-volatile memory; the non-volatile memory generates a corresponding code according to each read operation of the collection The read data is transferred to the controller; Wherein, the error correction code circuit performs a decoding operation on the encoded read data to generate a decoded content, and a first corresponding number in the decoded content is transferred to a first register in the register group; After the encoded read data is decoded, a value stored in the first register is a first parameter, which is input into a prediction equation in the equation storage circuit. The solid-state storage device as described in item 1 of the patent application scope, wherein the read operation for collection includes a reset enable field and a collect enable field; when the reset enable field is enabled , The first register is reset; and, when the collection enable field is enabled, the first corresponding number is input to the first register. The solid-state storage device according to item 1 of the patent application scope, wherein the first corresponding number is the number of erroneous bits, the number of erroneous bits, the number of decoding failures, the total busy time, or the number of ECC codewords. The solid-state storage device as described in item 3 of the patent application scope, wherein the read operation for collecting further includes a register selection field, and the register selection field can select the first in the register group A temporary register and a second temporary register. The solid-state storage device as described in item 4 of the patent application scope, wherein the error correction code circuit performs decoding operation on the encoded read data to produce the decoded content, and the first corresponding number in the decoded content is passed to the The first register, and a second corresponding number is transferred to the second register. The solid-state storage device as described in item 4 of the patent application scope, wherein the read operation for collection further includes a group selection field, and the group selection field can select a first temporary storage in the register group The first register and a second register in the device group. The solid-state storage device as described in item 6 of the patent application range, wherein the error correction code circuit performs decoding operation on the encoded read data to produce the decoded content, and the first corresponding number in the decoded content is passed to the The first register, and a second corresponding number is transferred to the second register. The solid-state storage device as described in item 1 of the patent application scope, wherein the collection read operation includes a collection end column; of the collection read operations generated by the controller, the last collection read operation The collection end column is set; and, when the collection read operation set in the collection end column is transferred to the non-volatile memory, the controller is notified that the value stored in the first register is the The first parameter is used to input the prediction equation in the equation storage circuit.

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