TWI694458B - Single port static random access memory with fast write speed - Google Patents

Abstract

The present invention proposes a high-speed write-in port static random access memory, which mainly includes a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), and a standby start circuit (4 ), a plurality of word line voltage level conversion circuits (5), a plurality of high voltage level control circuits (6), and a plurality of write drive circuits (7), the memory array is composed of a plurality of rows of memory cells It consists of a plurality of rows of memory cells, each column of memory cells is provided with a control circuit (2), a word line voltage level conversion circuit (5), and a high voltage level control circuit (6), and each A row of memory cells is provided with a precharge circuit (3) and a write drive circuit (7), so that in the write mode, the plurality of control circuits (2) and the plurality of write drive circuits can be used (7) While effectively preventing the difficulty of writing logic 1, it also increases the speed of writing logic 0. In the reading mode, on the one hand, it is controlled by the plurality of control circuits (2) and the plurality of high voltage levels The circuit (6) can improve reading speed while avoiding unnecessary power consumption. On the other hand, the plurality of word line voltage level conversion circuits (5) can effectively reduce the semi-selected cell during reading Interference, in the standby mode, the leakage current can be effectively reduced by the plurality of control circuits (2), and the design of the standby start circuit (4) can be used to effectively promote Make the static random access memory enter standby mode quickly.

Description

High-speed write-on-port static random access memory

The invention relates to a static random access memory (SRAM) with high writing speed, especially a kind of effective improving SRAM standby performance, and can effectively improve reading speed and writing speed And can effectively reduce leakage current (leakage current), reduce half-selected cell interference during reading and avoid unnecessary power consumption of SRAM.

The conventional 6T static random access memory (SRAM) is shown in Figure 1a, which mainly includes a memory array (memory array), which is composed of a plurality of memory blocks (memory block, MB ₁ , MB ₂ etc.), each memory block is further composed of a plurality of rows of memory cells and a plurality of rows of memory cells, each A row of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word lines, WL ₁ , WL ₂ etc.), each word line corresponds to a plurality of rows of memory cells One row in the unit cell; and plural bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _m, etc.), each bit line pair corresponds to one of the plural row memory cells One row, and each bit line pair is composed of a bit line (BL ₁ ... BL _m ) and a complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b shows the circuit diagram of the 6T static random access memory (SRAM) cell. Among them, PMOS transistors (P1) and (P2) are called load transistors and NMOS transistors (M1). ) And (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is a word line, and BL and BLB These are the bit line and the complementary bit line, because the SRAM cell of this port requires 6 transistors, and when reading logic 0, in order to avoid the initial moment of the read operation (initial instant) The other driving transistor is turned on, and the initial instantaneous voltage (V _AR ) of node A must satisfy equation (1): V _AR = V _DD ×(R _M1 )/(R _M1 +R _M3 )<V _TM2 ( 1)

Where, V _AR represents the initial instantaneous voltage of node A, R _M1 and R _M3 respectively represent the on-resistance of the NMOS transistor (M1) and the NMOS transistor (M3), and V _DD and V _TM2 respectively represent the power supply Voltage and the threshold voltage of the NMOS transistor (M2), which results in the current driving capability ratio (ie cell ratio) between the driving transistor and the access transistor usually set between 2.2 and 3.5 (please refer to 98 Patent Specification No. US76060B2, October 20, 2010, column 2, lines 8-10).

Figure 1b shows the HSPICE transient analysis simulation results of the 6T static random access memory cell during the write operation. As shown in Figure 2, it is simulated using TSMC90 nanometer CMOS process parameters.

One way to reduce the number of transistors in the 6T static random access memory (SRAM) cell is shown in Figure 3. Figure 3 shows a circuit diagram of a 5T static random access memory cell with only a single bit line. Compared with the 6T static random access memory cell of Figure 1b, this 5T static random access memory The body cell has one transistor and one bit line less than the 6T static random access memory cell, but the 5T static random access memory cell does not change the PMOS transistors P1 and P2 and the NMOS transistor M1. In the case of the channel width-to-length ratio of M2 and M3 (that is, maintaining the same transistor channel width-to-length ratio as the 6T SRAM cell), there is a problem that writing logic 1 is quite difficult. Consider the case where the node A on the left side of the memory cell originally stores logic 0. Since the charge of node A is only transferred from the bit line (BL), the logic 0 previously written in node A is overwritten by the logic 1 write. The initial instantaneous voltage (V _AW ) is equal to equation (2): V _AW = V _DD × (R _M1 )/(R _M1 + R _M3 ) (2) where V _AW represents the initial instantaneous voltage of node A, R _M1 And RM ₃ represent the on-resistance of NMOS transistor (M1) and NMOS transistor (M3) respectively. Comparing equation (1) and equation (2), we can see that the initial instantaneous voltage (V _AW ) is less than NMOS transistor (M2) The threshold voltage (V _TM2 ) cannot complete the logic 1 write operation. The simulation results of the HSPICE transient analysis of the 5T static random access memory cell shown in Figure 3 during the write operation are shown in Figure 4, which are simulated using TSMC 90nm CMOS process parameters. The simulation results can confirm that the 5T static random access memory cell with a single bit line has a problem that it is quite difficult to write logic 1.

So far, many methods have been proposed to solve the difficulty of writing logic 1 in the static random access memory cell of FIG. 5T described above. The first method is to lower the voltage level supplied to the memory cell to It is lower than the power supply voltage (V _DD ) to facilitate the writing of logic 1 (assuming that node A originally stored logic 0, and now wants to write logic 1), by increasing the on-resistance of driving transistor NMOS transistor M1 During the writing operation, the driving transistor NMOS transistor M2 can be turned on to complete the operation of writing logic 1, such as the "Memory System" proposed in Patent Document 1 (April 27, 1999 No. US 7706203B2) , Patent Document 2 (TW I426514B, February 11, 103), "5T Static Random Access Memory for Reducing Power Supply Voltage during Write Operation" and Patent Document 3 (TW I534802B, May 21, 105 No.) proposed "semiconductor memory", etc., although it can effectively solve the difficulty of writing logic 1, but because these methods need to set up dual power supply and/or discharge path, and these methods must be supplied when writing The voltage level to the memory cell is pulled lower than the power supply voltage (V _DD ) and the voltage level supplied to the memory cell is restored to the power supply voltage (V _DD ) after writing is completed Will cause unnecessary power consumption.

The second method is to redesign the channel width-to-length ratio of PMOS transistors P1 and P2 and NMOS transistors M1, M2 and M3, such as Non-Patent Document 4 (Satyanand Nalam et al., "5T SRAM with asymmetric sizing for improved read stability ", IEEE Journal of Solid-State Circuits. , Vol . 46.No. 10, pp 2431-2442, Oct. 2011.), but because the channel width-to-length ratios of PMOS transistors P1 and P2 are different and NMOS transistor M1 The channel width and length ratios of M2 and M2 are different, so the static noise margin (SNM) will be reduced.

The third method is to increase the voltage level of the word line (WL) of the access transistor M3 gate supplied to the memory cell during writing to be higher than the power supply voltage (V _DD ) to facilitate writing logic At 1 (assuming that node A originally stored logic 0, and now wants to write logic 1), the drive transistor NMOS transistor M2 can be turned on at the initial moment of writing by reducing the on resistance of access transistor M3 The operation of writing logic 1, such as the "Port Static Random Access Memory that raises the voltage level of the word line during writing operation" proposed in Patent Document 5 (TW I404065B on August 1, 102), but Since the voltage level of the word line (WL) of the access transistor M3 gate supplied to the memory cell is increased during writing to be higher than the power supply voltage (V _DD ), it will increase the half of the writing time Selected cell disturbance (half-selected cell disturbance).

The fourth method is to increase the source voltage level of the driving transistor NMOS transistor M1 to be higher than the ground voltage during writing, so that when writing logic 1 (assuming that node A originally stored logic 0, and now wants to write Logic 1), by raising the level of the drain voltage of the driving transistor NMOS transistor M1, the driving transistor NMOS transistor M2 can be turned on at the initial moment of writing, and the end The operation of writing into logic 1, for example, "Public Static Random Access Memory with High Writing Speed" proposed in Patent Document 6 (TW I638364B on October 11, 107), Patent Document 7 (107 (No. TW I638365B on October 11)) "5T static random access memory with high write speed" and the "Write with high write" proposed in Patent Document 8 (No. TWI638355B on October 11, 107) "Speed of 5t static random access memory" and so on.

The fifth method is to increase the threshold voltage of the driving transistor NMOS transistor M1 and at the same time lower the threshold voltage of the access transistor M3 by using the back gate bias technology to write logic At 1 (assuming that node A originally stored logic 0 and now wants to write logic 1), by increasing the drain voltage level of the driving transistor NMOS transistor M1, the driving transistor NMOS can be enabled at the initial moment of writing The crystal M2 is turned on, and the operation of writing logic 1 is completed, but this method requires the use of a split well, which increases the complexity of the process and is therefore less used.

The sixth method is to redesign the connection relationship between PMOS transistors P1 and P2 and NMOS transistors M1, M2 and M3, such as Non-Patent Document 9 (Chua-Chin Wang et al., "A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40 nm process", 2014 International Symposium on Circuits and Systems, pp 1126-1129, June 2014.) and Non-Patent Document 10 (Shyam Akashe et al., "High density and low "Leakage current based 5T SRAM cell using 45 nm technology", 2011 International Conference on Nanoscience, Engineering and Technology (ICONSET), pp 346-350, Nov. 2011.) and so on.

Although the above-mentioned techniques can effectively solve the problem of writing logic 1 difficult, but these techniques have not considered how to increase the speed of writing logic 0, of which Patent Literature 6 to Patent Literature 8 consider the writing When logic 1, design the write drive circuit that raises the bit line voltage level to be higher than the power supply voltage, to effectively prevent the difficulty of writing logic 1, and also effectively increase the speed of writing logic 1, but none Considering how to increase the speed of writing logic 0, for example, have not tested Considering that when writing logic 0, the bit line voltage level is lowered below the ground voltage to effectively increase the speed of writing logic 0, so there is still room for improvement.

In view of this, the main purpose of the present invention is to propose a high-speed write-port static random access memory, which can be designed by writing a bit line voltage level below the ground voltage write Drive circuit to effectively increase the speed of writing logic 0.

The secondary object of the present invention is to propose a high-speed write-on-port static random access memory, which can effectively reduce reading by a word line voltage level conversion circuit and a high voltage level control circuit At the same time, the selected cell interference can also effectively improve the reading speed.

Another object of the present invention is to provide a high-speed write-on-port static random access memory, which can effectively increase the reading speed by the control circuit, and can be improved by two-stage reading control While reading speed, it also avoids unnecessary power consumption.

The present invention proposes a high-speed write-in port static random access memory, which mainly includes a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), and a standby start circuit (4 ), a plurality of word line voltage level conversion circuits (5), a plurality of high voltage level control circuits (6), and a plurality of write drive circuits (7), the memory array is composed of a plurality of rows of memory cells It consists of a plurality of rows of memory cells, each column of memory cells is provided with a control circuit (2), a word line voltage level conversion circuit (5), and a high voltage level control circuit (6), and each A row of memory cells is provided with a precharge circuit (3) and a write drive circuit (7), so that in the write mode, the plurality of control circuits (2) and the plurality of write drive circuits can be used (7) While effectively preventing the difficulty of writing logic 1, It also increases the speed of writing logic 0. In the reading mode, on the one hand, the plurality of control circuits (2) and the plurality of high-voltage level control circuits (6) are used to increase the reading speed while also To avoid unnecessary power consumption, on the other hand, the multiple word line voltage level conversion circuits (5) are used to effectively reduce the interference of the semi-selected cell during reading, and can be controlled by the multiple in standby mode The circuit (2) can effectively reduce the leakage current, and the design of the standby start circuit (4) can effectively promote the static random access memory to quickly enter the standby mode.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧ Standby start circuit

5‧‧‧Character line voltage level conversion circuit

6‧‧‧High voltage level control circuit

7‧‧‧Write driver circuit

P11‧‧‧The first PMOS transistor

P12‧‧‧ Second PMOS transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧ Third NMOS transistor

A‧‧‧storage node

B‧‧‧Inverted storage node

BL‧‧‧bit line

WLC‧‧‧Character line control signal

V _DD ‧‧‧ Power supply voltage

VH‧‧‧High voltage node

VL1‧‧‧The first low voltage node

VL2‧‧‧second low voltage node

S‧‧‧Standby mode control signal

/S‧‧‧Inverted standby mode control signal

M21‧‧‧ Fourth NMOS transistor

M22‧‧‧Fifth NMOS transistor

M23‧‧‧Sixth NMOS transistor

M24‧‧‧NMOS transistor

M25‧‧‧Eighth NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧Tenth NMOS transistor

P21‧‧‧The third PMOS transistor

RC‧‧‧Read control signal

RGND‧‧‧Accelerated reading voltage

/RC‧‧‧Reverse read control signal

/WC‧‧‧Inverse write control signal

INV‧‧‧ third inverter

D1‧‧‧ First delay circuit

P31‧‧‧The fourth PMOS transistor

P‧‧‧Precharge signal

M41‧‧‧Eleventh NMOS transistor

P41‧‧‧ fifth PMOS transistor

C‧‧‧Node

D2‧‧‧second delay circuit

WL‧‧‧character line

R‧‧‧Read signal

P51‧‧‧Sixth PMOS transistor

M51‧‧‧Twelfth NMOS transistor

M52‧‧‧Thirteenth NMOS transistor

P61‧‧‧The seventh PMOS transistor

P62‧‧‧Eighth PMOS transistor

I63‧‧‧ fourth inverter

V _{DDH1 ‧‧‧The} highest power supply voltage

V _{DDH2 ‧‧‧The} second highest power supply voltage

P71‧‧‧Ninth PMOS transistor

M71‧‧‧14th NMOS transistor

M72‧‧‧The fifteenth NMOS transistor

M73‧‧‧Sixteenth NMOS transistor

I71‧‧‧fifth inverter

I72‧‧‧ sixth inverter

Cap‧‧‧Capacitor

Din‧‧‧Enter data

D3‧‧‧The third delay circuit

D4‧‧‧ Fourth Delay Circuit

Y‧‧‧Line decoder output signal

BLB ₁ ^… BLB _m ‧‧‧ complementary bit line

BLB‧‧‧Complementary bit line

MB ₁ ^… MB _k ‧‧‧ memory block

WL ₁ ^… WL _n ‧‧‧ character line

BL ₁ ^… BL _m ‧‧‧ bit line

I ₁ , I ₂ , I ₃ ‧‧‧ leakage current

M1 ^… M4‧‧‧‧NMOS transistor

P1 ^… P2‧‧‧PMOS transistor

Figure 1a shows the conventional static random access memory; Figure 1b shows the schematic circuit diagram of the conventional 6T static random access memory cell; Figure 2 shows the conventional 6T static random access memory cell Figure 3 is a circuit diagram of the conventional 5T static random access memory cell; Figure 4 is a circuit diagram of the conventional 5T static random access memory cell; Figure 5 is a schematic circuit diagram of the preferred embodiment of the present invention; Figure 6 is a simplified circuit diagram of the preferred embodiment of the present invention during the writing of logic 0 in Figure 5; Figure 7 is a schematic diagram of Figure 5 The simplified circuit diagram of the preferred embodiment of the present invention during reading; Figure 8 is a simplified circuit diagram of the preferred embodiment of the present invention of Figure 5 during standby.

According to the above main object, the present invention provides a high-speed static random access memory with a port, which mainly includes a memory array composed of a plurality of rows of memory cells and a plurality of rows of memory Each unit of memory cells and each row of memory cells includes a plurality of memory cells (1); a plurality of control circuits (2), each The column memory cell is provided with a control circuit (2); a plurality of precharge circuits (3), each row of memory cells is provided with a precharge circuit (3); a standby start circuit (4), the standby start circuit (4) It prompts SRAM to enter standby mode quickly to effectively improve the standby performance of SRAM; a plurality of word line voltage level conversion circuits (5), each column of memory cells is provided with a word line voltage level conversion circuit (5); A plurality of high voltage level control circuits (6), each row of memory cells is provided with a high voltage level control circuit (6); and a plurality of write drive circuits (7), each row of memory cells is provided with a write Into the drive circuit (7).

For ease of explanation, the static random access memory shown in Figure 5 only has a memory cell (1), a word line (WL), a bit line (BL), and a control circuit (2 ), a precharge circuit (3), a standby start circuit (4) and a word line voltage level conversion circuit (5), a high voltage level control circuit (6) and a write drive circuit (7) As an example. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11), and a second inverter (composed of a second PMOS transistor Crystal P12 and a second NMOS transistor M12) and a third NMOS transistor (M13), wherein the first inverter and the second inverter are connected by mutual coupling, that is, the first The output of the inverter (ie, node A) is connected to the input of the second inverter, and the output of the second inverter (ie, node B) is connected to the input of the first inverter, and the first The output of the inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store the inverted data of the SRAM cell. It is worth noting here that the first NMOS transistor (M11) and the second NMOS transistor (M12) have the same channel width-to-length ratio, and the first PMOS transistor (P11) and the second PMOS transistor (P12) also has the same channel width to length ratio.

Please refer to FIG. 5 again. The control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), a standby mode control signal (S), and It consists of an inverse standby mode control signal (/S). The source, gate, and drain of the fourth NMOS transistor (M21) are connected to the ground voltage, the reverse standby mode control signal (/S), and a second low voltage node (VL2); the fifth The source, gate and drain of the NMOS transistor (M22) are connected to the second low voltage node (VL2), the standby mode control signal (S) and a first low voltage node (VL1); the first The source of the six NMOS transistors (M23) is connected to the ground voltage, and the gate and the drain are connected together and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) , The gate and the drain are connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the first low voltage node (VL1); the eighth NMOS transistor (M25) ) Source, gate and drain are connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1) and the source of the seventh NMOS transistor (M24); the first The delay circuit (D1) is connected between the output of the third inverter (INV) and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV) is for receiving the Read the control signal (RC), and the output is connected to the input of the first delay circuit (D1); the source, gate, and drain of the ninth NMOS transistor (M26) are connected to the ground voltage, the The drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); the source and gate of the tenth NMOS transistor (M27) The pole and the drain are respectively connected to the standby mode control signal (S), the write control signal (WC) and the gate of the ninth NMOS transistor (M26); and the third PMOS transistor (P21) The source, gate, and drain are connected to the inverted standby mode control signal (/S), the write control signal (WC), and the drain of the tenth NMOS transistor (M27), respectively. It is worth noting here that the inverted standby mode control signal (/S) is obtained from the standby mode control signal (S) through an inverter.

Among them, the drain of the third PMOS transistor (P21), the drain of the tenth NMOS transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected together to form a node (C ), when the write control signal (WC) is a logic low level, the voltage level of the node (C) is the logic voltage level of the inverse standby mode control signal (/S), and when the write control When the signal (WC) is a logic high level, the voltage level of the node (C) is the logic voltage level of the standby mode control signal (S), thereby effectively preventing the occurrence of unintended factors in the standby mode Written by mistake.

The control circuit (2) is designed to control the voltage levels of the first low-voltage node (VL1) and the second low-voltage node (VL2) according to different operation modes. The source voltage (i.e., the first low voltage node VL1) of the driving transistor (i.e., the first NMOS transistor M11) closer to the bit line (BL) is set to a predetermined voltage (i.e., higher than the ground voltage) The gate-source voltage V _{GS(M23) of} the sixth NMOS transistor (M23) and the source voltage of the other driving transistor (that is, the second NMOS transistor M12) in the selected cell (that is, the second The low-voltage node VL2) is set to the ground voltage in order to prevent the problem of difficulty in writing logic 1.

At the first stage of the read mode, the source voltage of the driving transistor (ie, the first NMOS transistor M11) in the unit cell closer to the bit line (BL) is selected (ie, the first low voltage The node VL1) is set to the accelerated read voltage (RGND) that is lower than the ground voltage. The accelerated read voltage (RGND) that is lower than the ground voltage can effectively improve the reading speed. In the second stage, the source voltage of the driving transistor (ie, the first NMOS transistor M11) in the selected cell closer to the bit line (BL) is set back to the ground voltage, so as to reduce unnecessary power consumption, where the read The time between the second phase and the first phase of the fetch mode is equal to the read control signal (RC) changing from a logic low level to a logic high level, and to the gate of the eighth NMOS transistor (M25) The pole voltage is sufficient to turn off the eighth NMOS transistor (M25). The value can be determined by the falling delay time of the third inverter (INV) and the delay time provided by the first delay circuit (D1) Adjustment.

In the standby mode, the source voltage of the driving transistors in all memory cells is set to the predetermined voltage higher than the ground voltage in order to reduce the leakage current; in the hold mode, the driving power in the memory cells is set The source voltage of the crystal is set to the ground voltage in order to maintain the original retention characteristics. Its detailed working voltage level is shown in Table 1.

The write control signal (WC) in Table 1 is the result of the AND gate operation of a write signal (W) and the word line (WL) signal, at this time only the write signal (W) When the signal and the word line (WL) signal are at a logic high level, the write control signal (WC) is a logic high level; the read control signal (RC) is a read signal (R) and the character WL signal and gate operation result. It is worth noting here that for the non-read mode, the read control signal (RC) is set to the level of the accelerated read voltage (RGND) to prevent leakage of the seventh NMOS transistor (M24) Current.

Please refer to FIG. 5, the precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P), the source and gate of the fourth PMOS transistor (P31) And the drain are connected to the power supply voltage (V _DD ), the precharge signal (P) and the bit line (BL), respectively, so that during the precharge period, the precharge signal (P ) To pre-charge the bit line (BL) to the level of the power supply voltage (V _DD ).

Please refer to FIG. 5 again, the standby start circuit (4) is composed of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2) and the inverting standby Mode control signal (/S). The source, gate, and drain of the fifth PMOS transistor (P41) are connected to the power supply voltage (VDD), the inverted standby mode control signal (/S), and the eleventh NMOS transistor ( M41) drain; the source, gate and drain of the eleventh NMOS transistor (M41) are connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) and The drain of the fifth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/S), and the output of the second delay circuit (D2) is connected To the gate of the eleventh NMOS transistor (M41).

Please refer to Figure 5 again, the word line voltage level conversion circuit (5) is composed of a Six PMOS transistors (P51), a twelfth NMOS transistor (M51), a thirteenth NMOS transistor (M52), the read control signal (RC), and an inverted write control signal (/WC) , An inverted read control signal (/RC) and a word line control signal (WLC). The source, gate, and drain of the sixth PMOS transistor (P51) are connected to the word line (WL), the inverted write control signal (/WC), and the word line control signal (WLC, respectively) ); the source, gate and drain of the twelfth NMOS transistor (M51) are connected to the word line control signal (WLC), the read control signal (RC) and the word line (WL) respectively ); and the source, gate and drain of the thirteenth NMOS transistor (M52) are connected to the word line control signal (WLC), the inverse read control signal (/RC) and the word respectively Yuan Line (WL).

The detailed working voltage level of the word line voltage level conversion circuit (5) is shown in Table 2.

其中V_TM51表示該第十二NMOS電晶體(M51)之臨界電壓。在此值得注意的是，本發明一方面藉由二階段的讀取控制以於提高讀取速度的同時，亦避免無謂的功率耗損，另一方面藉由該字元線電壓位準轉換電路(5)，以於讀取操作期間將施加至選定晶胞之存取電晶體的字元線電壓下拉至低於 該電源供應電壓(即V_DD-V_TM51)，以有效降低讀取時之半選定晶胞干擾。

Where V _TM51 represents the threshold voltage of the twelfth NMOS transistor (M51). It is worth noting here that on the one hand, the invention uses two-stage reading control to improve the reading speed while avoiding unnecessary power consumption; on the other hand, the word line voltage level conversion circuit ( 5), during the reading operation, the word line voltage applied to the access transistor of the selected cell is _pulled below the power supply voltage (ie, V _DD -V _TM51 ) to effectively reduce the reading half Selected cell interference.

Please refer to FIG. 5 again, the high-voltage level control circuit (6) is composed of a seventh PMOS transistor (P61), an eighth PMOS transistor (P62), a fourth inverter (I63), the reading It is composed of a control signal (RC) and a first high power supply voltage (V _DDH1 ), wherein the source, gate and drain of the seventh PMOS transistor (P61) are connected to the power supply voltage (V _DD ), the read control signal (RC) and a high voltage node (VH), the source, gate and drain of the eighth PMOS transistor (P62) are connected to the first high power supply voltage ( V _DDH1 ), the output of the fourth inverter (I63) and the high voltage node (VH), and the input of the fourth inverter (I63) is for receiving the read control signal (RC) and output It is connected to the gate of the eighth PMOS transistor (P62). It is worth noting here that the first inverter is connected between the power supply voltage (V _DD ) and the first low voltage node (VL1), and the second inverter is connected to the high voltage Between the node (VH) and the second low voltage node (VL2).

Please refer to FIG. 5 again, the write drive circuit (7) is composed of a ninth PMOS transistor (P71), a fourteenth NMOS transistor (M71), a fifteenth NMOS transistor (M72), a Sixteenth NMOS transistor (M73), a fifth inverter (I71), a sixth inverter (I72), a capacitor (Cap), an input data (Din), a row of decoder output signals (Y ), a third delay circuit (D3), a fourth delay circuit (D4) and a second high power supply voltage (V _DDH2 ), wherein the source and gate of the ninth PMOS transistor (P71) And the drain are respectively connected to the second highest power supply voltage (V _DDH2 ), the output of the fifth inverter (I71) and the drain of the fourteenth NMOS transistor (M71), the fourteenth NMOS The source, gate and drain of the transistor (M71) are respectively connected to the drain of the sixteenth NMOS transistor (M73), the output of the fifth inverter (I71) and the ninth PMOS transistor (P71) drain, the source, gate and drain of the fifteenth NMOS transistor (M72) are connected to the ground voltage, the output of the third delay circuit (D3) and the ninth PMOS The drain of the crystal (P71), the source, gate and drain of the sixteenth NMOS transistor (M73) are connected to the ground voltage, the output of the sixth inverter (I72) and the tenth The source of the four NMOS transistors (M71), the input of the fifth inverter (I71) is used to receive the input data (Din), and the output is connected to the gate of the ninth PMOS transistor (P71), The gate of the fourteenth NMOS transistor (M71) and the input of the third delay circuit (D3), the input of the sixth inverter (I72) are used to receive the output signal (Y) of the row decoder, and The output is connected to the input of the fourth delay circuit (D4) and the gate of the sixteenth NMOS transistor (M73), and one end of the capacitor (Cap) is connected to the output of the fourth delay circuit (D4), The other end of the capacitor (Cap) is connected to the source of the fourteenth NMOS transistor (M71) and the drain of the sixteenth NMOS transistor (M73), wherein the ninth PMOS transistor (P71) ), the drain of the fourteenth NMOS transistor (M71) and the drain of the fifteenth NMOS transistor (M72) are connected to the bit line (BL), the bit line (BL ) The first stage of writing logic 0 is designed to be at a voltage level lower than the ground voltage to speed up the writing of logic 0, while writing logic 1 is designed to be higher than the power supply voltage ( V _DD ) the level of the second highest power supply voltage (V _DDH2 ) to accelerate the speed of writing logic 1.

Whether the write drive circuit (7) is enabled or not is determined by the logic level of the row decoder output signal (Y). When the row decoder output signal (Y) is a logic low level, the write drive circuit (7) 7) It is in the disabled state, and when the output signal (Y) of the row decoder is at a logic high level, the write drive circuit (7) is in the enabled state. When the output signal (Y) of the row of decoders is at a logic low level, the output of the sixth inverter (I72) is at a logic high level, on the one hand turning on the sixteenth NMOS transistor (M73), and on the other hand passing the After the delay time provided by the fourth delay circuit (D4) charges one end of the capacitor (Cap), the sixteenth NMOS transistor (M73) is turned on, so that the other end of the capacitor (Cap) is the ground voltage , And one end of the capacitor (Cap) will maintain the voltage level of the power supply voltage (V _DD ) due to the charging of the capacitor (Cap).

The write drive circuit (7) uses a two-stage operation when writing to the logic 0 enable state. In the first stage of the write drive circuit (7) enabling, the row decoder of the logic high level outputs a signal (Y), so that the output of the sixth inverter (I72) is a logic low level, on the one hand, the sixteenth NMOS transistor (M73) is turned off (OFF) state, on the other hand, through the fourth delay circuit (D4) After the delay time provided, one end of the capacitor (Cap) is quickly discharged to the ground voltage. Since the input data (Din) is at a logic low level at this time, the output of the fifth inverter (I71) Is a logic high level, so the 14th NMOS transistor (M71) is turned on, and the 9th PMOS transistor (P71) is turned off, so the voltage level of the bit line (BL) is at this level The write drive circuit (7) satisfies equation (3) when writing the first stage of logic 0: V _BL1 =-V _DD ×Cap/(Cap+C _BL ) (3)

Where, V _BL1 represents the voltage level of the bit line (BL) at the first stage of writing logic 0, and the absolute value of V _BL1 is designed to be less than the threshold voltage of the third NMOS transistor (M13), for example, it can be designed Is -100mV, -150mV or -200mV, V _{DD is} the voltage level of the power supply voltage (V _DD ), and Cap and C _BL represent the capacitance value of the capacitor (Cap) and the bit line (BL), respectively The parasitic capacitance value.

When the input data (Din) of the logic low level passes the delay time provided by the fifth inverter (I71) and the third delay circuit (D3), the write drive circuit (7) enters the enabled In the second stage, since the fifteenth NMOS transistor (M72) is in the on state, the voltage level of the bit line (BL) is at the second stage of writing a logic 0 in the write driver circuit (7) Satisfy equation (4): V _BL2 =0 (4)

Where, V _BL2 represents the voltage level of the bit line (BL) in the second stage of writing logic 0.

The working mode of the port SRAM is described below. The working principle of the preferred embodiment of the present invention shown in FIG. 5 is as follows:

(I) write mode

Before the write operation starts, the write control signal (WC) is at a logic low level, so that the third PMOS transistor (P21) is turned on (ON), and the tenth NMOS transistor (M27) is turned off (OFF) Since the inverted standby mode control signal (/S) is at a logic high level at this time, the drain of the third PMOS transistor (P21) is at a logic high level, and the third PMOS transistor at the logic high level ( The drain of P21) turns on the ninth NMOS transistor (M26) and makes the first low voltage node (VL1) assume a ground voltage.

During the write operation period, the write control signal (WC) is at a logic high level, so that the tenth NMOS transistor (M27) is turned on, and the node C assumes a ground voltage (due to the standby mode control signal at this time) (S) is the logic low level of the ground voltage), so that the ninth NMOS transistor (M26) is turned off, and the first low voltage node (VL1) is equal to the gate source of the sixth NMOS transistor (M23) The voltage V _GS(M26) can effectively prevent the problem of writing logic 1 difficult.

Next, according to the four write states of the port SRAM, the invention of FIG. 5 will be explained. How the preferred embodiment completes the write action.

(1) Node A originally stored logic 0, but now wants to write logic 0:

Before the write operation occurs (the word line control signal WLC is a ground voltage), the first NMOS transistor (M11) is turned on. Since the first NMOS transistor (M11) is ON, when the writing operation starts, the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ). When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13) (ie, access transistor), the third NMOS transistor (M13) changes from OFF to OFF On, at this time, because the first NMOS transistor (M11) is on, the voltage level of the node A is at the first stage of writing logic 0, although it will be less than the ground voltage due to equation (3) However, during the second phase of writing logic 0, the node A will return to the original ground voltage due to equation (4) until the end of the write cycle.

(2) Node A originally stored logic 0, but now wants to write logic 1:

Before the write operation occurs (the word line control signal WLC is a ground voltage), the first NMOS transistor (M11) is turned on. Because the first NMOS transistor (M11) is ON, when the writing operation starts, the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ), the node A The voltage of will rise following the voltage of the word line control signal (WLC).

When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from OFF to ON. Because the bit line (BL) is the voltage level of the second highest power supply voltage (V _DDH2 ), and because the first NMOS transistor (M11) is still ON and the node B is at a voltage level close to The initial state of the voltage level of the power supply voltage (V _DD ), so the first PMOS transistor (P11) is still OFF, and the initial writing instantaneous voltage (V _AWI1 ) of the node A satisfies the equation ( 5): V _AWI1 =V _DDH2 ×(R _M11 +R _M23 )/(R _M13 +R _M11 +R _M23 )>V _TM12 (5)

V _AWI1 represents the initial instantaneous voltage of node A written from logic 0 to logic 1, R _M11 , R _M13 and R _M23 represent the first NMOS transistor (M11), the third NMOS transistor (M13) and the The on-resistance of the sixth NMOS transistor (M23), and V _DDH2 and V _TM12 represent the second highest power supply voltage (V _DDH2 ) and the threshold voltage of the second NMOS transistor (M12) respectively, due to the second highest The voltage level of the power supply voltage (V _DDH2 ) is designed to be higher than the voltage level of the power supply voltage (V _DD ), and a voltage equal to the sixth NMOS transistor is provided at the first low voltage node (VL1) (M23) gate-source voltage V _GS(M23) voltage level, so the voltage level of node A can be easily set to be higher than that of the conventional 5T static random access memory cell of FIG. 4 The voltage level of node A is much higher. The much higher divided voltage level is sufficient to turn on the second NMOS transistor (M12), so that the node B discharges to a lower voltage level, and the lower voltage level of the node B causes the first The on-resistance (R _M11 ) of an NMOS transistor (M11) exhibits a higher resistance value, the higher resistance value of the first NMOS transistor (M11) will obtain a higher voltage level at the node A, the The higher voltage level of node A will pass through the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B exhibits a lower voltage level, the node The lower voltage level of B will pass through the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level, and the cycle , The node A can be charged to the power supply voltage (V _DD ), and the logic 1 write operation is completed.

It is worth noting here that the first low-voltage node (VL1) originally stores logic 0 at node A, and the period of writing logic 1 has a gate-source voltage V equal to the sixth NMOS transistor (M23) The voltage level of _{GS (M23)} , after writing logic 1, will have the level of ground voltage due to the discharge through the ninth NMOS transistor (M26).

(3) Node A originally stored logic 1, but now wants to write logic 1:

Before the write operation occurs (the word line control signal WLC is the ground voltage), the first PMOS transistor (P11) is turned on. When the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ), since the node A is the voltage level of the power supply voltage (V _DD ), and the bit line (BL) is the voltage level of the second highest power supply voltage (V _DDH2 ), so the third NMOS transistor (M13) will continue to be kept in the OFF state; at this time, because the first PMOS transistor ( P11) is still ON, although the voltage level of the node A will be slightly higher than the power supply voltage (V _DD ) due to the voltage level of the second highest power supply voltage (V _DDH2 ), but After the writing is completed, the node A will return to the original voltage level of the power supply voltage (V _DD ).

(4) Node A originally stored logic 1, but now wants to write logic 0:

Before the write operation occurs (the word line control signal WLC is the ground voltage), the first PMOS transistor (P11) is turned on. When the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the word line control signal (WLC) is greater than that of the third NMOS transistor (M13) At a critical voltage, the third NMOS transistor (M13) changes from OFF to ON, because the voltage level of the bit line (BL) is the voltage level that satisfies equation (3) ( V _BL1 ), which is less than 0V, and because the first PMOS transistor (P11) is still ON and the node B is in an initial state where the voltage level is close to the voltage level of the ground voltage, the first NMOS power The crystal (M11) is still off, and the initial instantaneous voltage (V _AWI0 ) of the node A satisfies equation (6): V _AWI0 =V _BL1 ×R _P11 /(R _M13 +R _P11 )+V _DD ×R _M13 /(R _M13 +R _P11 ) (6)

V _AWI0 represents the initial instantaneous voltage of node A written to logic 0 by logic 1, R _M13 and R _P11 represent the on-resistance of the third NMOS transistor (M13) and the first PMOS transistor (P11), and V _BL1 and V _DD represent the voltage level of the bit line (BL) at the first stage of writing logic 0 and the voltage level of the power supply voltage (V _DD ), respectively, because when logic 1 is written to logic 0 , The third NMOS transistor (M13) works in the saturation region, and the current in the saturation region is proportional to the square of its gate-source voltage V _{GS (M13)} voltage level minus its critical voltage, so by The design method that the voltage level of the bit line (BL) at the first stage of writing logic 0 (V _BL1 ) is less than 0V can effectively speed up the speed of writing logic 0 from logic 1, and FIG. 6 is the invention The simplified circuit diagram of Figure 5 of the preferred embodiment during the writing of logic 0 is indicated.

(II) Read mode

Before the start of the read operation, the write control signal (WC) is at a logic low level, and the inverted standby mode control signal (/S) is at a logic high level, so that the node C assumes a logic high level, which is the logic high level The node C turns on the ninth NMOS transistor (M26), and makes the first low voltage node (VL1) assume a ground voltage. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned on (ON).

It is worth noting here that during the precharge period before the start of the read operation, the precharge signal (P) is at a logic low level, thereby precharging the corresponding bit line (BL) to the power supply Voltage (V _DD ) level, but because the operating voltage of process technology such as below 10 nanometers will be reduced to below 0.9 volts, the reading speed will be reduced and it will not meet the specifications. Therefore, the present invention proposes a two-stage reading Take control to improve the reading speed and meet the specifications, while avoiding unnecessary power consumption.

The preferred embodiment of the present invention shown in FIG. 5 uses two-stage reading control to improve the reading speed while avoiding unnecessary power consumption. In the first stage of the reading operation, the reading The control signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the first low voltage node (VL1) is approximately The accelerated read voltage (RGND) with a low ground voltage, and the accelerated read voltage (RGND) with a lower ground voltage can effectively improve the reading speed.

In the second stage of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still turned on, but due to the eighth NMOS transistor at this time (M25) is turned off, so that the first low voltage node (VL1) assumes a ground voltage through the turned-on ninth NMOS transistor (M26), thereby effectively reducing unnecessary power consumption. It is worth noting here that the time between the second phase and the first phase of the read operation is equal to the read control signal (RC) changing from a logic low level to a logic high level, and to the first The gate voltage of the eight NMOS transistors (M25) is sufficient to turn off the eighth NMOS transistor (M25). The value can be determined by the falling delay time of the third inverter (INV) and the first delay circuit (D1) Adjust the delay time provided. Furthermore, regardless of whether the first stage or the second stage of the read operation, the ninth NMOS transistor (M26) is turned on (because the gate of the ninth NMOS transistor (M26) is at a logic high level ). FIG. 7 is a simplified circuit diagram of the preferred embodiment of the present invention of FIG. 5 during reading.

Next, the invention according to FIG. 7 will be explained according to the two reading states of the port SRAM How does the preferred embodiment use the control circuit (2) and the high-voltage level control circuit (6) to increase the reading speed while avoiding unnecessary power consumption; on the other hand, by the word line voltage level conversion The circuit (5) effectively reduces the interference of the half-selected cell during reading.

(1) Read logic 1 (node A stores logic 1):

Before the read operation occurs, the first NMOS transistor (M11) is turned off (OFF) and the second NMOS transistor (M12) is turned on (ON), the node A and the node B are respectively the power supply voltage (V _DD ) and the ground voltage, and the bit line (BL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). During the reading period, since the word line control signal (WLC) is the power supply voltage _deducting the threshold voltage of the twelfth NMOS transistor (M51) (that is, V _DD -V _TM51 ), and because the node A is The voltage level of the power supply voltage (V _DD ), so the third NMOS transistor (M13) is in the OFF state, thereby effectively keeping the bit line (BL) at the power supply voltage until reading At the end of the cycle, the operation of reading logic 1 is successfully completed. It is worth noting here that during the read operation, the word line control signal (WLC) _deducts the threshold voltage of the twelfth NMOS transistor (M51) (ie V _DD -V _TM51 ) for the power supply voltage Therefore, it can effectively reduce the half-selected cell interference during reading. In addition, in the first phase of the read operation, the first instantaneous voltage (V _RVL1I ) of the first low voltage node (VL1) when reading logic 1 must satisfy equation (7): V _RVL1I = RGND×R _M26 /(R _M26 +R _M24 +R _M25 )>-V _TM11 (7) to effectively prevent the semi-selected cell interference during reading, where V _RVL1I represents the first low voltage node (VL1) during reading Logic 1 reads the initial instantaneous voltage, RGND represents the accelerated read voltage, R _M26 represents the on-resistance of the ninth NMOS transistor (M26), R _M24 represents the on-resistance of the seventh NMOS transistor (M24), R _M25 represents the on-resistance of the eighth NMOS transistor (M25), and V _TM11 represents the threshold voltage of the first NMOS transistor (M11); during the second stage of the read operation, the first low voltage node The voltage of (VL1) (V _RVL1 ) can be expressed by equation (8): V _RVL1 = ground voltage (8) By this, unnecessary power consumption can be effectively reduced.

Furthermore, in order to effectively reduce the interference of the semi-selected cell during reading and effectively reduce the leakage current, the absolute value of the accelerated read voltage (RGND) can be set more conservatively than that of the first NMOS transistor (M11) The threshold voltage (V _TM11 ), that is, |RGND|<V _TM11 (9) where |RGND| and V _TM11 represent the absolute value of the accelerated reading voltage and the threshold voltage of the first NMOS transistor (M11), respectively.

(2) Read logic 0 (node A stores logic 0):

Before the reading operation occurs, the first NMOS transistor (M11) is turned on (ON) and the second NMOS transistor (M12) is turned off (OFF), the node (A) and the node (B) are respectively The ground voltage and the first high power supply voltage (V _DDH1 ), and the bit line (BL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). Because the first NMOS transistor (M11) is ON, when the reading operation starts, the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage deducts the twelfth NMOS The threshold voltage V _DD -V _{TM51 of} transistor M51). When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from OFF to ON. The initial instantaneous voltage (V _AR0I ) of the node A must satisfy equation (10): V _AR0I = V _DD ×(R _M11 +(R _M24 +R _M25 )∥R _M26 )/(R _M13 +R _M11 +( R _M24 +R _M25 )∥R _M26 )+RGND×(R _M11 +R _M13 )∥R _M26 /(R _M24 +R _M25 +(R _M11 +R _M13 )∥R _M26 )×R _M13 /(R _M11 + R _M13 )<V _TM12 (10) to avoid turning on the second NMOS transistor (M12), where V _AR0I represents the initial instantaneous voltage when node A reads logic 0, R _M11 , R _M13 , R _M24 , R _M25 and R _M26 represent the first NMOS transistor (M11), the third NMOS transistor (M13), the seventh NMOS transistor (M24), the eighth NMOS transistor (M25) and the ninth NMOS, respectively The on-resistance of the transistor (M26), and V _DD , RGND and V _TM12 represent the power supply voltage (V _DD ), the accelerated read voltage (RGND) and the threshold voltage of the second NMOS transistor (M12), respectively. It is worth noting here that the accelerated read voltage (RGND) is designed to be lower than the ground voltage and the absolute value of the accelerated read voltage is designed to be less than the threshold voltage of the first NMOS transistor (M11). Furthermore, in the present invention, the word line control signal (WLC) during the reading period is set such that the power supply voltage _deducts the threshold voltage (V _DD -V _TM51 ) of the thirteenth NMOS transistor (M51), which On the one hand, it can effectively reduce the interference of the semi-selected cell during reading; on the other hand, it can be easier to satisfy equation (10) by increasing the on-resistance (R _M13 ) of the third NMOS transistor (M13).

Furthermore, during the reading of logic 0, since node B is the first high power supply voltage (V _DDH1 ), and the first low voltage node (VL1) is a voltage lower than the ground voltage, due to the first high The power supply voltage (V _DDH1 ) is set to be higher than the power supply voltage (V _DD ), therefore, the read speed can be effectively improved by increasing the conduction degree of the first NMOS transistor (M11). It is worth noting here that the first high power supply voltage (V _DDH1 ) is set higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the second PMOS transistor ( P12) The absolute value of the threshold voltage | V _TP12 | The sum of V _DD <V _DDH1 <V _DD +| V _TP12 | (11) where | V _TP12 | represents the second PMOS transistor (P12) threshold voltage The absolute value.

It is worth noting here that the second highest power supply voltage (V _DDH2 ) is set higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the ninth PMOS transistor ( P71) The absolute value of the threshold voltage | V _TP71 | The sum of V _DD <V _DDH2 <V _DD +|V _TP71 | (12)

Among them, |V _TP71 | represents the absolute value of the critical voltage of the ninth PMOS transistor (P71).

Of course, in order to simplify the circuit scale, the first high power supply voltage (V _DDH1 ) can be set to the same potential as the second high power supply voltage (V _DDH2 ).

(III) Standby mode

First, explain how the standby start circuit (4) in Figure 5 prompts the port SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM: first, before entering the standby mode, the inverted standby mode control signal (/S) Logic High, the inverse standby mode control signal (/S) of the logic High makes the fourth PMOS transistor (P41) off (OFF), and makes the twelfth NMOS transistor (M41) on (ON); Then, after entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the inverted standby mode control signal (/S) of the logic Low makes the fourth PMOS transistor (P41) conductive (ON) ), but within the initial period of the standby mode (the initial period is equal to the inverted standby mode control signal (/S) from logic High to logic Low, from the gate of the twelfth NMOS transistor (M41) The time until the voltage is enough to turn off the twelfth NMOS transistor (M41), which can be adjusted by a delay time provided by the second delay circuit (D2)), the twelfth NMOS transistor (M41) is still ON, so that the first low voltage node (VL1) can be quickly charged to the voltage level of the critical voltage (V _TM23 ) of the sixth NMOS transistor (M23), that is, the port SRAM can quickly enter standby mode. It is worth noting here that after the initial period of standby mode, the twelfth NMOS transistor (M41) turns off and stops supplying current.

Please refer to FIG. 5, in the standby mode, the standby mode control signal (S) is at a logic high level, and the inverted standby mode control signal (/S) is at a logic low level, and the inverted standby of the logic low level The mode control signal (/S) makes the fourth NMOS transistor (M21) in the control circuit (2) OFF, and the standby mode control signal (S) of the logic high level makes the fifth The NMOS transistor (M22) is turned on. At this time, the fifth NMOS transistor (M22) is used as an equalizer. Therefore, the fifth NMOS transistor (M22) in the on state can be used. Making the voltage level of the first low voltage node (VL1) equal to the voltage level of the second low voltage node (VL2), and the voltage levels will be equal to the threshold of the sixth NMOS transistor (M23) The voltage level of the voltage (V _TM23 ). Figure 8 is a simplified circuit diagram of the preferred embodiment of the present invention in Figure 5 during standby.

Figure 8 depicts the subthreshold leakage currents I ₁ , I ₂ , and I ₃ generated by the embodiment of the present invention during the standby mode, where it is assumed that the output of the first inverter in the SRAM cell (ie Node A is logic Low (it is worth noting here that the voltage level of the second low voltage node (VL2) is maintained at the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23) during standby mode Voltage level of node A, so the voltage level of node A is logic Low is also maintained at the voltage level of V _TM23 ), and the output of the second inverter (ie node B) is logic High (power supply voltage V _DD ). Since the leakage currents I ₁ , I ₂ , and I _{3 of the} embodiment of the present invention are all smaller than the previous art of Figure 1b, they are common knowledge and will not be repeated here.

(IV) Retention mode (retension mode)

In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are set to ground voltage, the working principle is the same as the traditional 5T SRAM cell with a single bit line in FIG. 3, I will not repeat it here.

【Invention Effect】

The high-speed static random access memory proposed by the present invention has the following effects:

(1) Increase the speed of writing logic 0: when writing logic 0 from logic 1, the access transistor (ie, the third NMOS transistor M13) works in the saturation region, and the current in the saturation region is its gate-source The voltage level of the voltage V _{GS (M13)} is proportional to the square of its threshold voltage, so by designing the bit line (BL) in the first stage of writing logic 0 to be lower than the ground voltage Voltage level can effectively accelerate the speed of writing logic 0;

(2) High design freedom: Since the present invention pulls the storage node (A) below the threshold voltage (V _TM12 ) of the second NMOS transistor (M12) when reading logic 0, there are two mechanisms, one is With the word line voltage level conversion circuit (5), the word line voltage applied to the access transistor of the selected cell (ie, the third NMOS transistor M13) is pulled below the power supply voltage (ie, V _DD- V _TM51 ), the other is to pull down the storage node (A) by the accelerated read voltage (RGND) lower than the ground voltage, so it has the effect of high design freedom;

(3) Effectively reduce the interference of the semi-selected cell during reading: The present invention can use the word line voltage level conversion circuit (5) to apply the access transistor applied to the selected cell during the reading operation ( That is, the word line voltage of the third NMOS transistor M13) is _pulled down below the power supply voltage (ie, V _DD -V _TM51 ), which on the one hand can reduce the third NMOS transistor (M13) in the semi-selected cell The read interference, on the other hand, can reduce the read interference of the first NMOS transistor (M11) in the semi-selected cell by reducing the accelerated read voltage (RGND) required to satisfy equation (10). Effectively reduce the interference of semi-selected cell during reading;

(4) High reading speed and avoid unnecessary power consumption: The present invention adopts a two-stage reading operation. In the first stage of the reading operation, the first low voltage node (VL1) is set to a voltage higher than the ground Low acceleration read voltage (RGND), and cooperate with high voltage level control circuit (6) to pull the high voltage node (VH) higher than the voltage level of the power supply voltage (V _DD ), so it can be effective Increase the reading speed, and set the first low voltage node (VL1) back to the ground voltage in the second stage of the reading operation, so as to reduce unnecessary power consumption;

(5) Quickly enter the standby mode: the invention is provided with a standby start circuit (4) to prompt the SRAM to quickly enter the standby mode, and thereby seek to improve the standby performance of the port SRAM;

(6) Increase the speed of writing logic 1 and avoid the problem of writing logic 1 difficult: The invention can use the plurality of control circuits (2) and the plurality of writing drive circuits (7) during the writing operation ) In order to effectively prevent the difficulty of writing logic 1, it also improves the speed of writing logic 1;

(7) Low standby current: Since the present invention is in standby mode, the fifth NMOS transistor (M22) in the on state can be used to make the voltage level of the first low voltage node (VL1) equal to the first The voltage levels of the two low voltage nodes (VL2), and make the voltage levels equal to the threshold voltage level of the sixth NMOS transistor (M23), so the present invention also has the effect of low standby current;

(8) Low number of transistors: For SRAM arrays with 1024 rows and 1024 rows, the traditional 1B Figure 6T static random access memory array requires a total of 1024×1024×6=6,291,456 transistors, and the invention proposes The static random access memory only needs 1024×1024×5+1024×37+6=5,280,774 transistors, which reduces the number of transistors by 16.1%.

(9) Effectively prevent erroneous writing due to unintended factors in standby mode: In standby mode, if the write control signal (WC) is at a logic high level due to unintended factors, due to the multiple control The voltage level of the node (C) in the circuit (2) is the logic voltage level of the standby mode control signal (S), so it will turn on the ninth NMOS transistor (M26) and make the first low The voltage node (VL1) is a ground voltage, so it can effectively prevent erroneous writing.

Although the present invention specifically discloses and describes selected preferred embodiments, those skilled in the art may understand that any possible changes in form or detail do not depart from the spirit and scope of the present invention. Therefore, all changes within the relevant technical category are included in the patent application scope of the present invention.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧ Standby start circuit

5‧‧‧Character line voltage level conversion circuit

6‧‧‧High voltage level control circuit

7‧‧‧Write driver circuit

P11‧‧‧The first PMOS transistor

P12‧‧‧ Second PMOS transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧ Third NMOS transistor

A‧‧‧storage node

B‧‧‧Inverted storage node

BL‧‧‧bit line

WLC‧‧‧Character line control signal

V _DD ‧‧‧ Power supply voltage

VH‧‧‧High voltage node

VL1‧‧‧The first low voltage node

VL2‧‧‧second low voltage node

S‧‧‧Standby mode control signal

/S‧‧‧Inverted standby mode control signal

M21‧‧‧ Fourth NMOS transistor

M22‧‧‧Fifth NMOS transistor

M23‧‧‧Sixth NMOS transistor

M24‧‧‧NMOS transistor

M25‧‧‧Eighth NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧Tenth NMOS transistor

P21‧‧‧The third PMOS transistor

RC‧‧‧Read control signal

RGND‧‧‧Accelerated reading voltage

/RC‧‧‧Reverse read control signal

/WC‧‧‧Inverse write control signal

INV‧‧‧ third inverter

D1‧‧‧ First delay circuit

P31‧‧‧The fourth PMOS transistor

P‧‧‧Precharge signal

M41‧‧‧Eleventh NMOS transistor

P41‧‧‧ fifth PMOS transistor

C‧‧‧Node

D2‧‧‧second delay circuit

WL‧‧‧character line

R‧‧‧Read signal

P51‧‧‧Sixth PMOS transistor

M51‧‧‧Twelfth NMOS transistor

M52‧‧‧Thirteenth NMOS transistor

P61‧‧‧The seventh PMOS transistor

P62‧‧‧Eighth PMOS transistor

I63‧‧‧ fourth inverter

V _{DDH1 ‧‧‧The} highest power supply voltage

V _{DDH2 ‧‧‧The} second highest power supply voltage

P71‧‧‧Ninth PMOS transistor

M71‧‧‧14th NMOS transistor

M72‧‧‧The fifteenth NMOS transistor

M73‧‧‧Sixteenth NMOS transistor

I71‧‧‧fifth inverter

I72‧‧‧ sixth inverter

Cap‧‧‧Capacitor

Din‧‧‧Enter data

D3‧‧‧The third delay circuit

D4‧‧‧ Fourth Delay Circuit

Y‧‧‧Line decoder output signal

Claims (10)

A high-speed write-in port static random access memory, including: a memory array, the memory array is composed of a plurality of rows of memory cells and a plurality of rows of memory cells, each row of memory cells The cell and each row of memory cells include a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3 ), each row of memory cells is provided with a pre-charge circuit (3); a standby start circuit (4), the standby start circuit (4) is to prompt the 5T port static random access memory to quickly enter the standby mode to Effectively improve the standby performance of the 5T port static random access memory; a plurality of word line voltage level conversion circuits (5), each row of memory cells is provided with a word line voltage level conversion circuit (5), In order to effectively reduce the interference of the half-selected cell during reading; a plurality of high-voltage level control circuits (6), each column of memory cells is provided with a high-voltage level control circuit (6) to increase when reading logic 0 Read speed; and a plurality of write drive circuits (7), each row of memory cells is provided with a write drive circuit (7) to increase the write speed during write operations; wherein, each memory cell (1) It further includes: a first inverter composed of a first PMOS transistor (P11) and a first NMOS transistor (M11), the first inverter is connected to a power supply voltage (V _DD ) and a first low voltage node (VL1); a second inverter is composed of a second PMOS transistor (P12) and a second NMOS transistor (M12), the first The two inverters are connected between a high voltage node (VH) and a second low voltage node (VL2); a storage node (A) is formed by the output terminal of the first inverter; The phase storage node (B) is formed by the output of the second inverter; a third NMOS transistor (M13) is connected between the storage node (A) and the bit line (BL) , And the gate is connected to a word line control signal (WLC); wherein, the first inverter and the second inverter are alternately coupled, that is, the output terminal of the first inverter (ie The storage node A) is connected to the input terminal of the second inverter, and the output terminal of the second inverter (that is, the inverted storage node B) is connected to the input terminal of the first inverter; Each control circuit (2) further includes: a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor (M24) , An eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), A third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), a standby mode control Control signal (S) and an inverse standby mode control signal (/S); wherein the source, gate and drain of the fourth NMOS transistor (M21) are connected to the ground voltage and the inverse standby mode, respectively The control signal (/S) and the second low voltage node (VL2); the source, gate and drain of the fifth NMOS transistor (M22) are connected to the second low voltage node (VL2) and the The standby mode control signal (S) and the first low voltage node (VL1); the source of the sixth NMOS transistor (M23) is connected to the ground voltage, and the gate and the drain are connected together and connected to the The first low voltage node (VL1); the source, gate and drain of the seventh NMOS transistor (M24) are connected to the drain of the eighth NMOS transistor (M25) and the read control signal ( RC) and the first low voltage node (VL1); the source, gate and drain of the eighth NMOS transistor (M25) are connected to the accelerated read voltage (RGND) and the first delay circuit ( D1) the output and the source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected between the output of the third inverter (INV) and the eighth NMOS transistor (M25) Between the gates; the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the ninth NMOS The source, gate and drain of the crystal (M26) are connected to the ground voltage, the drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); the tenth NMOS transistor The source, gate and drain of (M27) are connected to the standby mode control signal (S), the write control signal (WC) and the gate of the ninth NMOS transistor (M26) respectively; the third The source, gate, and drain of the PMOS transistor (P21) are connected to the inverted standby mode control signal (/S), the write control signal (WC), and the tenth NMOS transistor (M27), respectively Drain; wherein, the drain of the third PMOS transistor (P21), the drain of the tenth NMOS transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected together to form a Node (C), when the write control signal (WC) is a logic low level, the voltage level of the node (C) is the logic voltage level of the inverted standby mode control signal (/S), and when the When the write control signal (WC) is at a logic high level, the voltage level of the node (C) is the logic voltage level of the standby mode control signal (S), thereby effectively preventing unintended factors in standby mode The erroneous writing occurred; where the read control signal (RC) during the non-read mode is set to the level of the accelerated read voltage (RGND) to prevent the seventh NMOS transistor (M24) Leakage current during non-read mode; in addition, the standby start circuit (4) is designed It is calculated that during an initial period of entering the standby mode, the parasitic capacitance at the first low voltage node (VL1) is quickly charged to the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23); In addition, each word line voltage level conversion circuit (5) further includes: a sixth PMOS transistor (P51), a twelfth NMOS transistor (M51), a thirteenth NMOS transistor (M52), The read control signal (RC), an inverted write control signal (/WC), an inverted read control signal (/RC) and the word line control signal (WLC); wherein, the sixth PMOS The source, gate and drain of the crystal (P51) are connected to a word line (WL), the reverse write control signal (/WC) and the word line control signal (WLC); the tenth The source, gate and drain of the two NMOS transistors (M51) are connected to the word line control signal (WLC), the read control signal (RC) and the word line (WL); and the first The source, gate, and drain of the NMOS transistor (M52) are connected to the word line control signal (WLC), the inverted read control signal (/RC), and the word line (WL), respectively Where each word line voltage level conversion circuit (5) converts the word line (WL) of the selected cell from the power supply voltage (V _DD ) to the power supply voltage during the read operation ( V _DD ) is deducted from the threshold voltage (V _TM51 ) of the twelfth NMOS transistor (M51) (ie V _DD -V _TM51 ) and then supplied to the word line control signal (WLC); and during the writing operation , Then the power supply voltage (V _DD ) of the word line (WL) of the selected cell is provided to the word line control signal (WLC); moreover, each high voltage level control circuit (6) It further includes: a seventh PMOS transistor (P61), an eighth PMOS transistor (P62), a fourth inverter (I63), the read control signal (RC) and a first high power supply voltage (V _DDH1 ), wherein the source, gate and drain of the seventh PMOS transistor (P61) are respectively connected to the power supply voltage (V _DD ), the read control signal (RC) and the high voltage node (VH ), the source, gate and drain of the eighth PMOS transistor (P62) are connected to the first high power supply voltage (V _DDH1 ), the output of the fourth inverter (I63) and the high Voltage node (VH), and the input of the fourth inverter (I63) is for receiving the read control signal (RC), and the output is connected to the gate of the eighth PMOS transistor (P62); finally, Each write drive circuit (7) further includes: a ninth PMOS transistor (P71), a fourteenth NMOS transistor (M71), a fifteenth NMOS transistor (M72), a sixteenth NMOS transistor Crystal (M73), a fifth inversion (I71), a sixth inverter (I72), a capacitor (Cap), an input data (Din), a row of decoder output signals (Y), a third delay circuit (D3), a fourth delay Circuit (D4) and a second highest power supply voltage (V _DDH2 ); wherein the source, gate and drain of the ninth PMOS transistor (P71) are connected to the second highest power supply voltage (V _DDH2 ), the output of the fifth inverter (I71) and the drain of the fourteenth NMOS transistor (M71); the source, gate and drain of the fourteenth NMOS transistor (M71) are respectively Connected to the drain of the sixteenth NMOS transistor (M73), the output of the fifth inverter (I71) and the drain of the ninth PMOS transistor (P71); the fifteenth NMOS transistor (M72) ) The source, gate and drain are connected to the ground voltage, the output of the third delay circuit (D3) and the drain of the ninth PMOS transistor (P71); the sixteenth NMOS transistor ( M73) the source, gate and drain are connected to the ground voltage, the output of the sixth inverter (I72) and the source of the fourteenth NMOS transistor (M71); the fifth inversion The input of the device (I71) is for receiving the input data (Din), and the output is connected to the gate of the ninth PMOS transistor (P71), the gate of the fourteenth NMOS transistor (M71) and the first Three delay circuit (D3) inputs; the sixth inverter (I72) input is for receiving the row decoder output signal (Y), and the output is connected to the fourth delay circuit (D4) input and the The gate of the sixteenth NMOS transistor (M73); one end of the capacitor (Cap) is connected to the output of the fourth delay circuit (D4), and the other end of the capacitor (Cap) is connected to the fourteenth The source of the NMOS transistor (M71) and the drain of the sixteenth NMOS transistor (M73); wherein, the drain of the ninth PMOS transistor (P71) and the fourteenth NMOS transistor (M71) The drain and the drain of the fifteenth NMOS transistor (M72) are connected to the bit line (BL). The bit line (BL) is designed to be lower than The voltage level of the ground voltage accelerates the speed of writing logic 0, and when writing logic 1, it is designed to be the second highest power supply voltage (V _DDH2 ) higher than the power supply voltage (V _DD ) Level to accelerate the speed of writing logic 1. As described in item 1 of the patent application scope, a high-speed static random access memory with a port, wherein each precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge Signal (P); wherein the source, gate and drain of the fourth PMOS transistor (P31) are connected to the power supply voltage (V _DD ), the precharge signal (P) and the corresponding Bit line (BL), so that during a pre-charge period, the pre-charge signal (P) at a logic low level is used to pre-charge the corresponding bit line (BL) to the power supply voltage (V _DD ) Level. As described in item 2 of the patent application scope, a high-speed static random access memory with a large port, wherein the standby start circuit (4) is composed of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2) and the inverted standby mode control signal (/S); wherein, the source, gate and drain of the fifth PMOS transistor (P41) It is connected to the power supply voltage (VDD), the inverted standby mode control signal (/S) and the drain of the eleventh NMOS transistor (M41); the source of the eleventh NMOS transistor (M41) The gate, gate and drain are connected to the first A low voltage node (VL1), the output of the second delay circuit (D2) and the drain of the fifth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverting standby mode control Signal (/S), and the output of the second delay circuit (D2) is connected to the gate of the eleventh NMOS transistor (M41). As described in item 3 of the patent application scope, a high-speed static random access memory with a port, in which the first stage where each write drive circuit (7) writes a logic 0 satisfies the following equation: V _BL1 =-V _DD ×Cap/(Cap+C _BL ), where V _BL1 represents the voltage level of the bit line (BL) at the first stage of writing logic 0, and the absolute value of V _BL1 is designed to be less than this The threshold voltage of the third NMOS transistor (M13), V _{DD is} the voltage level of the power supply voltage (V _DD ), and Cap and C _BL represent the capacitance value of the capacitor (Cap) and the bit line ( BL) parasitic capacitance value. The port static random access memory with high writing speed as described in item 4 of the patent scope, wherein the storage node (A) is written from logic 0 to logic 1 to write the initial instantaneous voltage (V _AWI1 ) Satisfy the following equation: V _AWI1 = V _DDH2 × (R _M11 + R _M23 )/(R _M13 + R _M11 + R _M23 ) and V _AWI1 > V _TM12 where R _M11 , R _M13 and R _M23 represent the first NMOS respectively Transistor (M11), the third NMOS transistor (M13) and the sixth NMOS transistor (M23) on-resistance, and V _DDH2 and V _TM12 respectively represent the voltage of the second highest power supply voltage (V _DDH2 ) The level and the threshold voltage of the second NMOS transistor (M12). As described in item 5 of the patent application scope, a port-based static random access memory with a high writing speed, wherein the storage node (A) is written with a logic 1 to a logic 0 write initial instantaneous voltage (V _AWI0 ) Meet the following equation: V _AWI0 =V _BL1 ×R _P11 /(R _M13 +R _P11 )+V _DD ×R _M13 /(R _M13 +R _P11 ) where R _M13 and R _P11 represent the third NMOS transistor ( M13) and the on-resistance of the first PMOS transistor (P11), and V _BL1 and V _DD respectively represent the voltage level of the bit line (BL) at the first stage of writing logic 0 and the power supply voltage (V _DD ) voltage level. As described in Item 1 of the patent application range, a high-speed static random access memory with a high write speed, wherein the initial instantaneous voltage (V _AR0I ) when the storage node A reads logic 0 satisfies the following equation: V _AR0I =V _DD ×(R _M11 +(R _M24 +R _M25 )∥R _M26 )/(R _M13 +R _M11 +(R _M24 +R _M25 )∥R _M26 )+RGND×(R _M11 +R _M13 ) ∥R _M26 /(R _M24 +R _M25 +(R _M11 +R _M13 )∥R _M26 )×R _M13 /(R _M11 +R _M13 ) and V _AR0I <V _TM12 Among them, R _M11 , R _M13 , R _M24 , R _M25 and R _M26 represent the first NMOS transistor (M11), the third NMOS transistor (M13), the seventh NMOS transistor (M24), the eighth NMOS transistor (M25) and the ninth The on-resistance of the NMOS transistor (M26), and V _DD , RGND and V _TM12 respectively represent the power supply voltage (V _DD ), the accelerated read voltage (RGND) and the critical voltage of the second NMOS transistor (M12) . As described in item 1 of the patent application range, a high-speed static random access memory with a high port speed, wherein the first instantaneous voltage (V) of the first low voltage node (VL1) when reading logic 1 is read _RVL1I ) satisfies the following equation: V _RVL1I = RGND×R _M26 /(R _M26 +R _M24 +R _M25 ) and V _RVL1I >-V _TM11 where RGND represents the accelerated reading voltage, R _M26 , R _M24 and R _M25 are respectively Represents the on-resistance of the ninth NMOS transistor (M26), the seventh NMOS transistor (M24) and the eighth NMOS transistor (M25), and V _TM11 represents the critical voltage of the first NMOS transistor (M11) . As described in item 1 of the patent scope, a high-speed static random access memory with a high write speed, wherein the first high power supply voltage (V _DDH1 ) is set to be higher than the power supply voltage (V _DD ) But lower than the sum of the absolute value of the power supply voltage (V _DD ) and the critical voltage of the second PMOS transistor (P12) |V _TP12 |, that is, V _DD <V _DDH1 <V _DD +|V _TP12 |. As described in item 1 of the patent scope, a high-speed static random-access memory with high writing speed, wherein the second highest power supply voltage (V _DDH2 ) is set to be higher than the power supply voltage (V _DD ) But lower than the sum of the absolute value of the power supply voltage (V _DD ) and the critical voltage of the ninth PMOS transistor (P71) |V _TP71 |, that is, V _DD <V _DDH2 <V _DD +|V _TP71 |.

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