TWI692042B - Semiconductor package structure and manufacturing method thereof - Google Patents

Abstract

A manufacturing method of a semiconductor package structure including the following steps is provided. Providing a lead frame which includes a first lead group and a second lead group. Disposing a carrier at one side of the first lead group, wherein the first lead group comprises a plurality of first leads and the carrier covers a gap between any two adjacent first leads. Forming a two-stage thermosetting adhesive layer at the other side of the first lead group, and the two-stage thermosetting adhesive layer is further filled into the gap between any two adjacent first leads. Adhering a first chip to the two-stage thermosetting adhesive layer, and the first chip and the carrier are located at two opposite sides of the first lead group. Using wire bonding manner to make the first chip be electrically connected to the first lead group and the second lead group. Forming an encapsulant to cover the lead frame, the two-stage thermosetting adhesive layer and the first chip.

Description

Semiconductor packaging structure and manufacturing method thereof

The invention relates to a packaging structure, and in particular to a semiconductor packaging structure and a manufacturing method thereof.

Lead frames are often used in semiconductor packages to carry chips and as a medium for the chips to be electrically connected to external devices. Further, the chip can be carried by the first pin group of the lead frame and electrically connected to the first pin group and the second pin group relative to the first pin group, but is limited by the size of the lead frame If the large-size chip is placed on the first pin group of the lead frame, the portion of the first pin group that is electrically connected to the large-size chip may be covered by the large-size chip, resulting in the large-size chip One pin group is electrically connected. In addition, at present, the lead frame is pre-adhered to the pin group with an appropriate size of adhesive film, and then the wafer is directly attached to the adhesive film. However, the cost of the adhesive film is quite expensive, so how to overcome the above large size The technical problems of chip packaging and reducing the cost of die bonding have become one of the problems that need to be solved urgently.

The invention provides a method for manufacturing a semiconductor packaging structure, which is beneficial to large-sized chip packaging.

The invention provides a semiconductor packaging structure, which helps to simplify the crystal bonding process, reduce the production cost and has good reliability.

The manufacturing method of the semiconductor package structure of the present invention includes the following steps. A lead frame is provided, including a first pin group and a second pin group. The carrier is disposed on one side of the first pin group, wherein the first pin group includes a plurality of first pins, and the carrier covers a gap between any two adjacent first pins. A two-stage thermosetting adhesive layer is formed on the other side of the first pin group. The two-stage thermosetting adhesive layer further fills the gap between any two adjacent first pins. The first chip is attached to the two-stage thermosetting adhesive layer, and the first chip and the carrier are respectively located on opposite sides of the first pin group. The first chip is electrically connected to the second pin group by wire bonding. An encapsulating gel is formed to cover the lead frame, the two-stage thermosetting adhesive layer and the first chip.

In an embodiment of the invention, the above-mentioned method for manufacturing a semiconductor package structure further includes the following steps. After attaching the first chip to the two-stage thermosetting adhesive layer, a baking process is performed to fix the first chip to the first pin group through the two-stage thermosetting adhesive layer, and then the carrier is removed.

In an embodiment of the invention, in the process of attaching the first wafer to the two-stage thermosetting adhesive layer, the active surface of the first wafer faces the two-stage thermosetting adhesive layer, and the active surface of the first wafer At least partially between the first pin group and the second pin group.

In one embodiment of the present invention, the above-mentioned method of forming the two-stage thermosetting adhesive layer on the first pin group uses a screen printing process.

In an embodiment of the present invention, the lead frame further includes a bus bar located between the first pin group and the second pin group. During the process of attaching the first chip to the two-stage thermosetting adhesive layer, The end of the first chip extends from the first pin group toward the second pin group and stops between the bus bar and the second pin group, and the first chip is electrically connected to the bus bar by wire bonding.

In an embodiment of the invention, the above-mentioned method for manufacturing a semiconductor package structure further includes the following steps. After attaching the first wafer to the two-stage thermosetting adhesive layer, the second wafer is attached to the first wafer, and the first wafer is located between the two-stage thermosetting adhesive layer and the second wafer. The first chip is electrically connected to the first pin group, the second chip is electrically connected to the second pin group and the first chip is electrically connected to the second chip by wire bonding, and the first chip is electrically connected through the second chip The second pin group.

The semiconductor packaging structure of the present invention includes a lead frame, a two-stage thermosetting adhesive layer, a first chip, and an encapsulating gel. The lead frame includes a first pin group and a second pin group, where the first pin group includes a plurality of first pins. The two-stage thermosetting adhesive layer is disposed on one side of the first pin group, and is further filled in the gap between any two adjacent first pins. The first chip is attached to the two-stage thermosetting adhesive layer to connect the first pin group through the two-stage thermosetting adhesive layer, and the first chip is electrically connected to the first pin group and the second pin. The packaging gel coats the lead frame, the two-stage thermosetting adhesive layer and the first chip.

In an embodiment of the invention, the above-mentioned semiconductor packaging structure further includes a carrier, which is disposed on the other side of the first pin group and is covered by the packaging gel. The first wafer carriers are respectively located on opposite sides of the first pin group, wherein the carrier covers the gap between any two adjacent first pins and fills the gap between any two adjacent first pins The two-stage thermosetting adhesive layer contacts the carrier.

In an embodiment of the present invention, the lead frame further includes a bus bar, which is located between the first pin group and the second pin group. The end of the first chip extends from the first pin group toward the second pin group and stops between the bus bar and the second pin group, and the first chip is electrically connected to the bus bar.

In an embodiment of the present invention, the above-mentioned semiconductor package structure further includes a second chip, is attached to the first chip, and is covered with a packaging gel. The first chip is located between the two-stage thermosetting adhesive layer and the second chip, wherein the first chip is electrically connected to the first pin group, the second chip is electrically connected to the second pin group, and the first chip is electrically connected to the second Chip, so that the first chip is electrically connected to the second pin group through the second chip.

Based on the above, the first pin group has opposite first and second sides, and the first side is provided with electrical contacts. By placing the chip on the second side of the first pin group, the semiconductor package of the present invention The manufacturing method of the structure can avoid the situation that the electrical contact on the first side of the inner pin is covered by the wafer, so it is advantageous for large chip size packaging. On the other hand, the chip is fixed to the second side of the first pin group through a two-stage thermosetting adhesive layer and does not easily fall off from the lead frame, so the semiconductor package structure of the present invention has good reliability.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

1A to 1D are schematic diagrams of the manufacturing process of a semiconductor package structure according to an embodiment of the invention. FIG. 2A is a schematic top view corresponding to FIG. 1A. FIG. 2B is a schematic cross-sectional view of FIG. 1B along section line I-I. 2C is a schematic cross-sectional view of FIG. 1C along section line J-J. Please refer to FIGS. 1A and 2A. In this embodiment, first, a lead frame 110 is provided. The lead frame 110 includes a first pin group 111 and a second pin group 112 opposite to each other. The first pin group 111 is formed by A plurality of first pins 111c are formed in parallel at an appropriate pitch, and the second pin group 112 is formed by a plurality of second pins 112c in parallel at an appropriate pitch. For example, the gap 111d is maintained between any two adjacent first pins 111c, and the gap between any two adjacent second pins 112c may have the same size as the gap 111d, but the present invention Not limited to this.

The first pin group 111 has opposite first sides 111a and second sides 111b, and the second pin group 112 has opposite first sides 112a and second sides 112b. The first side 111a of the first pin group 111 and the first side 112a of the second pin group 112 face the same side, and the second side 111b of the first pin group 111 and the second side of the second pin group 112 112b faces the same side. Further, the first pin group 111 and the second pin group 112 face each other-the two ends are separated from each other to form a channel 101, and the length of the first pin group 111 is greater than that of the second pin group 112 length. On the other hand, the lead frame 110 further includes a bus bar 113 located in the channel 101 between the first pin group 111 and the second pin group 112. As shown in FIG. 1A, a gap is maintained between the first pin group 111 and the bus bar 113, and a gap is maintained between the bus bar 113 and the second pin group 112.

Next, the carrier 120 is disposed on the first side 111a of the first pin group 111, wherein the carrier 120 partially covers the first side 111a of the first pin group 111 and does not cover the first side 111a of the first pin group 111 The block closest to the second pin group 112 forms a bonding area. For example, the carrier 120 may be a combination of an adhesive tape or a spacer and an adhesive tape (or colloid) to be attached to the first side 111a of the first pin group 111, so the carrier 120 does not arbitrarily relative to the first pin Group 111 moves. On the other hand, the carrier 120 is used to cover the gap 111d between any two adjacent first pins 111c, and the degree to which each gap 111d is covered by the carrier 120 and the number of gaps 111d covered by the carrier 120 depend on the actual process Depends.

Please refer to FIG. 1B and FIG. 2B, and then, a two-stage thermosetting adhesive layer 130 is formed on the second side 111b of the first pin group 111, wherein the two-stage thermosetting adhesive layer 130 is also called a semi-hardening stage epoxy resin (b-stage epoxy resin), and can be formed on the second side 111b of the first pin group 111 through a screen printing process. In this embodiment, the distribution range of the two-stage thermosetting adhesive layer 130 on the second side 111b of the first pin group 111 is substantially the same as or similar to the distribution range of the carrier 120 on the first side 111a of the first pin group 111 Among them, the two-stage thermosetting adhesive layer 130 is further filled into the gap 111d between any two adjacent first pins 111c, and the two-stage thermosetting adhesive layer 130 is restricted by the carrier 120 and does not flow randomly.

On the other hand, the two-stage thermosetting adhesive layer 130 filled in the gap 111d between any two adjacent first pins 111c contacts the carrier 120, and the contact carrier 120 is exposed to any two adjacent first pins 111c The surface within the gap 111d is improved by the adhesion area, and the two-stage thermosetting adhesive layer 130 is not easy to fall off from the gap of the first pin group 111, so it helps to improve the process yield. In other embodiments, the two-stage thermosetting adhesive layer filled in the gap between any two adjacent first pins may not contact the carrier, that is, the carrier is exposed between any two adjacent first pins Keep the distance within the gap.

Please refer to FIGS. 1C and 2C. Then, the first chip 140 is bonded to the two-stage thermosetting adhesive layer 130, and the first chip 140 and the carrier 120 are respectively located on opposite sides of the first pin group 111. Further, the active surface 141 of the first chip 140 faces the second side 111b of the first pin group 111 and the two-stage thermosetting adhesive layer 130, and is attached to the two-stage thermosetting adhesive layer 130 with the active surface 141, and then passes through A baking process cures the two-stage thermosetting adhesive layer 130, so that the first chip 140 is fixed to the second side 111b of the first pin group 111 through the two-stage thermosetting adhesive layer 130.

On the other hand, the active surface 141 of the first wafer 140 has a section 141a, wherein the section 141a is not in contact with the two-stage thermosetting adhesive layer 130 and falls between the first pin group 111 and the second pin group 112 (I.e. falls within the channel 101). Further, the active surface 141 of the first wafer 140 is provided with bonding pads and is located in the section 141a. As shown in FIG. 1C, the end 142 of the first wafer 140 corresponding to the section 141 a extends from the first pin group 111 toward the second pin group 112 and stops between the bus bar 113 and the second pin group 112 (That is, it extends toward the second pin group 112 and stops in the channel 101), and the bonding pad on the active surface 141 falls between the bus bar 113 and the second pin group 112, for example.

Please refer to FIG. 1C. Next, the first chip 140 is electrically connected to the first pin group 111 and the second pin group 112 by wire bonding. For example, the wire 150 passes through the gap between the bus bar 113 and the second pin group 112 from the bonding pad on the active surface 141, and extends across the bus bar 113 toward the first side 111a of the first pin group 111, The wire bonding area on the first pin group 111 is electrically connected. The wire 151 passes through the gap between the bus bar 113 and the second pin group 112 from the bonding pad on the active surface 141 and extends toward the bus bar 113 to be electrically connected to the bus bar 113. The electrical junction of the wire 151 on the bus bar 113 and the electrical junction of the wire 150 on the first pin group 111 face the same side. On the other hand, the wire 152 passes through the gap between the bus bar 113 and the second pin group 112 from the bonding pad on the active surface 141 and extends toward the first side 112a of the second pin group 112 for electrical bonding The bonding area on the second pin group 112. In particular, the above-mentioned lead-through method can be adjusted according to actual process requirements.

Please refer to FIG. 1D. Finally, an encapsulant 160 is formed to cover the lead frame 110, the carrier 120, the two-stage thermosetting adhesive layer 130, the first chip 140, and the wires 150-152. So far, the fabrication of the semiconductor package structure 100 of this embodiment is substantially completed, and the semiconductor package structure 100 obtained through the above-mentioned fabrication process has good reliability.

3 is a schematic diagram of a semiconductor package structure according to another embodiment of the invention. Referring to FIG. 3, the semiconductor package structure 100A of this embodiment is slightly different from the semiconductor package structure 100 of the above embodiment. Further, the semiconductor package structure 100A of this embodiment further includes a back surface 143 fixed to the first chip 140 The second wafer 170, and the second wafer 170 is covered by the encapsulant 160.

In terms of the manufacturing process of the semiconductor package structure 100A of this embodiment, after the first wafer 140 is bonded to the two-stage thermosetting adhesive layer 130, the second wafer 170 is bonded to the back surface of the first wafer 140 with the active surface 171 143, and the first wafer 140 is located between the two-stage thermosetting adhesive layer 130 and the second wafer 170. Further, the active surface 171 of the second wafer 170 has a section 171 a, wherein the section 171 a does not fit the back surface 143 of the first wafer 140 and extends beyond the end 142 of the first wafer 140. Also, the section 171 a of the active surface 171 falls between the bus bar 113 and the second pin group 112.

On the other hand, the first chip 140 is not directly electrically connected to the second pin group 112, but is indirectly electrically connected to the second pin group 112 through the second chip 170. In addition, the second chip 170 indirectly and electrically connects the bus bar 113 and the first pin group 111 through the first chip 140. For example, the active surface 171 of the second wafer 170 is provided with bonding pads and is located in the section 171a. As shown in FIG. 3, the wire 153 extends from the pad on the active surface 171 of the second wafer 170 toward the active surface 141 extending the first wafer 140, and is electrically connected to the pad on the active surface 141. The wire 154 passes through the gap between the bus bar 113 and the second pin group 112 from the bonding pad on the active surface 171 of the second chip 170, and extends toward the first side 112a of the second pin group 112 to electrically The bonding area on the second pin group 112 is engaged. In particular, the above-mentioned lead-through method can be adjusted according to actual process requirements.

4 is a schematic diagram of a semiconductor package structure according to yet another embodiment of the present invention. Referring to FIG. 4, the semiconductor package structure 100B of this embodiment is slightly different from the semiconductor package structure 100 of the above embodiment. Further, the semiconductor package structure 100B of this embodiment is not provided with a carrier 120 (see FIG. 1D ).

In terms of the manufacturing process of the semiconductor package structure 100B of this embodiment, the carrier 120 (see FIG. 1D) is removed before the encapsulant 160 is formed. Furthermore, after curing the two-stage thermosetting adhesive layer 130 through a baking process, so that the first chip 140 is fixed to the second side 111b of the first pin group 111 through the two-stage thermosetting adhesive layer 130, the carrier 120 (See Figure 1D) is removed.

5 is a schematic diagram of a semiconductor package structure according to yet another embodiment of the present invention. Referring to FIG. 5, the semiconductor package structure 100C of this embodiment is slightly different from the semiconductor package structure 100A of the above embodiment. Further, the semiconductor package structure 100C of this embodiment is not provided with a carrier 120 (see FIG. 3 ).

In terms of the manufacturing process of the semiconductor packaging structure 100C of this embodiment, the carrier 120 (see FIG. 3) is removed before the encapsulant 160 is formed. Furthermore, after curing the two-stage thermosetting adhesive layer 130 through a baking process, so that the first chip 140 is fixed to the second side 111b of the first pin group 111 through the two-stage thermosetting adhesive layer 130, the carrier 120 (See Figure 3) is removed.

In summary, the first pin group has opposite first and second sides, and the first side is provided with a bonding area. By placing the chip on the second side of the first pin group, the semiconductor package of the present invention The manufacturing method of the structure can avoid the situation that the wire bonding area on the first side of the first pin group is covered by the wafer, so it is beneficial to the packaging of a large chip size. When forming the two-stage thermosetting adhesive layer on the second side of the first pin group, the first side of the first pin group is provided with a carrier to prevent the two-stage thermosetting adhesive layer from flowing randomly or falling off from the first pin group , So it helps to improve the yield of the process. On the other hand, the chip is fixed to the second side of the first pin group through a two-stage thermosetting adhesive layer and does not easily fall off from the lead frame, so the semiconductor package structure of the present invention has good reliability.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100, 100A~100C: semiconductor packaging structure

101: channel

110: lead frame

111: first pin group

111a, 112a: first side

111b, 112b: second side

111c: the first pin

111d: clearance

112: second pin group

112c: second pin

113: bus bar

120: carrier

130: Two-stage thermosetting adhesive layer

140: the first chip

141, 171: Active surface

141a, 171a: section

142: end

143: back surface

150~154: wire

160: encapsulating colloid

170: second chip

1A to 1D are schematic diagrams of the manufacturing process of a semiconductor package structure according to an embodiment of the invention. FIG. 2A is a schematic top view corresponding to FIG. 1A. FIG. 2B is a schematic cross-sectional view of FIG. 1B along section line I-I. 2C is a schematic cross-sectional view of FIG. 1C along section line J-J. 3 is a schematic diagram of a semiconductor package structure according to another embodiment of the invention. 4 is a schematic diagram of a semiconductor package structure according to yet another embodiment of the present invention. 5 is a schematic diagram of a semiconductor package structure according to yet another embodiment of the present invention.

100: Semiconductor packaging structure

101: channel

110: lead frame

111: first pin group

111a, 112a: first side

111b, 112b: second side

112: second pin group

113: bus bar

120: carrier

130: Two-stage thermosetting adhesive layer

140: the first chip

141: Active surface

141a: Section

142: end

150~152: wire

160: encapsulating colloid

Claims (8)

A method for manufacturing a semiconductor packaging structure includes: providing a lead frame including a first pin group and a second pin group; setting a carrier on one side of the first pin group, wherein the first pin group includes A plurality of first pins, and the carrier covers a gap between any two adjacent ones of the plurality of first pins; forming a two-stage thermosetting adhesive layer on the other side of the first pin group, The two-stage thermosetting adhesive layer is further filled into the gap between any two adjacent ones of the plurality of first pins; the first chip is attached to the two-stage thermosetting adhesive layer, and the first chip And the carrier are located on opposite sides of the first pin group; wire bonding is used to electrically connect the first chip to the first pin group and the second pin group; and forming Encapsulating colloid to cover the lead frame, the two-stage thermosetting adhesive layer and the first chip, wherein the lead frame further includes a bus bar located between the first pin group and the second pin Between the groups, in the process of attaching the first wafer to the two-stage thermosetting adhesive layer, the end of the first wafer extends from the first pin group toward the second pin group It also stops between the bus bar and the second pin group, and the first chip is electrically connected to the bus bar by wire bonding. The manufacturing method of the semiconductor package structure as described in item 1 of the patent application scope further includes: After attaching the first chip to the two-stage thermosetting adhesive layer, a baking process is performed to fix the first chip to the first pin group through the two-stage thermosetting adhesive layer, Then remove the carrier. The method for manufacturing a semiconductor package structure as described in item 2 of the patent application range, wherein in the process of attaching the first wafer to the two-stage thermosetting adhesive layer, the active surface of the first wafer faces the The two-stage thermosetting adhesive layer makes at least part of the active surface of the first wafer fall between the first pin group and the second pin group. The method for manufacturing a semiconductor package structure as described in item 1 of the patent application scope, wherein the method of forming the two-stage thermosetting adhesive layer on the first pin group is by a screen printing process. The method for manufacturing a semiconductor package structure as described in item 1 of the patent application scope further includes: after bonding the first wafer to the two-stage thermosetting adhesive layer, bonding the second wafer to the first A wafer, and the first wafer is located between the two-stage thermosetting adhesive layer and the second wafer; and the first wafer is electrically connected to the first pin group and the second by wire bonding The chip is electrically connected to the second pin group and the first chip is electrically connected to the second chip, and the first chip is electrically connected to the second pin group through the second chip. A semiconductor packaging structure includes: a lead frame, including a first pin group and a second pin group, wherein the first pin The group includes a plurality of first pins; a two-stage thermosetting adhesive layer is provided on one side of the first pin group and further fills the gap between any two adjacent ones of the plurality of first pins Inside; the first chip is attached to the two-stage thermosetting adhesive layer to connect the first pin group through the two-stage thermosetting adhesive layer, and the first chip is electrically connected to the first pin Group and the second pin; and an encapsulating colloid covering the lead frame, the two-stage thermosetting adhesive layer and the first chip, wherein the lead frame further includes a bus bar, which is located at the first lead Between the foot group and the second pin group, the end of the first chip extends from the first pin group toward the second pin group and stops at the bus bar and the second Between the pin groups, and the first chip is electrically connected to the bus bar. The semiconductor packaging structure as described in item 6 of the patent application scope further includes: a carrier, which is disposed on the other side of the first pin group and is covered by the packaging colloid, the first chip and the Carriers are respectively located on opposite sides of the first pin group, wherein the carrier covers the gap between any two adjacent ones of the plurality of first pins and is filled in the plurality of first pins The two-stage thermosetting adhesive layer in the gap between any two neighbors contacts the carrier. The semiconductor packaging structure as described in item 6 of the patent application scope further includes: a second chip attached to the first chip and covered by the packaging gel, the first chip is located in the two-stage thermosetting Between the glue layer and the second wafer, Wherein the first chip is electrically connected to the first pin group, the second chip is electrically connected to the second pin group, and the first chip is electrically connected to the second chip, so that The first chip is electrically connected to the second pin group through the second chip.

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