TWI690055B - Memory device and method for fabricating the same - Google Patents

Abstract

A memory device including a substrate, a non-doped semiconductor layer, a plurality of contact portions and a metal-stacking layer is provided. The substrate includes a plurality of word lines and a plurality of isolation structures. The non-doped semiconductor layer is disposed on the substrate. The contact portions are adjacent to the non-doped semiconductor layer and in direct contact with the substrate. The metal-stacking layer is disposed on the substrate. A portion of the metal-stacking layer is disposed on the non-doped semiconductor layer and in direct contact with the contact portions.

Description

Memory device and its manufacturing method

The disclosed embodiments relate to a memory device and a method of manufacturing the same, and particularly to a memory device having an undoped semiconductor layer and a method of manufacturing the same.

Dynamic random access memory (DRAM) devices are widely used in consumer electronics products, such as personal computers, smart phones, and tablet computers. In general, the step of manufacturing a DRAM device may include forming a metal oxide semiconductor (MOS) transistor and a contact on the substrate, and then forming a capacitor on the contact. The capacitor can be electrically connected to the substrate and the MOS transistor through a contact.

In most DRAM devices, a doped polysilicon/metal stack can be used as the bit line structure. However, due to the high height of the bit line structure, this structure may result in high parasitic capacitance.

In some examples, the doped polysilicon/metal stacked bit line structure may be replaced with a metal bit line structure to reduce high parasitic capacitance. However, this structure can The gap between the cell area and the peripheral area of the DRAM device can be increased. Therefore, the difficulty of the manufacturing process is increased.

According to some embodiments of the present disclosure, a method for manufacturing a memory device is proposed. The manufacturing method of the memory device includes providing a substrate. The substrate includes a complex digital element line and a complex isolation structure. The manufacturing method of the memory device also includes forming a semiconductor layer on the substrate. The manufacturing method of the memory device further includes patterning the semiconductor layer and the substrate to form a plurality of trenches. The trench exposes a portion of the substrate. The manufacturing method of the memory device includes forming a doped material layer on the semiconductor layer and filling the trench. The manufacturing method of the memory device also includes removing a portion of the doped material layer to form a plurality of contact portions such that the top surface of each contact portion is aligned with or lower than the top surface of the semiconductor layer. The manufacturing method of the memory device further includes forming a metal stacked layer on the semiconductor layer. The metal stack layer is in direct contact with the contact part.

According to some embodiments of the present disclosure, a memory device is proposed. The memory device includes a substrate, an undoped semiconductor layer, a plurality of contact portions, and a metal stack layer. The substrate includes a complex digital element line and a complex isolation structure. The undoped semiconductor layer is disposed on the substrate. The contact portion is adjacent to the undoped semiconductor layer and directly contacts the substrate. The metal stack layer is disposed on the substrate. A part of the metal stacked layer is disposed on the undoped semiconductor layer and directly contacts the contact part.

100: memory device

10: substrate

10-1: Unit area

10-2: surrounding area

12: Isolation structure

14: Silicon oxide layer

16: Silicon nitride layer

21: Photoresist layer

22: photoresist layer

23: Photoresist layer

24: photoresist layer

25: photoresist layer

30: Dielectric layer

31: The first dielectric layer

32: Second dielectric layer

34: Semiconductor layer

34T: top surface

36-1: First doped semiconductor layer

36-2: Second doped semiconductor layer

38: Mask layer

40: Groove

42: Spacer

44: doped material layer

46: Contact part

46T: top surface

48: metal stack

48-1: Ti disilicide layer

50: bit line

52: brake wire

54: capacitor contact

A-A’: Section line

WL: character line

The disclosed embodiments will be described in detail below in conjunction with the accompanying drawings. It should be noted that the various feature parts are not drawn to scale and are used for illustration only. In fact, the size of the element may be enlarged or reduced to clearly show the technical features of the disclosed embodiments.

1 to 15 show cross-sectional views of various stages of forming a memory device according to an embodiment of the present disclosure.

FIG. 16 is a partial top view of a memory device according to an embodiment of the present disclosure.

Fig. 17 is a partial cross-sectional view of the memory device taken along line B-B' in Fig. 16;

First, as shown in FIG. 1, a substrate 10 is provided. In some embodiments, the material of the substrate 10 may include (but is not limited to) element semiconductors (eg, may include silicon or germanium), compound semiconductors (eg, may include tantalum carbide (TaC), gallium arsenide (GaAs), indium arsenide (InAs) or indium phosphide (InP)), alloy semiconductors (e.g. may include silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP) or gallium indium phosphide (GaInP)), other suitable Semiconductors or combinations of the foregoing, but the disclosed embodiments are not limited thereto. In some embodiments, the substrate 10 may be a semiconductor-on-insulator (SOI) substrate.

In this embodiment, the substrate may include a complex number line WL and a complex isolation structure 12. The word line WL and the isolation structure 12 may be buried in the substrate 10, but the disclosed embodiments are not limited thereto. For example, as shown in FIG. 1, a pair of adjacent word lines WL may be disposed between two isolation structures 12.

In some embodiments, the isolation structure 12 may be a shallow trench isolation (STI), and the material of the isolation structure 12 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, etc. The disclosed embodiments are not limited thereto. The isolation structure 12 can be formed through an etching process and a deposition process.

In some embodiments, the material of the word line WL may include conductive materials, such as amorphous silicon, polysilicon, metal, metal nitride, conductive metal oxide, etc. However, the embodiments of the present disclosure are not limited thereto. The character line WL can be formed through an etching process and a deposition process.

In some embodiments, as shown in FIG. 1, a silicon oxide layer 14 and a silicon nitride layer 16 may be formed on the substrate 10 in sequence. Here, the silicon oxide layer 14 and the silicon nitride layer 16 can be formed through a deposition process.

In this embodiment, the substrate 10 can be divided into a unit area 10-1 and a peripheral area 10-2. As shown in FIG. 2, a photoresist layer 21 can be formed on the substrate 10 (silicon nitride layer 16) in the cell region 10-1, and the silicon oxide layer 14 and nitrogen in the peripheral region 10-2 can be formed The siliconized layer 16 is removed. For example, the silicon oxide layer 14 and the silicon nitride layer 16 in the peripheral region 10-2 can be removed through a patterning process. In some embodiments, the aforementioned patterning process may include, but is not limited to, a lithography process (eg, coating the resist), soft baking, exposure, post-exposure baking, developing, other suitable processes or a combination of the foregoing processes), etching processes (e.g., wet etching Process, dry etching process, other suitable processes or a combination of the aforementioned processes), other suitable processes or a combination of the aforementioned processes.

As shown in FIG. 3, a dielectric layer 30 is formed on the substrate 10 in the peripheral region 10-2. In some embodiments, the material of the dielectric layer 30 may include (but is not limited to) silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), hafnium silicon oxynitride (HfSiON), other suitable Dielectric materials or combinations of the foregoing materials. In some embodiments, oxidation, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), other suitable processes, or a combination of the foregoing processes may be used. The dielectric layer 30 is formed on the substrate 10 in the peripheral region 10-2, but the disclosed embodiment is not limited thereto.

As shown in FIG. 4, in some embodiments, a portion of the dielectric layer 30 may be removed. For example, a photoresist layer 22 can be formed on the substrate 10 (silicon nitride layer 16), and a portion of the dielectric layer 30 (in the peripheral region 10-2) can be removed. Similarly, a portion of the dielectric layer 30 can be removed through a patterning process. In some embodiments, the aforementioned patterning process may include, but is not limited to, a lithography process (eg, resist coating, soft baking, exposure, post-exposure baking, development, other suitable processes, or a combination of the aforementioned processes ), Etching process (eg, wet etching process, dry etching process, other suitable processes or a combination of the foregoing processes), other suitable processes or a combination of the foregoing processes.

As shown in FIG. 5, in some embodiments, the dielectric layer 30 may be formed on the substrate 10 in the peripheral region 10-2 again to form a first dielectric layer 31 and a second dielectric layer 32 . Here, the second dielectric layer 32 is thicker than the first dielectric layer 31. For example, the thickness of the first dielectric layer 31 may be about 2 nm to 3 nm, and the thickness of the second dielectric layer 32 may be about 5 nm to 6 nm, but the disclosed embodiments are not limited thereto. In other embodiments, the steps in FIGS. 4 and 5 may be omitted, so that the first dielectric layer 31 and the second dielectric layer 32 have the same thickness.

As shown in FIG. 6, a semiconductor layer 34 can be formed on the substrate 10. In more detail, the semiconductor layer 34 may be disposed on the silicon nitride layer 16 in the cell region 10-1, and may be disposed on the dielectric layer 30 (eg, the first dielectric layer 31 and the On the second dielectric layer 32). Here, the semiconductor layer 34 may be an undoped semiconductor layer, such as an undoped polysilicon layer. That is, the silicon oxide layer 14 and the silicon nitride layer 16 may be disposed between the substrate 10 (in the cell region 10-1) and the undoped semiconductor layer 34. However, the disclosed embodiments are not limited thereto. In some embodiments, the semiconductor layer 34 may be a silicon germanium (SiGe) layer, which has a high resistivity.

As shown in FIGS. 7 and 8, in some embodiments, the semiconductor layer 34 in the peripheral region 10-2 may be doped. In more detail, a photoresist layer 23 may be formed on the semiconductor layer 34 and expose a portion of the semiconductor layer 34 on the first dielectric layer 31 (that is, the cell region 10- 1 in the semiconductor layer 34 and in the second Semiconductor layer 34 on the electrical layer 32), and then, boron (B) ions can be doped into the semiconductor layer 34 on the first dielectric layer 31 by ion implantation or plasma doping To form a first doped semiconductor layer 36-1 shown in FIG. 7. Next, a photoresist layer 24 may be formed on the semiconductor layer 34 and expose a portion of the semiconductor layer 34 on the second dielectric layer 32 (that is, the photoresist layer 24 may cover the cell region 10-1 Semiconductor layer 34 and the semiconductor layer 34 on the first dielectric layer 31), then, phosphorus (P) ions can be doped into the semiconductor layer 34 on the second dielectric layer 32 by ion implantation or plasma doping To form a second doped semiconductor layer 36-2 shown in FIG. 8.

Here, the first doped semiconductor layer 36-1 may be disposed on the first dielectric layer 34-1 and has a first conductivity type (eg, P-type), and the second doped semiconductor layer 36-2 may be disposed It is on the second dielectric layer 34-2 and has a second conductivity type (for example, N-type), but the disclosed embodiments are not limited thereto.

As shown in FIG. 9, in some embodiments, a mask layer 38 may be formed on the semiconductor layer 34. In more detail, the mask layer 38 may be formed on the undoped semiconductor layer 34 in the cell region 10-1, and formed on the first doped semiconductor layer 36-1 and the second in the peripheral region 10-2 On the doped semiconductor layer 36-2. In some embodiments, the material of the mask layer 38 may include silicon oxide (SiO ₂ ), and may be through atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor The mask layer 38 is formed on the semiconductor layer 34 by low-pressure chemical vapor deposition (LPCVD), other suitable processes, or a combination of the foregoing processes, but the disclosed embodiments are not limited thereto.

As shown in FIG. 10, the semiconductor layer 34 and the substrate 10 may be patterned to form a plurality of trenches 40. In more detail, a photoresist layer 25 may be formed on the undoped semiconductor layer 34 (mask layer 38) in the cell region 10-1, and then the mask layer 38, the undoped semiconductor layer 34, Some portions of the silicon nitride layer 16 and the silicon oxide layer 14 are etched to form the trench 40. In this embodiment, the trench 40 may expose part of the substrate 10.

As shown in FIG. 11, in some embodiments, a spacer layer 42 may be formed on the sidewall of the trench 40. In some embodiments, the material of the spacer layer 42 may include, but is not limited to, silicon nitride (SiN) or silicon oxide (SiO ₂ ). In more detail, silicon nitride (SiN) (or silicon oxide (SiO ₂ )) material can be deposited in the trench 40 and on the mask layer 38, and then, silicon nitride (SiN) (or silicon oxide ( SiO ₂ )) the portion of the material on the mask layer 38 and the portion of the bottom surface of the trench 40 are removed (eg, etched) so that the spacer layer 42 can be formed on the sidewall of the trench 40. However, the disclosed embodiments are not limited thereto. In some embodiments, the steps in Figure 11 may be omitted.

As shown in FIG. 12, a doped material layer 44 can be formed on the semiconductor layer 34 (mask layer 38 ), and the trench 40 can be filled with the doped material layer 44. In more detail, a semiconductor material can be formed on the mask layer 38 and the trench 40 by deposition, and then, the semiconductor material is doped. In some embodiments, phosphorus (P) ions can be doped into the semiconductor material to form the doped material layer 44 through ion implantation, but the disclosed embodiments are not limited thereto. In other embodiments, the doped material layer 44 may be Crystal silicon is deposited on the mask layer 38 and formed in the trench 40. Here, the doped material layer 44 may have a low resistivity to be electrically connected to the substrate 10. Since the mask layer 38 can be disposed between the semiconductor material and the undoped semiconductor layer 34, the undoped semiconductor layer 34 can be protected by the mask layer 38 during the doping process (eg, ion implantation).

As shown in FIG. 13, a part of the doped material layer 44 may be removed to form a plurality of contact parts 46. For example, the portion of the doped material layer 44 above the mask layer 38 can be etched back by dry etching so that the top surface 46T of each contact portion 46 is aligned or lower than the top surface 34T of the undoped semiconductor layer 34 . Next, the mask layer 38 may be removed to expose the top surface 46T of each contact portion 46, the top surface 34T of the undoped semiconductor layer 34, the top surface of the first doped semiconductor layer 36-1, and the second The top surface of the doped semiconductor layer 36-2. In this embodiment, as shown in FIG. 13, the contact portion 46 may be adjacent to the undoped semiconductor layer 34 and directly contact the substrate 10.

As shown in FIG. 14, a metal stacked layer 48 can be formed on the semiconductor layer 34. In more detail, the metal stack layer 48 may be formed on the undoped semiconductor layer 34 in the cell region 10-1, and the first doped semiconductor layer 36-1 and the second doped semiconductor layer formed in the peripheral region 10-2 On the hetero semiconductor layer 36-2. In this embodiment, the metal stack layer 48 may directly contact the contact portion 46. In some embodiments, the metal stack layer 48 may be formed as a multilayer structure, and the metal stack layer 48 (multilayer structure) may include titanium, titanium nitride, tungsten, tungsten silicide, tungsten nitride, and titanium disilicide (TiS ₂ ) Or other suitable materials, but the disclosed embodiments are not limited thereto. For example, the metal stack layer 48 may include a titanium silicide (TiS ₂ ) layer 48-1. The titanium disilicide (TiS ₂ ) layer 48-1 can directly contact the contact portion 46 to reduce the interface resistance between the contact portion 46 and the metal stack layer 48.

As shown in FIG. 15, the metal stack layer 48 and the semiconductor layer 34 (the first doped semiconductor layer 36-1 and the second doped semiconductor layer 36-2) may be patterned to form the memory device 100. For example, the metal stack layer 48 may be etched to form a complex bit line 50 in the cell region 10-1, and the metal stack layer 48, the first doped semiconductor layer 36-1, and the second doped semiconductor layer 36-2 is etched to form a plurality of gate conductors 52 in the peripheral region 10-2. It should be noted that the undoped semiconductor layer 34 in the cell region 10-1 and the first doped semiconductor layer 36-1 and the second doped semiconductor layer 36-2 in the peripheral region 10-2 may also be used Patterned. In addition, the word line WL may be a buried gate region, and the substrate 10 may include a source/drain region and a channel region surrounding the buried gate region (not shown in detail in FIG. 15). That is, the contact portion 46 may directly contact the source/drain region of the substrate 10 in the unit region 10-1.

In some embodiments, the foregoing deposition process may include (but is not limited to) chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDCVD), plasma enhanced chemical vapor deposition Deposition (PECVD), low pressure chemical vapor deposition (LPCVD), other suitable processes, or a combination of the foregoing processes. In some embodiments, the foregoing etching process may include, but is not limited to, wet etching, dry etching, other suitable processes, or a combination of the foregoing processes.

Here, FIG. 15 may have a partial cross-sectional view showing the memory device 100 cut along the line A-A' of FIG. 16, but some components are not shown in FIG. 15. (For example, capacitor contact 54 and capacitor). It should be noted that, for the sake of simplicity, not all components of the memory device 100 are shown in FIGS. 16 and 17.

As shown in FIGS. 16 and 17, since the undoped semiconductor layer 34 can have a high resistivity (for example, about 10E3Ωm at room temperature), it can be closer to the insulator, and the wire force of the undoped semiconductor layer 34 ( electric line force) may be smaller than the doped semiconductor layer. Therefore, the bit line parasitic capacitance between the bit line 50 and the other bit line 50 or between the bit line 50 and the capacitor contact 54 can be effectively reduced.

According to the above description, the memory device 100 with the undoped semiconductor layer 34 according to the disclosed embodiment may have low parasitic capacitance. Furthermore, the manufacturing method of the memory device 100 according to the embodiment of the present disclosure can minimize the gap between the unit area 10-1 and the peripheral area 10-2 of the memory device 100.

The above summarizes the components of several embodiments, so that those with ordinary knowledge in the technical field to which the present disclosure belongs can better understand the viewpoints of the disclosed embodiments. Those with ordinary knowledge in the technical field to which this disclosure pertains should understand that they can design or modify other processes and structures based on the disclosed embodiments to achieve the same purposes and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which this disclosure belongs should also understand that such equivalent structures do not deviate from the spirit and scope of this disclosure, and they can do various things without violating the spirit and scope of this disclosure. Various changes, substitutions and replacements. Therefore, the scope of protection disclosed in this disclosure shall be deemed as defined by the scope of the attached patent application. In addition, although the present disclosure has been disclosed above in several preferred embodiments, it is not intended to limit the present disclosure.

100: memory device

34: Semiconductor layer

10: substrate

46: Contact part

10-1: Unit area

50: bit line

10-2: surrounding area

52: brake wire

12: Isolation structure

A-A’: Section line

14: Silicon oxide layer

WL: character line

16: Silicon nitride layer

Claims (13)

A manufacturing method of a memory device includes: providing a substrate, wherein the substrate includes a complex number of digital lines and a complex isolation structure; forming a semiconductor layer on the substrate; patterning the semiconductor layer and the substrate to form a complex number Trenches, wherein the trenches expose portions of the substrate; a doped material layer is formed on the semiconductor layer and fills the trenches; a portion of the doped material layer is removed to form a plurality of contact portions So that the top surface of each contact portion is aligned with or lower than the top surface of the semiconductor layer; and a metal stacked layer is formed on the semiconductor layer, wherein the metal stacked layer is in direct contact with the contact portions. The method for manufacturing a memory device as described in item 1 of the patent application scope, wherein before the step of forming the doped material layer on the semiconductor layer and filling the trenches, the manufacturing method further includes: separating a space A layer is formed on the sidewalls of the trenches. The method for manufacturing a memory device as described in item 1 of the patent application, wherein the substrate has a unit area and a peripheral area, and before the step of forming the semiconductor layer on the substrate, the manufacturing method further includes: A dielectric layer is formed on the substrate in the peripheral area, wherein the dielectric layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is thicker than the first dielectric layer . The method for manufacturing a memory device as described in item 3 of the patent application scope further includes: doping the semiconductor layer in the peripheral region; wherein the semiconductor layer on the first dielectric layer has a first The conductivity type and the semiconductor layer on the second dielectric layer has a second conductivity type, which is different from the first conductivity type. The method for manufacturing a memory device as described in item 3 of the patent application scope, wherein before the step of forming the dielectric layer on the substrate in the peripheral region, the manufacturing method further includes: a silicon monoxide layer and A silicon nitride layer is sequentially formed on the substrate; and the silicon oxide layer and the silicon nitride layer in the peripheral area are removed. The method for manufacturing a memory device as described in item 1 of the patent application scope, wherein before the step of patterning the semiconductor layer and the substrate, the manufacturing method further includes: forming a mask layer on the semiconductor layer. A memory device includes: a substrate including a complex digital element line and a complex isolation structure; an undoped semiconductor layer disposed on the substrate; a complex contact portion adjacent to the undoped semiconductor layer and directly contacting the Substrate; and A metal stacked layer is disposed on the substrate, wherein a portion of the metal stacked layer is disposed on the undoped semiconductor layer and directly contacts the contact portions. The memory device as described in item 7 of the patent application scope further includes: a spacer layer disposed between each contact portion and the undoped semiconductor layer. A memory device as described in item 7 of the patent application range, wherein the substrate has a unit area and a peripheral area, and the memory device further includes: a dielectric layer disposed on the substrate in the peripheral area; wherein The undoped semiconductor layer is disposed in the unit area. The memory device as described in item 9 of the patent application range, wherein the dielectric layer is divided into a first dielectric layer and a second dielectric layer, and the second dielectric layer is higher than the first dielectric layer thick. The memory device as described in item 10 of the patent application scope further includes: a first doped semiconductor layer disposed on the first dielectric layer; and a second doped semiconductor layer disposed on the second dielectric On the electrical layer; wherein the first doped semiconductor layer has a first conductivity type and the second doped semiconductor layer has a second conductivity type, the second conductivity type is different from the first conductivity type. The memory device as described in item 11 of the patent application range, wherein another part of the metal stack layer is disposed on the first doped semiconductor layer and the second doped semiconductor layer. The memory device as described in item 9 of the patent application scope further includes: A silicon oxide layer provided on the substrate in the unit area; and a silicon nitride layer provided on the silicon oxide layer; wherein the silicon oxide layer and the silicon nitride layer are provided on the substrate and the undoped Between semiconductor layers.

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