TWI670842B - Monolithically integrated resistive memory using integrated-circuit foundry compatible processes - Google Patents

Abstract

The present invention relates to a monolithic resistive memory using an integrated circuit casting compatible process, and a monolithic body of a resistive memory having a complementary metal oxide semiconductor using an integrated circuit casting process. A memory device is provided that includes a substrate and a monolithic stack comprising one or more complementary metal oxide semiconductor devices and a first insulator layer formed on the substrate. The single stone stack includes a plurality of layers fabricated over the first insulator layer as part of a single stone process. The plurality of layers includes a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or a via device. Additionally, the first metal layer is coupled to the second metal layer.

Description

Single-rock integrated resistive memory with integrated circuit casting compatible process Related application cross reference

The present application claims priority to U.S. Provisional Patent Application No. 61/937,412, filed on Feb. 6, 2014, entitled s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s U.S. Patent Application Serial No. 14/034,390, filed on Aug. 23, which is incorporated herein by reference to U.S. Patent Application Serial No. 13/58, No. 5,759, filed on Aug. Continuation; each of the above-referenced documents is hereby incorporated by reference in its entirety for all purposes in its entirety.

In general, the present invention relates to electronic memory. For example, the present invention describes a monolithic resistive memory that can be fabricated using an integrated circuit casting compatible process.

Resistive memory device means integrated circuit technology Recent innovations in the field. Although most of this technology is still in the development stage, various technical concepts used in the proposed resistive memory device and its manufacture have been exhibited by the inventors. The inventors believe that various resistive memory technologies and various techniques for fabricating various resistive memory devices exhibit convincing evidence to maintain significant advantages over competing technologies in the semiconductor electronics industry.

Over time, advances in technology have provided an increase in the number of semiconductor devices (e.g., transistors) that can be fabricated on a given geometric area of a semiconductor wafer. Increasing the number of semiconductor devices means increasing the memory capacity and processing power of semiconductor wafers and associated electronic devices.

In view of the above, the inventors desire to continue to develop the practical use and manufacture of resistive memory technology.

A brief summary of the invention is presented below to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. They are not intended to identify key or critical elements of the specification, nor the scope of any particular embodiments in the scope of the application. The intention is to present some concepts of the present invention in a simplified form as a

For the single-rock integrated resistive memory using the integrated circuit casting compatible process, a number of aspects of the inventive invention are provided. One embodiment relates to a memory device including a substrate comprising one or more complementary metal oxide semiconductor devices and a first formed on the substrate Insulator layer. The memory device also includes a single stone stack comprising a plurality of layers fabricated over the first insulator layer as part of a single stone process. The plurality of layers can include a first metal layer (eg, a first metallization layer), a second insulator layer, and a second metal layer (eg, a second metallization layer). The resistive memory device structure can be formed within the second insulator layer. In various embodiments, the resistive memory device structure is formed under the thermal budget of the one or more complementary metal oxide semiconductor devices. In a further embodiment, the resistive memory device structure can be implemented at least in part as a strut device. In other embodiments, at least a first portion of the first metal layer can be coupled to at least a second portion of the second metal layer.

According to some embodiments, the distance defined between the first metal layer and the second metal layer may be substantially similar to the distance between the second metal layer and the third metal layer. In other words, the thickness of the interlayer dielectric does not change to accommodate the formation of the resistive memory device structure in the second insulator layer. Thus, the embodiments discussed herein are compatible with existing integrated circuit (IC) designs.

In some embodiments, the resistive memory device structure can be fabricated at temperatures of 450 degrees Celsius or less. In some embodiments, the complementary metal oxide semiconductor circuit layer may use a gate dielectric material having a high relative dielectric constant compared to cerium oxide. In one embodiment, the gate dielectric material used in the complementary metal oxide semiconductor device may be a low-k dielectric (HBD3) of Applied Materials Producer® Black Diamond® (eg, k<=3.0).

The memory device structure is at least partially implemented as a pillar In one embodiment, the strut device can include a strut structure (contacting material) formed on top of the first metal layer and a collar structure disposed on top of the strut structure. The collar structure may comprise two or more layers of material disposed in a laminate structure above the strut structure. In one or more embodiments, the cross-section of the collar structure can be larger than the strut structure. In some embodiments, the two or more layers may comprise a first layer disposed in a cylindrical structure above the second cylindrical structure. The second cylindrical structure contacts the second metal layer at the first surface and the second surface is coupled to the first cylindrical structure. In this embodiment, the first cylindrical structure has a first side that contacts the strut structure and a second side that contacts the second surface of the second cylindrical structure. The first surface and the second surface can be located on opposite sides of the second cylindrical structure.

Another embodiment relates to a method of fabricating a memory device. In various embodiments, the method can be a cast compatible method (e.g., whether it is an existing or future variation, which is consistent with at least one integrated circuit casting manufacturing process). The method can include fabricating a monolithic stack that can include multiple layers. The fabrication of multiple layers can be carried out within the thermal budget of the substrate. In one embodiment, the substrate can be a substrate comprising one or more CMOS devices formed therein or thereon. Additionally, fabricating the multilayer can include providing a substrate comprising one or more complementary metal oxide semiconductor devices and fabricating a first insulator layer over the substrate. The method can also include fabricating a first metal layer over the first insulator layer. Additionally, the method can include fabricating an interlayer dielectric material layer over the first metal layer and fabricating a resistive memory device structure within the interlayer dielectric material layer, which can include Contains a pillar forming device. Additionally, the method can include fabricating a second metal layer over the resistive memory device structure.

According to another embodiment, fabricating a monolithic stack may comprise fabricating the monolithic stack at a temperature of approximately 450 degrees Celsius. In a further embodiment, the temperature can be 450 degrees Celsius or less. In various embodiments, the fabrication of the monolithic stack can comprise a range consisting of: about 450 degrees Celsius to about 400 degrees Celsius, about 400 degrees Celsius to about 350 degrees Celsius, and about 300 degrees Celsius to about 350 degrees Celsius. A single stone stack is fabricated at a selected temperature range in the group.

Yet another embodiment is directed to a memory cell that can include a substrate including one or more complementary metal oxide semiconductor devices and a first insulator layer formed on the substrate. The memory device can also include a single stone stack including a plurality of layers fabricated over the first insulator layer as part of a single stone process. The plurality of layers may include a first metal layer formed on a top surface of the substrate, a first conductive layer, a second insulator layer, and a second metal layer formed on the first metal layer. A resistive memory device structure can be formed within the second insulator layer and within a thermal budget of the one or more complementary metal oxide semiconductor devices. Additionally, the first metal layer is coupled to the second metal layer.

Yet another embodiment is directed to a memory device including a substrate comprising one or more complementary metal oxide semiconductor devices and a first insulator layer formed on the substrate. The memory device also includes a single stone stack comprising a plurality of layers fabricated over the first insulator layer as part of a single stone process. The plurality of layers may comprise a first metal a layer, a second insulator layer, and a second metal layer. A resistive memory device structure can be formed within the second insulator layer with the thermal budget of the one or more complementary metal oxide semiconductor devices. The resistive memory device structure can be implemented as a via device. Additionally, the first metal layer is coupled to the second metal layer.

Another embodiment relates to a method of fabricating a memory device. The method can include fabricating a monolithic stack comprising a plurality of layers, wherein the manufacturing is performed within a thermal budget of the substrate. The fabrication can include providing a substrate comprising one or more complementary metal oxide semiconductor devices and fabricating a first insulator layer over the substrate. Additionally, the fabricating can include fabricating a first metal layer over the first insulator layer and fabricating an interlayer dielectric material layer on the first metal layer. The fabricating further includes fabricating a resistive memory device structure within the layer of interlayer dielectric material, the fabricating comprising forming a via device and fabricating a second metal layer over the resistive memory device structure.

Yet another embodiment is directed to a memory cell including a substrate comprising one or more complementary metal oxide semiconductor devices, and a first insulator layer formed on the substrate. The memory unit includes a single stone stack including a plurality of layers fabricated over the first insulator layer as part of a single stone process. The plurality of layers include a first metal layer formed on a top surface of the substrate, a first conductive layer, a second insulator layer, and a second metal layer formed on the first metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal oxide semiconductor devices. Resistive memory The body device structure can be implemented as a through hole device. Additionally, the first metal layer is coupled to the second metal layer.

The following description and the annexed drawings set forth some example aspects of this specification. However, these aspects are only a part of the various ways in which the principles in this specification can be employed. Other advantages and novel features of the present invention will become apparent from the Detailed Description of the Drawing.

100,200,300,400‧‧‧ memory unit

102‧‧‧Complementary metal oxide semiconductor layer

104‧‧‧Single stone stacking

106,204,408‧‧‧First insulator layer

108,206‧‧‧First metal layer

110,210,412‧‧‧second insulator layer

112,212‧‧‧Second metal layer

114,214‧‧‧Resistive memory device structure

202‧‧‧Substrate

208‧‧‧First conductive plug

302,402‧‧‧M3 metal layer

304‧‧‧M6 metal layer

306‧‧‧V3 contact

308,410‧‧‧M4 metal layer

310‧‧‧V4 contact

312, 404‧‧‧M5 metal layer

314‧‧‧V5 contact

316‧‧‧ pillar device

318‧‧‧ memory components

320‧‧‧ pillar

322‧‧‧ collar

324‧‧‧Switch material layer

326‧‧‧Active metal layer

328‧‧‧Disability material layer

330‧‧‧Top cover

406‧‧‧ Conductive embolization

414‧‧‧through-hole device

416‧‧‧The first part of the through-hole device

418‧‧‧The second part of the through-hole device

420‧‧ ‧ embolization

422A‧‧‧First double-ended memory unit

422B‧‧‧Second double-ended memory unit

500,600,700‧‧‧ method

502, 504, 506, 508, 510, 512, 514, 602, 604, 606 ‧ ‧ steps

608, 610, 612, 614, 616, 618, 620, 622, 624, 626 ‧ ‧ steps

628, 630, 702, 704, 706, 708, 710, 712, 714, 716 ‧ ‧ steps

718, 720, 722, 724, 726, 728, 730, 732 ‧ steps

800,900‧‧‧Control environment

802‧‧‧ memory cell array

804‧‧‧ column controller

806‧‧‧ row controller

808‧‧‧ clock source

810‧‧‧ address register

812‧‧‧Input/Output Buffer

814‧‧‧ command interface

816‧‧‧ state machine

902‧‧‧ computer

904‧‧‧Processing unit

906‧‧‧System Memory

908‧‧‧System Bus

910‧‧‧ volatile memory

912‧‧‧ Non-volatile memory

914‧‧‧Disk storage

916‧‧‧ interface

918‧‧‧ operating system

920‧‧‧Applications

924‧‧‧Program Module

926‧‧‧ program data

928‧‧‧Input device

930‧‧‧Interface

934‧‧‧Adapter

935‧‧‧ codec

936‧‧‧output device

938‧‧‧Remote computer

940‧‧‧Memory storage device

942‧‧‧Network Information

944‧‧‧Communication connection

The various aspects, embodiments, and advantages of the invention will be apparent from the In the present specification, numerous specific details are set forth to provide a complete understanding of the invention. However, it should be understood that certain aspects of the subject invention may be practiced without these specific details or other methods, components, materials, and the like. In other instances, well-known structures and devices are shown in the form of block diagrams to help describe the subject invention.

1 is a block diagram illustrating an exemplary memory cell using an integrated circuit casting compatible process, in accordance with one or more embodiments of the present invention.

2 is a block diagram illustrating another example memory cell using an integrated circuit casting compatible process, in accordance with one or more embodiments of the present invention.

3 is a cross-sectional block diagram illustrating an intermediate stage in an exemplary memory structure for fabricating a memory device, in accordance with one or more embodiments of the subject disclosure, in accordance with one or more embodiments of the present invention.

Figure 4 illustrates a cross-sectional block diagram of an intermediate stage in another exemplary memory structure for fabricating a memory device, in accordance with one or more embodiments of the present invention.

Figure 5 is a flow chart illustrating an exemplary and non-limiting method of fabricating a memory cell including a resistive memory using an integrated circuit casting compatible process in accordance with various aspects of the present invention.

Figure 6 is a flow diagram illustrating an exemplary and non-limiting method of fabricating a memory cell including a memory forming a monolithic resistive memory as a pillar device, in accordance with various aspects of the present invention.

Figure 7 is a flow diagram illustrating an exemplary and non-limiting method of fabricating a memory cell including a monolithic resistive memory formed as a via device in accordance with various aspects of the present invention.

Figure 8 illustrates a block diagram of a sample operating environment that facilitates implementation of one or more of the disclosed embodiments.

Figure 9 illustrates a block diagram of an example computing environment that can be implemented in connection with various embodiments.

The present invention relates to a double-ended memory unit for digital or multi-level information storage. In some embodiments, the double-ended memory unit can include a resistive technique, such as a resistive-switching two-terminal memory cell. A resistive double-ended memory cell (also referred to as a resistive memory cell or a resistive memory), as used herein, includes a guide having an active region between two conductive contacts Electrically contacted circuit components. The active region of the double-ended memory device exhibits a plurality of stable or semi-stable resistance states with resistive memory, and each of the resistance states has a different resistance value. Moreover, each of the plurality of states can be formed or activated in response to a suitable electrical signal applied to the two conductive contacts. Suitable electrical signals may be voltage values, current values, voltage or current polarities, electrical or magnetic fields, etc., or suitable combinations thereof. An exemplary resistive double-ended memory device, although not comprehensive, may include resistive random access memory (RRAM).

The disclosed embodiments provide a filamentary-based memory cell. One embodiment of the filament-based memory unit can include: a contact material layer (eg, a p-type (or n-type) germanium (Si) support layer (eg, p-type or n-type polysilicon, p-type polysilicon, etc.)) a resistance switching layer (RSL) comprising a plurality of defect locations, and an active metal layer to promote particles (eg, metal ions and atoms that can be ionized in response to a suitable field or other suitable stimulus, or similar particles) ) is generated within the RSL, or at the boundary. Under appropriate bias conditions (eg, programming voltage), particles (eg, metal ions, atoms that can be ionized, etc.) can migrate to defect sites within the RSL to provide filaments that form ions into the RSL. At least a portion of the conductive filaments formed by the ions in the RSL are deformed under bias removal conditions. In some embodiments, in the absence of bias conditions with high electrical resistance, deformation of the filaments can include particles (eg, metal ions) that are trapped within the defect location, which become neutral particles (eg, metal atoms). . In other embodiments, the deformation of the filaments may include dispersion (or partial dispersion) of the particles within the RSL, the response of which The conductive path provided by the filament is broken under bias conditions. In still other embodiments, the deformation of the filaments can be in response to another suitable physical mechanism, or a suitable combination of the foregoing.

RSL (which may also be considered as a resistance switching medium (RSM) in the art) may include, for example, an undoped amorphous germanium layer, a semiconductor layer having intrinsic properties, and a suboxide of germanium (eg, SiOx, Wherein x has a value between 0.1 and 2), a non-stoichiometric oxide, a metal oxide (such as zinc oxide), and the like. Other examples of suitable materials for RSL may include Si _X Ge _Y O _Z (where X, Y, and Z are each a suitable positive integer), yttrium oxide (eg, SiO _N , where N is a suitable positive integer), amorphous矽 (a-Si), amorphous yttrium (a-SiGe), TaO _B (where B is a suitable positive integer), HfO _C (where C is a suitable positive integer), TiO _D (where D is a suitable positive Integer) and so on, or a suitable combination thereof.

Examples of the active metal layer may include, but are not limited to, silver (Ag), gold (Au), titanium (Ti), titanium nitride (TIN), or other suitable compound of titanium, nickel (Ni), copper (Cu), Aluminum (Al), chromium (Cr), tantalum (Ta), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), and palladium (Pd). Other suitable electrically conductive materials, as well as compounds or combinations of the foregoing or similar materials, may be used in the active metal layer in some aspects of the subject invention. In some embodiments, a thin layer of barrier material composed of titanium, titanium nitride, or the like may be disposed between the RSL and the active metal layer (eg, silver, aluminum, etc.). The details of other embodiments of the present invention, which are similar to the foregoing examples, can be found in the U.S. Patent Application Serial No. 11/875,541, filed on Oct. 19, 2007. And U.S. Patent Application Serial No. 12/575,921, filed on Oct. 8, 2009, and other references herein. Each of the above-identified documents is hereby incorporated by reference in its entirety in its entirety for the purposes of the disclosure.

In accordance with various disclosed embodiments of the present invention, the disclosed resistive device can be fabricated in a manner consistent with the casting compatible process. As used herein, casting compatible refers to having physical limitations associated with the manufacture of semiconductor-based devices in semiconductor fabrication facilities in the industry, such as Taiwan Semiconductor Manufacturing Corporation and others. Physical limitations include the wafer and the thermal budget (eg, maximum operating temperature) of the materials and metals constructed on the wafer prior to the custom process step. For example, where the wafer includes one or more metal layers or constructs, and the device model requires the metal layer to remain at tight position tolerances, the thermal budget may be set by the softening temperature of the metal to avoid loss of metal stiffness. Other physical limitations may include: manufacturing constraints of suitable ones in CMOS, nMOS, or pMOS, manufacturing tool sets for a particular metallization scheme (eg, etch/mask/grooving tool sets that may be used for aluminum, copper, etc.) limitations, or Physical properties of special process processes (eg, dispersibility of copper, oxidative properties of metals and semiconducting materials, etc.), or other industry casting limitations. Therefore, the term "cast compatible" means consistent with the process limitations of at least one industry semiconductor manufacturer.

In order to program a filament-based resistive memory cell, a suitable programming voltage can be applied to the memory cell (eg, a resistance switching layer) to cause a variable length and width of the conductive path or filament formation in the memory cell. The part of the resistor. This can cause the memory cells to switch from a relatively high resistance state to one or more relatively low resistance states. In some resistive devices The erase process can be accomplished by deforming the conductive filaments (at least a portion) such that the memory cells can return from a low resistance state to a high resistance state. In memory, such state changes can be associated with binary or multiple binary individual states. For an array of multiple memory cells, the words, bytes, pages, blocks, etc. of the memory cells can be programmed or erased to represent zero or one of the binary information, and by retaining these states for a period of time Affects storage binary information. In various embodiments, multiple levels of information (eg, multiple bits) may be stored in respective memory units.

Although resistive memory is still in the development stage, the inventors believe that resistive memory will replace traditional NAND and NOR flash memory devices, as well as replace other memory devices. The inventors have observed that the development of resistive memory has encountered bottlenecks in actual manufacturing, that is, thermal budget limitations of related devices (eg, the front end of in-line manufactured products). Thermal budget refers to the total amount of thermal energy transferred to a wafer during a particular temperature operation. In the process of manufacturing the resistive memory, for example, it may be desirable not to apply an excessive amount of heat or the like to a complementary metal oxide semiconductor (CMOS) device to adversely affect. Thus, a CMOS device within a substrate can add thermal budget constraints to the fabrication of memory components in accordance with a CMOS wafer or substrate (eg, by way of a back-end line process). Likewise, for example, thermal budget constraints should be considered during the fabrication of resistive memory devices in integrated circuits. In order to address the limitations of thermal budgets, some techniques have attempted to separate resistive memory from CMOS circuits. Therefore, in some cases, the resistive memory is formed on a wafer separated from the wafer on which the CMOS circuit is formed. After forming the resistive memory, the wafer It can be (turned upside down and combined) into a CMOS circuit. The inventors have realised that the above approach introduces additional cost and other challenges associated with fabricating resistive memory.

Another challenge associated with the integration of resistive memory is plasma damage from the resistive memory process. There may be a large number of complex plasticizing processes that affect the CMOS circuit from the perspective of plasma damage. The inventors believe that at least some of the plasma damage problems have not been successfully resolved.

Another challenge or limitation to the single-rock inclusion of resistive memory on top of a CMOS circuit includes the ability to use existing back-end line processes. The use of existing back-end line processes can alleviate or avoid RC delays in the back-end wiring during the fabrication of resistive memory (where "R" is the metal line resistance and "C" is the interlayer dielectric capacitance) . For example, changes in RC delay may make the electrical model useless. For example, some technologies use a custom process to integrate memory manufacturing into the back end of the line process. CMOS circuits can have multiple layers of wiring in the back end, and some techniques known to the inventors attempt to integrate memory elements into the back end. This process is complex and, until now, cannot be done without significantly changing the back-end line process. One or more of the aspects disclosed herein are directed to at least a subset of improvements that can be combined with existing backend line processes or thereon. In addition, the disclosed aspects are subject to thermal budget constraints that may be consistent with such processes.

The casting of an integrated circuit (IC) includes various devices and programs for incorporating resistive memory into the back-end line process. The inventors of the present disclosure are quite familiar with the compatibility of the backend materials associated with them. question. The one or more disclosed aspects can be used to fabricate a resistive memory device in a relatively simple manner relative to other resistive memory fabrication processes. For example, a memory stack, as discussed herein, in some embodiments, the memory stack can add only one or two additional layers, as compared to 20 or 30 additional layers used by other memory fabrication programs. This can significantly reduce the cost, complexity, and process overhead associated with manufacturing resistive memory as a back-end on-line process. In addition, the various aspects of the present invention can be easily scaled to the next generation node (e.g., to facilitate smaller memory cells, and thus greater wafer density) relative to other processes.

In addition, one or more of the present invention faces a smaller wafer size for one or more disclosed processes that can be used to process a resistive memory monolith to a front-end process (eg, a CMOS substrate). And lower costs. In addition, the fabrication of resistive memory devices can be performed using standard IC casting compatible manufacturing procedures. Various embodiments may also be implemented without changing the design after a monolithic body (eg, by a CMOS device) to account for changes in parasitic structure. The parasitic structure is part of a device (eg, a memory device) that reorganizes the structure into different semiconductor devices, which may cause the device to enter an unplanned operation. Moreover, in at least one disclosed embodiment, a manufacturing process product (eg, a memory device) is provided that can include a monolithic body of resistive memory in a CMOS circuit. Moreover, the fabrication method may include an integrated circuit casting compatible process in further embodiments (eg, a new or different process is not necessary. However, in an alternative embodiment, the process is further Step improvements should not be excluded from the scope of the various aspects of the invention). Moreover, the disclosed aspects can be performed at temperatures not exceeding about 450 degrees Celsius. For example, the temperature can be 450 degrees Celsius or lower. The plurality of faces may be performed at a temperature range selected from the group consisting of: about 450 degrees Celsius to about 400 degrees Celsius, about 400 degrees Celsius to about 350 degrees Celsius, and about 300 degrees Celsius to about 350 degrees Celsius.

Referring now to the drawings, FIG. 1 illustrates a block diagram of an exemplary memory cell 100 using an integrated circuit casting compatible process in accordance with one or more embodiments of the present invention. The memory cell 100 can include a complementary metal oxide semiconductor (CMOS) layer 102 and a single stone stack 104. In various embodiments, CMOS layer 102 can include memory driver circuitry, processing logic, gate arrays, communication layers, wired or wireless communication circuitry, and the like, or a suitable combination of the foregoing.

For example, in one embodiment, a substrate can be provided that includes one or more CMOS devices formed therein. In an alternate embodiment, one or more CMOS devices can be fabricated on or in the substrate. In another embodiment, the substrate can be provided in which one or more CMOS devices are formed, and further comprising fabricating one or more additional CMOS devices on or in the substrate.

A first insulating layer 106 may be formed over the CMOS layer 102 prior to fabrication of the single stone stack 104. The single stone stack 104 can include a plurality of layers that are sequentially fabricated over the CMOS layer 102. In some embodiments, a single stone stack 104 may also be formed over the first insulating layer 106, while in at least one alternative embodiment, the single stone stack 104 may be at least partially formed. In the first insulating layer 106. Moreover, one or more additional layers, although not specifically shown, may be included in the single stone stack 104 in accordance with alternative embodiments (eg, see Figures 2 and 3 and below).

According to some embodiments, the plurality of layers of the single stone stack 104 may include a first metal layer 108, a second insulating layer 110, and a second metal layer 112. The first metal layer 108 may be made of a first metal (eg, tungsten, aluminum, silver, gold, precious metal, or the like, or a suitable alloy of the foregoing). The second metal layer 112 may be formed of a second metal (eg, aluminum, which in one embodiment is titanium nitride). Additionally, the resistive memory device structure 114 can be fabricated within the second insulating layer 110. The resistive memory device structure 114 can create a contact between the first metal layer 108 and the second metal layer 112.

The resistive memory device structure 114 can be fabricated within the thermal budget of the CMOS layer 102. For example, the resistive memory device structure 114 can be fabricated at temperatures of 450 degrees Celsius or less. According to one embodiment, the temperature may be 450 degrees Celsius or lower. In various embodiments, the fabrication of the resistive memory device structure can be comprised of: from about 450 degrees Celsius to about 400 degrees Celsius, about 400 degrees Celsius to about 350 degrees Celsius, and about 300 degrees Celsius to about 350 degrees Celsius. Manufactured within a range of temperatures selected in the range group.

The inventors believe that the dielectric constant imposes limitations, and thus the construction of a resistive memory device with a low thermal budget can provide lower manufacturing costs compared to other high temperature memory fabrication processes because of the fabrication of such other high temperature memories. The program has high temperature components, as described above, and must be CMOS is manufactured separately and does not act as a single stone process for the CMOS wafer. As an example, the gate dielectric material for the CMOS device may be a low-k dielectric of Applied Materials Producer Black Diamond (HBD3) (eg, K <= 3.0), although the invention is not limited to this example.

In one embodiment, the resistive memory element structure 114 may remain at a defined distance between the first metal layer 108 and the second metal layer 112. For example, when the resistive memory device structure 114 is formed, the distance between the first metal layer 108 and the second metal layer 112 remains approximately the same. In other words, if the resistive memory device structure 114 is to be included in the established fabrication process, the distance between the first metal layer 108 and the second metal layer 112 will not significantly increase. In some embodiments, the distance between the first metal layer 108 and the second metal layer 112 is between the second metal layer 112 and the third metal (not shown, but see, for example, Figures 3 and 4 and below) The distance is the same.

In one aspect, the resistive memory device structure 114 can be implemented as a strut device. For example, the strut device can include a first portion of the resistive memory device structure 114 formed on the first metal layer 108. The strut device can also include a second portion (eg, an oversized layer) formed from a plurality of adjacent materials (eg, the second portion includes a plurality of layers of adjacent materials). In some embodiments, the layers of material are cylindrical and substantially concentric, such as a first cylinder and a second cylinder. However, the invention is not limited to this embodiment. The second portion of the strut device can contact the second metal layer 112. Moreover, in at least one embodiment, the first portion may have a cross section of a cylindrical shape or a substantially cylindrical shape, a polygonal shape, or an approximately polygonal shape (example) For example, when viewed from the top or bottom, it has a defined perimeter. Additionally, the second portion can have a larger perimeter than the defined perimeter of the first portion (eg, a larger diameter, a larger radius, etc.). In one or more embodiments, the first portion can be a cylinder having a first diameter (or approximately a cylinder) and the second portion can include a one formed from one or more adjacent materials above the first portion A series of cylinders (or approximately cylindrical) and having at least one additional diameter that is greater than a first diameter of the first portion of the strut device.

In other embodiments, as used herein, a structure or device referred to as a "cylinder" may alternatively or additionally include a polygonal or approximately polygonal shape. In another example, a structure or device referred to as a cylinder may alternatively or additionally include an oval or approximately oval shape. Moreover, such structures or devices may alternatively have a conical shape, an approximately conical shape, and the like, and so on. In another example, such a structure or device may be approximately polygonal (eg, a polygon having at least one partially rounded edge, or having at least one partial fillet, or multiple partial rounded edges, or multiple partial rounded corners) Polygon, or a combination of the aforementioned). In another example, the structure or device can have at least one non-linear side, such as a curved side. In a further example, the structure or device may have some non-sharp edges or some non-sharp sides. In yet another example, the structure or device can be an approximately polygonal object, a convex polygon having at least one non-linear side, or a convex polygon having at least one non-sharp edge. In some embodiments, the area of the cross section may be substantially similar or different. Therefore, it should be understood that the reference to the particular structure of the structure or device should be considered as illustrative and should not be construed as limiting the invention.

In one example, the second portion of the strut device can include a first cylinder (eg, a collar having a larger diameter or circumference than the first portion of the strut device), which can have a position a first side and a second side of opposite ends of a cylinder. The strut device can include a second cylinder that can have a first surface and a second surface that are located on opposite sides of the second cylinder. The first side of the first cylinder can contact the first portion of the strut device (eg, the strut) and the second side of the first cylinder can contact the second surface of the second cylinder. The first side of the second cylinder may contact the second metal layer 112 (see, for example, the cut-out portion 318 of Figure 3 and below).

According to an embodiment, the resistive memory device structure 114 can be implemented in a post-type device that includes a strut structure. The pillar structure can be formed of a conductive material. In some embodiments, the strut structure can include a prismatic structure (parallel base) having a cross-sectional pattern such as a circle, an approximately polygonal shape, an oval shape, and the like. In one example, the first cylinder is formed from a switching material and the second cylinder is formed from another electrically conductive material. In one facing, the conductive material of the pillar structure and the second cylinder are different materials. However, depending on some aspects, the material of the strut structure and the second cylinder may be the same material or a similar material.

According to one embodiment, the strut device may be formed at least in part by a through hole (which is created by forming holes, voids, etc. in other materials) and filled with one or more layers of material or material (in such a In this case, it may also be referred to herein as a through hole device. In one embodiment, the pillars may be at least partially formed by filling at least a subset of the vias (eg, filling a subset of the holes, voids, etc.) Device. In a further embodiment, the strut device can include a via liner formed from a material deposited over a surface of other material exposed through the via. The via liner material may be selected from the group consisting of cerium oxide (SiOx), a compound of SiOx and titanium oxide (TiOx), and a compound of SiOx and aluminum oxide (AlOx), or the like, or a suitable combination thereof. According to one embodiment, the via device may be filled (on the liner material), the materials selected of which include: aluminum, aluminum and copper, aluminum containing titanium nitride, aluminum containing titanium or titanium nitride, nitrogen Titanium, aluminum and copper or titanium nitride, or a suitable combination thereof, or a similar material.

In some embodiments, returning to the second portion of the reference strut device, the first cylinder can have a first thickness and the second cylinder can have a second thickness that is different than the first thickness. Therefore, the first cylinder can be thicker than the second cylinder. However, depending on the other orientation, the first cylinder can be thinner than the second cylinder.

2 is a block diagram illustrating another example memory cell using an integrated circuit casting compatible process, in accordance with one or more embodiments of the present invention. The memory cell 200 can include a substrate 202, a first insulating layer 204, and a first metal layer 206 formed over the first insulating layer 204 and a top surface of the substrate 202. In various embodiments of the invention, substrate 202 can be a complementary metal oxide semiconductor (CMOS) substrate having one or more CMOS compatible devices. Further, the first metal layer 206 may be formed of tungsten, aluminum, or the like.

In various embodiments, CMOS layer 102 can include memory driver circuitry, processing logic, gate arrays, and the like. For example, in one implementation In an example, a substrate 202 can be provided that includes one or more CMOS devices formed therein. In an alternate embodiment, one or more CMOS devices can be fabricated with at least a portion of the substrate or a portion over the substrate. In another embodiment, the substrate can be provided in which one or more CMOS devices are formed, and further comprising fabricating one or more additional CMOS devices on or in the substrate.

In some embodiments, the first conductive plug 208 can be formed within the first insulating layer 204. A first conductive plug 208 (eg, tungsten) can electrically connect the substrate 202 and the first metal layer 206.

The second insulating layer 210 may be formed on a top surface of the first metal layer 206. The second metal layer 212 may be formed over the second insulating layer 210. The first metal layer 206, the second metal layer 212, and the subsequent metal layer may be formed of a metal. Additionally, the resistive memory device structure 214 can be formed within the second insulating layer 210. Moreover, as shown, the resistive memory device structure 214 can be formed within the first metal layer 206 and at least a portion of the first insulating layer 204. The resistive memory device structure 214 can create contact between the first metal layer 206 and the second metal layer 212. Resistive memory device structures 214 can be formed using integrated circuit casting compatible processes (e.g., using existing integrated circuit casting tools), depending on the various aspects discussed herein.

Forming the resistive memory device structure 214 according to one aspect can include maintaining a defined distance between the first metal layer 206 and the second metal layer 212. For example, when forming the resistive memory device structure 214, the distance for separating the first metal layer 206 from the second metal layer 212 is maintained at approximately the same distance before the resistive memory device structure 214 is formed. from.

According to another embodiment, the resistive memory device structure 214 can be implemented in the form of a through-hole device. The through-hole device can be one of many different configurations including, but not limited to, via structures (eg, holes, voids, etc.), channels, penetrations, and the like. The via structure may be lined with aluminum, copper, silver, a suitable compound, or a suitable combination of the foregoing. In some embodiments, the liner of the via structure may be a deposition having a substantially uniform thickness over a surface exposed by a via structure/channel/through or the like, which may be 20 nm or less, in In some embodiments, it may be comprised of a thickness selected from a range of ranges: from about 15 nm to about 20 nm, from about 10 nm to about 15 nm, from about 5 nm to about 10 nm, and less than about 1 nanometer to about 5 nanometers. Additionally, the via structure can include at least a portion that is fabricated from a conductive material.

FIG. 3 illustrates a cross-sectional block diagram of an intermediate stage in an exemplary memory structure 300 for fabricating a memory device, in accordance with one or more embodiments of the present invention. The memory structure 300 can include a resistive memory. One or more vertical contacts of memory structure 300, such as V4 contact 310, may be replaced with a strut device or a through-hole device, depending on a variety of alternative or additional aspects. Accordingly, the memory structure 300 is not limited to a number of positions of the strut type device shown in FIG.

It should be noted that the memory architecture 300 is shown to be disposed between a first set of metals (M3 metal layer 302) and a second set of metals (M6 metal layer 304). For simplicity, it is included under the M3 metal layer 302 (eg, metal M1, metal M2, gate level components, CMOS circuitry, etc.) The various components of memory structure 300 are not shown or described. Additionally, an additional metal layer over the M6 metal layer 304 can be included in the memory structure 300, but is not shown or described for the sake of simplicity.

The first set of vertical contacts (V3 contact 306) may connect portions of the M3 metal layer 302 to portions of the third set of metals (M4 metal layer 308). Additionally, a second set of vertical contacts (V4 contacts 310) may connect portions of the metal layer 302 of M3 to portions of the fourth set of metals (M5 metal layers 312). Additionally, another set of V4 contacts 310 (although not specifically shown) may connect portions of the M4 metal layer 308 to portions of the M5 metal layer 312. Additionally, a third set of vertical contacts (V5 contacts 314) may connect portions of the metal layer 312 of M5 to portions of the M6 metal layer 304.

Between the M4 metal layer 308 portion and the M5 metal layer 312 portion is depicted a memory element 318. According to one embodiment, the memory element can be a strut device 316. It should be noted that while the strut device 316 is illustrated between the M4 metal layer 308 and the M5 metal layer 312, one or more post devices may be formed elsewhere within the memory structure 300. For example, one or more post-type devices may be formed between the M3 metal layer 302 and the M4 metal layer 308, between the M5 metal layer 312 and the M6 metal layer 304, or between other sets of metals, or other metal back end layers. Between (not shown).

Additionally, a strut-type device can be formed between sets of metals. For example, at least one strut device may be formed between the M4 metal layer 308 and the M5 metal layer 312, and at least another strut device may be formed between the M5 metal layer 312 and the M6 metal layer 304, or may be formed in other Between metal. Thus, the strut-type device can be sandwiched between any suitable metal layers, including any suitable other back-end metal layers, although the metal layers are not shown or described for the sake of simplicity.

During the manufacturing process of the memory element between the set of metal layers (eg, between the M4 metal layer 308 and the M5 metal layer 312), the metal layer in at least some of the disclosed embodiments may not be altered. The manufacture of the memory element 318 is performed with an interval (for example, defined in a back-end line process model or the like). For example, in such an embodiment, the height between each of the M4 metal layers 308 and each of the M5 metal layers 312 may be substantially the same as the height between the M3 metal layer 302 and the M4 metal layer 308. Additionally, in an embodiment in which a strut device forms a memory component 318 (which may include, for example, in one at least one such embodiment, a post (PL) and a collar (CL)), the total of the strut device The height may be the same or substantially the same as the gap between each of the M4 metal layer 308 and each of the M5 metal layers 312 prior to placement of the memory component. In this manner, existing dielectrics (e.g., dielectrics used between the various metal layers prior to placement of the memory or pillar devices) can continue to be used. Additionally, various other existing processes used in integrated circuits may continue to be used to fabricate the example memory structure 300.

In various disclosed embodiments, the resistive memory device can be monolithic on top of the substrate. In a further embodiment, the substrate can be a CMOS substrate having one or more CMOS compatible devices. In one or more other embodiments, the disclosed memory device can be a resistive double-ended note that is partially or fully compatible with existing CMOS fabrication techniques. Recalling the device. Thus, some or all of the disclosed memory devices can be fabricated with low manufacturing cost, limited rework, etc., to achieve high density and high efficiency double-ended memory that the inventors believe can be fabricated, and can be combined with other memories. Body equipment or process technology is brought to market compared to fewer manufacturing problems.

To illustrate, some processes for integrated resistive memory may result in changes in dielectric thickness or back-end critical dimensions and, therefore, the capacitance of the memory device may change. Therefore, the electrical design documents of these other processes must be changed to cause consumption of precious resources (eg, time, cost, etc.). One or more aspects disclosed herein minimize these variations by adding or forming resistive memory on top of the CMOS circuit. In addition, the thickness of the interlayer dielectric (ILD) is maintained the same (or similar) as that between the back end metal layers (for example, as the metal layer 308 of the M4 and the metal layer 312 of the M5) to mitigate Or avoid changing the capacitance of the metal layer, which is compared to the capacitance assumed by the associated electrical design model.

In addition, as shown by the cut-out portion of the memory element 318 (dashed circle), the strut device (which may be placed between the metals of each group) may include a post 320 (labeled PL) and a collar 322 (labeled CL) ). For example, the struts 320 can be placed, and then a collar 322 including one or more components (eg, one or more collar elements) can be placed. In one example, the collar assembly can be a cylinder, a polygonal cross section, a three dimensional object having a cylindrical cross section, and the like. In one orientation, the collar can comprise a single three-dimensional object formed from a single material. In another aspect, the collar can have There are a plurality of articles comprising at least one completely different material stacked or placed on top of each other. In the other direction, the collar can have multiple objects, at least one of which approximates a geometric cross section (eg, a cylinder), but is not a true geometry.

In various embodiments, as shown in FIG. 3, collar 322 can include a layer of resistive switching material 324, such as an undoped layer of amorphous germanium material, non-stoichiometric tantalum oxide, and the like. The collar 322 may also include an active metal layer 326 (eg, silver, gold, aluminum, precious metal, etc., alloys of the foregoing, or suitable combinations thereof). In various embodiments, the collar 322 can include a thin barrier material layer 328 between the resistance switching material and the active metal material layer, such as titanium, tungsten, titanium nitride, and the like. In various embodiments, the cap 330 can be a conductive material (eg, titanium, tungsten, titanium nitride, etc.). The barrier material layer 328 or cap 330 may be a metal plug, in an alternative or additional embodiment (eg, a tungsten plug), may be in the memory element 318 and a portion of the metal layer M5 (or other suitable in an alternate embodiment) Electrical contact is provided between the metal layers). For example, after the pillar 320 and other materials of the collar 322 are formed in the via hole, the tungsten plug can be formed by filling tungsten in any space remaining in the via hole.

In one embodiment, the cylinder or other item of the collar may be of different sizes. For example, the first cylinder can be thicker than the second cylinder. In another example, the first cylinder can be thinner than the second cylinder. In such an embodiment, leakage along the sidewalls can be minimized by breaking the strut device 316 into a subset of multiple layers having different diameters (or perimeters, for non-geometric shapes). Flow path and better material can be achieved Package. In at least one embodiment, the struts 320 can be formed from a plurality of materials of the same size, substantially the same size, or different sizes.

The struts 320 can include a conductive material such as p-type polycrystalline germanium, p-type polycrystalline, germanium, and the like. In some embodiments, the bottom layer of collar 322 (eg, at least a portion of the first cylinder) is a switching material (eg, RSL or RSM described herein). However, in other embodiments, the switching material can be in a different layer of the collar 322 (eg, an intermediate layer, etc.). Additionally, a top portion of the collar 322 (eg, at least a portion of the second cylinder) can be an electrically conductive connection formed by a conductive material.

In accordance with one or more aspects of the present invention, the material used is a low thermal budget material that does not affect CMOS casting of integrated circuits below the 45 nm node (eg, high k gate dielectric metal gate process or other ). For example, the materials selected for the struts 320 and collar 322 can be processed within the thermal budget of the CMOS circuitry associated with the memory structure 300. In addition, the material can be processed within existing metal layer space models. In addition, the cell process is compatible with small nodes without affecting the CMOS circuitry.

In one embodiment, the memory structure 300 can be fabricated by forming a first insulating layer over a CMOS substrate and forming an M3 metal layer 302 over the first insulating layer. The M3 metal layer 302 can be formed into one or more sections of the M3 metal layer 302 by patterning and etching, trenching and filling, via etching and filling, and the like. A second insulating layer is formed over the M3 metal layer 302, and one or more via holes are formed in the second insulating layer. One or more vias may be filled with a conductive material to form a first set of conductive plugs 306. Square on the second insulating layer and the conductive plug 306 Form M4 metal layer 308. In a first embodiment, various layers of pillar-type device 316 may be deposited, patterned, and etched over M4 metal layer 408 to form pillar-type device 316 that may be embedded in a third insulating layer and ground The top surface of the third insulating layer and the strut device 316 is substantially coplanar. In the second embodiment, a third insulating layer may be formed over the M4 metal layer 308, and a set of vias, trenches, grooves, and the like may be formed in the third insulating layer. The vias/grooves/grooves may be deposited back and forth with the various layers of the strut device 316. Additional insulating material may be deposited and ground to the top surface of each of the strut devices 316, or alternatively the top surface of the various layers of the strut device 316 may be ground to be flush with the top surface of the third insulating layer. The M5 metal layer 312 can then be deposited and segmented to form a plurality of segments of the M5 metal layer 312. A fourth insulating layer may be deposited over the M5 metal layer, and one or more additional conductive vias 314 may be formed within the fourth insulating layer. Additionally, the M6 metal layer 304 can then be deposited and segmented to form multiple sections of the M6 metal layer 304.

Referring to Fig. 3, some resistive memory devices may employ pillars and collar structures sandwiched between two metal back end layers. The purpose of breaking up the strut device into at least two concentric cylindrical layers is to minimize leakage paths along the sidewalls and achieve better material encapsulation. However, memory devices may be limited to lithography because it is related to scaling. In at least some embodiments of the memory device structure of FIG. 3, the size of the technical node that establishes the memory device 316 can be the surface area that provides electrical contact between the post and the collar (or top cylinder).

In the art, this technique of establishing a memory unit The size of a node is often referred to as a critical dimension. This term is used in the same meaning throughout the disclosure. It should be understood, however, that the terms are not to be construed as limiting the scope of the disclosure or the appended claims. Because some embodiments will have a technology node established by one critical dimension (eg, electrical contact surface area between strut 320 and collar 322), while the technical nodes of other embodiments are by another critical dimension (eg, by The electrical contact surface area common to the memory device and the metal layer of the electrode and the switching layer of the memory device; see the technical node established in Figure 4 and below). Moreover, it should be understood that since the disclosed memory device can be scaled to less than 20 nanometers in some embodiments, and even to a technical node of 1 nanometer in other embodiments, the critical dimensions are not limited For a specific quantity.

In addition, scaling to a smaller topography can become quite expensive for a double-ended memory unit (eg, RRAM, etc.). With one or more aspects disclosed herein, the scalability of the dual-ended memory cell in a manufacturing device can be expanded without the need for more advanced lithography techniques. For example, a structure formed by a struts becoming through holes can be utilized, wherein the device dimensions are contact between a thin bottom electrode layer (eg, controlled by film thickness) and a via pad (eg, controlled by film thickness). Area controlled. One or more of the aspects disclosed herein can also effectively scale double-ended memory on CMOS by using the same or lower cost and lower resolution lithography tools.

4 is an illustration of an intermediate stage in another example memory structure for fabricating a memory device, in accordance with one or more embodiments of the present invention. Sectional block diagram of the segment. It should be noted that, similar to the memory structure 300 of FIG. 3, the memory structure 400 is shown to be disposed between a first set of metals (M3 metal layer 402) and a second set of metals (M5 metal layer 404). For the sake of simplicity, the various components of memory structure 400 included under M3 metal layer 402 (eg, metal M1, metal M2, gate level components, CMOS circuitry, etc.) are not shown or described. Additionally, multiple sets of metal over the M5 metal layer 404 can be included in the memory structure 400, but are not shown or described for the sake of simplicity. In various embodiments, metal layers 402, 404, 410 can be used as word lines, bit lines, source lines, data lines, or select lines for memory structure 400, etc., or a suitable combination of the foregoing.

In various embodiments, one or more metal layers 402, 404, 410 can be segmented into multiple segments of respective metal layers 402, 404, 420. For example, the M5 metal layer 404 (or the M3 metal layer 402, the M4 metal layer 410, or other metal layers not shown in FIG. 4) may be segmented into a plurality of corresponding segments of the M5 metal layer 404. In some disclosed embodiments, a first subset of segments may be connected to control circuitry (eg, power, ground, sense circuitry, etc.) of memory architecture 400, and a second subset of segments may be It can be electrically isolated from (direct) contact with the control circuit and remains floating. Thus, in some embodiments, a segment of the M5 metal layer 404 can be in contact (eg, unpowered, ungrounded, etc.) in contact with an electronic component (eg, a memory cell), while in other embodiments, the M5 metal The segments of layer 404 can be driven by control circuitry or sensing circuitry to act as a control contact or sense contact for the electronic component, or both. Metal layer segments 402, 404, 410 can be patterned and etched by various metal layers 402, 404, 410 form a through hole between the respective segments and fill the through hole with an insulating material, form a groove between the respective segments, fill the groove with an insulator material, or the like, or a suitable combination of the above.

The memory structure 400 can include a substrate having one or more CMOS devices (not shown) formed therein or thereon. In some disclosed embodiments, one or more metal layers and intermediate insulating layers may be formed (eg, deposited, etc.) on the top surface of the substrate and below the M3 metal layer 402. These metal layers and intermediate insulating layers can be patterned, etched, ground, slotted, etc. to form suitable electronic devices or electronic circuits. The circuit can provide electrical contact to a subset of the CMOS devices. In some embodiments, the circuitry can provide peripheral electronics or functionality or the like to a subset of the CMOS devices. However, in other embodiments, the memory structure 400 may have no intermediate layer between the substrate and the M3 metal layer 402, or some but not all of the intermediate layers described above, or some, but not all, suitable electronic devices. Or an electronic circuit to achieve the desired electronic device.

In a further embodiment, the first insulating layer 408 can be formed (eg, deposited, etc.) over the M3 metal layer 402. One or more conductive plugs 406 (eg, tungsten) may be formed in the first insulating layer 408. Conductive plug 406 can connect various portions of M3 metal layer 402 and associated portions of another set of metals (M4 metal layer 410). In one embodiment, the conductive plug 406 can be formed by creating a via in the first insulating layer 408 and filling at least a portion of the via with a selected conductive material (eg, tungsten, etc.). Other mechanisms for forming the conductive plug 406 are considered to be within the scope of the present disclosure, such as within the first insulating layer 408. A groove is formed and the groove is filled with a material selected for the conductive plug 406. While the conductive plug 406 is depicted as having a vertical side, it should be understood that this is for illustrative purposes only, and other geometries (or non-geometry) may also be implemented. Such as suitable inclined sides, curved sides, irregular sides, non-geometric sides, and the like.

An additional metal layer (M4 metal layer 410) may be formed over the first insulating layer 408. In one embodiment, at least a subset of the M4 metal layer 410 can be formed in direct electrical contact with the conductive plug 406. In a further embodiment, as described above, the M4 metal layer 410 can be segmented into a plurality of metal layer segments. In various embodiments, the M4 metal layer 410 can be made of a variety of metallic materials (eg, titanium nitride, tungsten, aluminum, etc.) or conductive germanium-containing materials (eg, p-type polysilicon, p-type germanium, doped矽锗, etc.) The conductive layer formed.

A second insulating layer 412 can be formed (eg, deposited) over the M4 metal layer 410. The one formed in the second insulating layer 412 may be a through-hole device 414 (eg, vias, vias, throughs, etc.). In one or more embodiments, the via device 414 can also be formed through the M4 metal layer 410 and into the first insulating layer 408. It should be noted that although the via device 414 is shown between a portion of the M4 metal layer 410 and a portion of the M5 metal layer 404, one or more via devices may be included elsewhere within the memory structure 400. . For example, one or more via devices may be located between M3 metal layer 402 and M4 metal layer 410, between M3 metal layer 402 and M5 metal layer 404, M5 metal layer 404 and M6 metal layer (not shown). Metal backend layer between, or in other groups Between (not shown), between a exposed metal layer and an unexposed metal layer, or in at least one embodiment, between the metal layer and the metal interconnect (eg, with conductive plugs 406 and metal layers) Electrical contact, or between two conductive plugs, or some other suitable orientation).

Additionally, additional via devices can be included between sets of metal layers. For example, at least one via device may be formed between the M4 metal layer 410 and the M5 metal layer 404, and at least another via device may be formed between the M5 metal layer 404 and the M6 metal layer (not shown), Or it can be formed between other metals or metal layers. Thus, the via device can be sandwiched between any suitable metal layers, including any other back metal layers, although such metal layers are not shown or described for the sake of simplicity.

The via device can be formed using a suitable etching technique, a grooving technique, or a similar technique for removing at least a subset of the materials of the stacked semiconductor film or layer. Similar to the memory structure 300 described in FIG. 3, in at least some of the disclosed embodiments, the via device is inserted between the metal interconnect groups (eg, between the M4 metal layer 410 and the M5 metal layer 404) During the manufacturing process, the spacing between the metal layers does not become wider or narrower, or does not substantially widen or narrow. For example, the height between each of the M4 metal layers 410 and the respective M5 metal layers 404 may remain constant or substantially unchanged. To illustrate, the height of the through-hole device can have the same or substantially the same overall height as the height between each of the M4 metal layer 410 and each of the M5 metal layers 404 prior to placement of the via device. In this manner, existing dielectrics can be used (eg, dielectrics used between sets of metal layers prior to placement of the via-type device) without changing or substantially changing. The expected capacitance between the metal layers. Additionally, various other existing processes used in the fabrication of integrated circuits may continue to be used to fabricate the example memory structure 400.

As shown, in some disclosed embodiments, the through-hole device 414 can include horizontal portions (or approximately horizontal portions) and vertical portions (or approximately vertical portions) that intersect each other. In the first embodiment, the second insulating layer 412 may be formed to an initial height that is substantially equal to the bottom surface of the horizontal portion of the through-hole device 414. After the via device 414 is formed, further deposition of the second insulating layer 412 may bring the second insulating layer 412 to the bottom surface of the M5 metal layer 404. Other embodiments may utilize other steps to achieve the above or similar orientation.

Once the second insulating layer 412 is formed, vias (or, for example, trenches, grooves, etc.) may be formed in the second insulating layer 412 to form a gap at the depicted vertical portion. The via device 414 (or a plurality of via devices) may cause portions of the sidewalls of the respective insulating or metal layers to be exposed. By filling at least a subset of the exposed sidewall portions with respective layers of via devices 414, the double-ended memory cells can be in a non-perpendicular direction (eg, horizontal) relative to the orientation of FIG. Formed in directions, substantially horizontal, oblique, etc.). For example, in at least some embodiments, the first double-ended memory cell 422A can be formed (left dashed ellipse) at the intersection of the left side of the via device and the M4 metal layer 410, while the second double-ended memory cell 422B can It is formed at the intersection of the right side of the via device 414 and the M4 metal layer 410. For example, the formation of the via device 414 can include thin film deposition by the first material or other suitable The technique forms the first portion 416. At least a subset of the remaining space formed by the vias may be filled by the second portion 418 of the via device 414, wherein the second portion 418 includes a second material that may be different than the first material.

In various embodiments, the second portion 418 is a layer of a resistance switching material, such as an undoped layer of amorphous germanium material, non-stoichiometric yttrium oxide, and the like. In one embodiment, the layer of resistive switching material can serve as a non-volatile switching element for the double ended memory cells 422A, 422B. The first portion 416 can be an active metal layer (eg, silver, gold, aluminum, etc.) that acts as a first electrode common to the dual-ended memory cells 422A, 422B. The via device 414 can also include a thin barrier material layer between the first portion 416 and the second portion 418, such as titanium, tungsten, titanium nitride, and the like. Additionally, various subsets of M4 metal layers 410 can be independently controlled, sensed, etc. to provide separate and respective second electrodes to the double-ended memory cells 422A, 422B, thereby enabling independent operation thereon.

In various embodiments, the plug 420 can be formed between the through-hole device 414 and the M5 metal layer 404. The plug 420 can be formed of a conductive material (eg, titanium, tungsten, titanium nitride, etc.). According to one aspect, the through-hole device can be formed using a tungsten plug process to join aluminum, copper, a suitable compound or alloy thereof, or any other suitable metallization scheme. For example, as discussed herein, tungsten plugs can be used to make metal contacts. According to one aspect, the second insulating layer 412 may be formed to have a height substantially corresponding to the bottom surface of the M5 metal layer 404 (whether before or after the via device 414 is formed), and the via hole may be formed in the second insulating layer 412 Inside and down The top surface of the via device 414 is exposed and exposed. The tungsten plug can be formed by filling the via with tungsten such that the top surface of the via 414 can be in direct electrical contact with the plug 420. In some embodiments, the top surface of the second insulating layer 412 can be ground to provide a top surface of the plug 420 that is flush or substantially flush with the top surface of the second insulating layer 412. An M5 metal layer 404 can then be deposited over the top surface of the plug 420 and the second insulating layer 412 such that at least a subset of the M5 metal layer 404 is in electrical contact with the plug 420. Thus, at least the subset of the M5 metal layer 404 can be in electrical contact with the top surface of the via device 414 by the plug 420.

As mentioned above, the via device 414 can form one or more double ended memory cells 422A, 422B along a non-perpendicular angular direction (eg, a tilt angle, etc.). Memory cells 422A, 422B may be created at respective junctions of the first portion 416 and the second portion 418 with the left and right subsets of the M4 metal layer 410. As a result, the critical dimensions of the two-terminal memory cells 422A, 422B can be established by a minimum common surface area that facilitates electrical conductivity through the various junctions. In one embodiment, the smallest electrical contact surface area may (respectively) be the sidewall surface of the M4 metal layer 410, which is associated with the respective portions of the second portion 418 of the via device 414 (as depicted in each dashed oval) Set direct electrical contact. Thus, controlling the thickness of the M4 metal layer effectively scales the respective respective double-ended memory cells 422A, 422B. Moreover, this thickness can be controlled using techniques of film thickness and, in at least some embodiments, can be accomplished without scaling the printed features using lithography. Compared to FIG. 3, for example, the layer of the M4 metal layer 410 can be formed more than the M4 metal layer 308 of FIG. Thin to form the double-ended memory cells 422A, 422B as smaller technology nodes. According to one aspect, the thinner the M4 layer, the smaller the device. Thus, the memory device can be scaled by controlling the thickness of the metal bottom electrode, for example, it can be controlled to less than 50 angstroms or 5 nanometers. In other embodiments, however, thinner or thicker (e.g., 20 nm, 1 nm, etc.) M4 layers are also contemplated. Examples of the material of the bottom electrode layer may include: tungsten, aluminum, or the like, or a suitable combination thereof.

In addition, the strut device 316 of FIG. 3 can be changed to the through-hole device 414 of FIG. In some embodiments, the lining of the through-hole device 414 can include a selection and switching layer. Additionally, the collar material of the through-hole device 414 can comprise a simple conductive material. Examples of the material for the pillar to become the through-hole backing layer may include: a compound of cerium oxide (SiOx), SiOx, and titanium oxide (TiOx), a compound of SiOx and aluminum oxide (AlOx), or the like, or a suitable combination thereof. Examples of the material for filling the pillar layer may include: a compound of aluminum, aluminum, and copper, a compound of aluminum, titanium, and titanium nitride, and a combination of aluminum and copper, aluminum, and copper or titanium nitride. Examples of materials for the top electrode (eg, the second metal layer 112 of FIG. 1) may include, but are not limited to, aluminum, titanium nitride, or other suitable compounds of aluminum and titanium nitride. In some examples, the top electrode can be formed from a number of other materials including: tantalum (Ta), tantalum nitride, copper, and the like, or a suitable combination thereof.

As shown, the vias may all pass (or in some embodiments partially pass) a second electrode metal (eg, M4 metal layer 410). The critical dimension may be a surface area that is in direct electrical contact between the second electrode metal (eg, M4 metal layer 410) and the via device 414. this In addition, this surface region can affect the resistivity of the double-ended memory cells 422A, 422B by limiting the current density through the cell. Because the vias can be formed to have various cross-sectional shapes or sizes, the shape/size of the vias for the via device 414 can also affect this critical dimension surface area, thereby affecting the resistivity of the dual-ended memory cells 422A, 422B. Thus, in at least one embodiment, the critical dimension can be at least partially adjusted by controlling the size or shape of the via for the via display 414.

According to some embodiments, the vias may be drilled through a plurality of bottom electrode (BE) stacks (eg, multiple metal layers) that may allow three (or other number) devices to be included in the same via. According to some aspects, the bottom electrode can be a semiconductor. In a further embodiment, the orientation along the tilt angle of the two-terminal memory cells 422A, 422B can be selected to provide an enhanced electric field (E-field) that can reduce the form of the vias relative to the planar device (for example, width or length).

In accordance with one or more of the disclosed aspects, a memory device structure can utilize smaller CMOS devices and can increase memory efficiency. Moreover, the various oriented memory device structures disclosed herein can be fabricated using materials that are already present in most IC foundries. In addition, the integrated solution can scale the device structure to 5 nm without the need to use a typical manufacturing tool set of 5 nanometers (or less) of technology nodes (eg, no further processing is required). For example, using a 44 nm or 193 nm lithography tool set, the disclosed device can be used to make devices below 20 nm.

According to one embodiment, the strut device or through-hole device may comprise one or more materials that are presented as a selector device, such as a selection device for Crossbar FAST (TM). In some embodiments, the selector device can include a selector layer, which can be a non-stoichiometric material having volatile, bipolar switching characteristics. Examples of suitable materials for the selection layer may include: SiO _X , TiO _X , AlO _X , WO _X , Ti _X N _Y O _Z, etc., or suitable combinations thereof, wherein x, y, and z may be suitable non-stoichiometric value. In at least one embodiment of the invention, the selector layer can be doped with metal during the fabrication process to achieve target resistance or conductance characteristics. As described above, the selector device may include the ion conductor layer 1 or the ion conductor layer 2. The ion conductor layer 1 or the ion conductor layer 2 may include a solid electrolyte (for example, silver-antimony-sulfur, copper-antimony-sulfur, silver-antimony-rhenium, copper-antimony-rhenium, etc.), a metal oxide alloy (for example, AgSiO). ₂ etc.), or the like.

In view of the exemplary illustrations described above, the process methods implemented in accordance with the disclosed subject matter will be more readily understood by reference to the following flowchart. Although the method has been illustrated and described as a series of blocks for purposes of illustration. It should be understood and understood, however, that the claimed subject matter is not limited by the order of the blocks, as some blocks may be present in a different order or in conjunction with other blocks depicted and described herein. Moreover, not all illustrated blocks are required to implement the methods described herein. In addition, it should be further understood that the methods disclosed in the entire specification can be stored on an article of manufacture to transfer and transfer the methods to the electronic device. The term "article of manufacture", as is conventional, is intended to encompass a computer program accessible from any computer-readable device, device-incorporated carrier, or storage medium.

Figure 5 illustrates an exemplary and non-limiting use of an integrated circuit casting compatible process including resistive in accordance with various aspects of the present invention. A flowchart of a method 500 of manufacturing a memory cell. At 502, method 500 can include fabricating a monolithic stack comprising a plurality of layers over a substrate. The monolithic stack can be fabricated over a substrate comprising a complementary metal oxide semiconductor circuit layer as part of a single stone process. In addition, the manufacture of multiple layers can be carried out within the thermal budget of the substrate.

Accordingly, at step 504, fabricating the monolithic stack can include providing a substrate comprising one or more complementary metal oxide semiconductor (CMOS) devices. For example, in one embodiment, the substrate can be configured to include one or more CMOS devices formed therein. In an alternate embodiment, one or more CMOS devices can be fabricated at least partially within or over the substrate. In another embodiment, a substrate can be provided with one or more pre-existing CMOS devices, and method 500 can further include fabricating one or more additional CMOSs within, on, or over the substrate. Device.

At step 506, a first insulator layer is fabricated over the substrate, and at step 508, a first metal layer is fabricated over the first insulator layer. The first insulator layer can be configured to electrically isolate the substrate from the first metal layer.

At step 510, an interlayer dielectric material layer is formed over the first metal layer. Additionally, at step 512, the resistive memory device structure can be fabricated within the layer of interlayer dielectric material. For example, a resistive memory device can be implemented as a strut-type device in electrical contact with at least a first metal layer. According to another example, the resistive memory device can be implemented as a through-hole device. In addition, in the present example, the through hole device may be formed to be at least A metal layer is in electrical contact.

At step 514, a second metal layer is fabricated over the resistive memory device structure. In various embodiments, the distance between the first metal layer and the second metal layer can be substantially similar to the distance between the second metal layer and the third metal layer. In other embodiments, method 500 can form a resistive memory device structure while maintaining a target distance between the first metal layer and the second metal layer (eg, a predetermined distance established by an electrical design model).

According to one embodiment, fabricating a monolithic stack may include fabricating a monolithic stack at a temperature of approximately 450 degrees Celsius. In a specific embodiment, a single stone stack can be fabricated at temperatures between about 400 and 450 degrees Celsius. In another embodiment, the monolithic stack can be fabricated at temperatures between about 350 and 400 degrees Celsius. In yet another embodiment, a single stone stack can be fabricated at temperatures between about 300 and 350 degrees Celsius.

6 is a flow diagram illustrating an exemplary and non-limiting method 600 of fabricating a memory cell including a monolithic resistive memory formed as a pillar device, in accordance with various aspects of the present invention. In some embodiments, the method 600 of FIG. 6 can be used to fabricate the memory unit 100 of FIG. 1, for example. In other embodiments, method 600 can be used to fabricate memory structure 300 of FIG.

The method 600 begins at step 602 by providing a substrate. The substrate may be a subset of the CMOS 102 of Figure 1 or the M3 metal layer 302 of Figure 3. In one embodiment, the provided substrate has a One or more of the CMOS devices. In an alternate embodiment, one or more CMOS devices can be fabricated on or in a substrate. In a further embodiment, the substrate can be configured to include one or more CMOS devices formed therein, and further, one or more additional CMOS devices can be fabricated on or in the substrate.

At step 604, a first metal layer is disposed over the substrate. In some embodiments, the first metal layer can be a subset of CMOS 102 of FIG. 1 or M3 metal layer 304 of FIG. For example, a first metal layer (eg, M3 metal layer 304) is provided as part of the substrate. In another example, a first metal layer (eg, M3 metal layer 304) is formed on top of a substrate comprising one or more CMOS devices. According to one embodiment, before the first metal layer is formed over the substrate, an insulating layer (eg, interlayer dielectric) is disposed on the substrate, and a first metal layer is formed over the insulating layer.

At step 606, the first metal layer can be covered by an interlayer dielectric. The interlayer dielectric may be, for example, the first insulating layer 106 of FIG. 1 or the first insulator layer. The interlayer dielectric is used for the electrically insulating metal layer. In one or more embodiments, the interlayer dielectric is a closely spaced space for electrically separating patterned traces (eg, metal word lines, bit lines, data lines, source lines, select lines, etc.) in a memory device. The dielectric material of the array. The interlayer dielectric can include an insulator having a relatively low (eg, close to 1) dielectric constant k. Having a low dielectric constant k minimizes capacitive coupling (eg, electrical crossover signals or effects) between adjacent metal lines. According to one aspect, the low-k dielectric has a dielectric constant k of less than 3.9 (cerium oxide) k value) of dielectric material.

At step 608, vias may be formed through or formed within the interlayer dielectric. The vias can be, for example, contacts, vertical contacts, conductors, and the like. In one embodiment, the vias may be formed in at least a portion of the interlayer dielectric. At step 610, the vias may be filled with a conductive material. For example, the via filled with the conductive material may be the V3 contact 306 of FIG. According to various embodiments, the via device can be formed using suitable etching techniques, slotting techniques, or similar techniques for removing materials of stacked semiconductor films or layers.

At step 612, a second metal layer can be formed over the interlayer dielectric and the via. The second metal layer may be the M4 metal layer 308 of FIG. According to one embodiment, the second metal layer can be patterned.

According to some embodiments, forming the second metal layer can include forming one or more discontinuities (eg, segments) in the second metal layer. In one embodiment, the discontinuity can be created by creating one or more vias between the subset of second metal layers. In another embodiment, the discontinuity may be formed by patterning the second metal layer, for example, a mask may be disposed over the second metal layer (eg, the M4 layer), but not included in the discontinuity Above the area of the two metal layers. The second metal layer can then be etched to remove material that is not covered by the mask, thereby providing discontinuities. Thereafter, the mask can be removed. According to an embodiment, the discontinuity in the second metal layer may be filled by a dielectric material.

At step 614, a layer of electrically conductive material can be formed. At step 616, the layer of conductive pillar material can be patterned to form a conductive structure (eg, Pillar device, pillar device, etc.). At step 618, the patterned conductive structure can be filled with an interlayer dielectric. Additionally, at step 620, the interlayer dielectric can be planarized to expose at least the top surface of the conductive structure.

At step 622, the material stack is deposited with layers of various materials. For example, the stack of materials can include a layer of resistive switching material, such as an undoped layer of amorphous tantalum material, non-stoichiometric tantalum oxide, and the like. The material stack may also include an active metal layer (eg, silver, gold, aluminum, etc.). Additionally, the material stack can include a barrier material layer between the resistance switching material and the active metal material layer, such as titanium, tungsten, titanium nitride, and the like. In various embodiments, the cap may be comprised of a conductive material (eg, titanium, tungsten, titanium nitride, etc.). At step 624, the material stack can be patterned to create a collar structure. In one or more embodiments, the stack of materials can be patterned and etched to form a stack of materials on top of the conductive structures of steps 616 and 618 above. Additionally, the material stack structure can be formed to have a first perimeter that is different than the length of the second perimeter of the conductive structure. This difference in length of the perimeter (the material stack has a first perimeter length and is stacked on top of the conductive structure having a second perimeter length) can reduce leakage current near the material stack and provide within the insulating dielectric layer Better material packaging.

At step 626, method 600 can include filling with another interlayer dielectric layer. Next, at step 628, planarization is performed to expose the top surface of the material stack. Further, at step 630, a third metal layer (eg, M5 metal layer 312 of FIG. 3) is formed over the top surface of the material stack and other interlayer dielectric layers. According to one embodiment, the third metal layer can be patterned, etched, and filled (using an insulating material) to form each Three metal layer segments.

As described herein, the strut material layer can include a strut device that can include a strut structure (of the contact material) formed on top of the metal layer and a collar structure disposed on top of the strut structure. The collar structure can include two or more layers of material disposed in a stacked structure above the strut structure. The collar structure may have a cross section that is larger than the strut structure (eg, as described above, having a larger circumference). In some embodiments, two or more layers may include a first layer disposed in a cylindrical structure above the second cylindrical structure. The second cylindrical structure contacts the metal layer on the first surface and the second surface is coupled to the first cylindrical structure. According to this embodiment, the first cylindrical structure has a first side that contacts the strut structure and a second side that contacts the second surface of the second cylindrical structure. The first surface and the second surface may be located on opposite sides of the second cylindrical structure.

According to another embodiment, the resistive memory device structure can include a strut device. The strut device can include a strut structure including a conductive material, a first cover material layer, and a second cover material layer, wherein the first cover material layer comprises a switching material and the second cover material layer comprises an active conductor material. According to this embodiment, the first covering material layer is characterized by a first thickness and the second covering material layer is characterized by a second thickness different from the first thickness.

Figure 7 is a flow diagram illustrating an exemplary and non-limiting method of fabricating a memory cell including a monolithic resistive memory formed as a via device in accordance with various aspects of the present invention. The method 700 of FIG. 7 can be utilized to fabricate, for example, the memory of FIG. Unit 200 and/or memory structure 400 of FIG.

A substrate is provided at step 702. In one embodiment, the provided substrate has one or more CMOS devices formed therein. In an alternate embodiment, one or more CMOS devices can be fabricated on or in a substrate. In a further embodiment, a substrate can be provided in which one or more CMOS devices are formed, and one or more additional CMOS devices can also be fabricated on or in the substrate.

At step 704, a first metal layer is disposed over the substrate. In some embodiments, the first metal layer is the M3 metal layer 404 of FIG. For example, a first metal layer (eg, M3 metal layer 404) can be provided as part of the substrate. In another example, a first metal layer (eg, M3 metal layer 404) can be formed on top of a substrate comprising one or more CMOS devices. According to one embodiment, an insulating layer (eg, an interlayer dielectric) is disposed over the substrate prior to forming the first metal layer over the substrate, and a first metal layer is formed over the insulating layer.

At step 706, a first interlayer dielectric can be formed over the first metal layer. The interlayer dielectric can be used for electrically insulating metal layers. Further, the interlayer dielectric is in detail a dielectric material for electrically separating closely spaced interconnect lines (eg, metal layers). The interlayer dielectric may include an insulator having a dielectric constant that is as low as possible (eg, closer to 1 as possible). Having a low dielectric constant k minimizes capacitive coupling (eg, crosstalk) between adjacent metal lines. According to one aspect, the low-k dielectric is a dielectric material having a dielectric constant k of less than 3.9 (k value of cerium oxide).

At step 708, the vias may be formed through the interlayer dielectric quality. According to various embodiments, the via device can be formed using suitable etching techniques, slotting techniques, or similar techniques for removing materials of stacked semiconductor films or layers. The vias can be, for example, contacts, vertical contacts, conductors, and the like. In one embodiment, the vias may be formed in at least a portion of the interlayer dielectric. At step 710, the vias may be filled with a conductive material. For example, the via filled with the conductive material may be the V3 contact 406 of FIG.

At step 712, a second metal layer can be formed over the interlayer dielectric and the via. The second metal layer may be the M4 metal layer 408 of FIG. According to one embodiment, the second metal layer can be patterned.

At step 714, another interlayer dielectric layer can be formed. Another interlayer dielectric layer can be formed over the second metal layer and can be used to electrically isolate the second metal layer from subsequent layers.

At step 716, a second via may be formed through a portion of another interlayer insulating layer and a portion of the second metal layer. At step 718, the sidewalls of the second via may be lined. According to one embodiment, the side walls are lined with a layer of resistance switching material.

At step 720, the remainder of the second via is filled with a metallic material. In one embodiment, the metal material used to fill the remaining portion of the second via may be an active metal. In another embodiment, the second metal layer may be formed of an active metal, and in such a case, the metal material for filling the remaining portion of the second via may be selected from aluminum, aluminum, and copper, including titanium nitride. Aluminum, titanium or titanium nitride-containing aluminum, titanium nitride, aluminum and copper or titanium nitride, or a suitable combination thereof. At step 722, the other interlayer dielectrics and the tops of the second vias may be planarized.

At step 724, the planarized interlayer dielectric and the second via may be covered by a third interlayer dielectric. Further, at step 726, a third via is formed in the third interlayer dielectric. The third through hole may be formed downward toward the top surface of the second through hole to be filled.

At step 728, the third via is filled with a metallic material. For example, the metallic material can be tungsten or a similar material. At step 730, the third interlayer dielectric and the third via are planarized to expose the tungsten material. Additionally, at step 732, a third metal layer is formed. The third metal layer can be patterned according to one face.

Provided herein is a monolithic body of resistive memory having a CMOS that utilizes an integrated circuit casting process. The disclosed aspects are acceptable in terms of thermal budget and plasma damage, which can be based on a variety of design considerations. Moreover, the connection schemes as discussed herein have been provided using a variety of schemes for integrated circuit casting, according to one aspect, multiple schemes utilizing a tungsten plug process to connect to aluminum, copper, or any other metallization scheme. Moreover, by using the disclosed aspects, the design rules and electrical modes for other devices in the circuit can only have a small impact. Moreover, one or more of the disclosed aspects have lower cost, lower parasitic considerations, and smaller wafer sizes relative to other processes.

In various embodiments of the invention, the disclosed memory structure can be used as an independent or integrated embedded memory device with a CPU or microcomputer. Some embodiments may be implemented, for example, as part of a computer memory (eg, random access memory, cache memory, read only memory, storage memory, etc.). Other implementable embodiments, For example, as a portable memory device. Examples of suitable portable memory devices may include, for example, removable memory, secure digital (SD) cards, universal serial bus (USB) memory sticks, compact flash (CF) cards, etc., or suitable for the foregoing. combination. (See, for example, Figures 8 and 9 and below).

NAND FLASH can be used in compact flash devices, USB devices, SD cards, solid state drives (SSDs), and storage class storage, and can be used in other forms as well. While NAND has proven successful in the past decade to drive reduced technology to smaller devices and higher wafer densities, as technology scales down to the old 25 nanometer (nm) memory cell technology, some Structural, performance and reliability issues have also become apparent. Such considerations have been addressed in the disclosed aspects.

To provide a context-specific context for the disclosed subject matter, FIG. 8, and the following discussion, a brief, suitable description is provided for various aspects of the environment in which the disclosed subject matter can be implemented or processed. Although the subject matter for making and operating such structures has been described in the general context of semiconductor structures and process methods, those skilled in the art will appreciate that the invention can be practiced in combination with other structures or process methods. Moreover, those skilled in the art will appreciate that the disclosed program can be implemented in a processing system or computer processor (whether it is a separate computer or in conjunction with a host computer (eg, computer 902 in FIG. 9 and hereinafter)), which can include Single processor or multiple processor computer systems, small computing devices, large computers, even personal computers, handheld computer devices (eg, PDAs, smart phones, watches), microprocessor-based or programmable consumer or industrial Electronic products, etc. The illustrated aspects can also be implemented in a decentralized computing loop The task is performed by a remote processing device connected via a communication network. However, some or all aspects of the present invention can be implemented in stand-alone electronic devices such as memory cards, flash memory modules, removable memory, and the like. In a decentralized computing environment, program modules can be located in both local and remote memory storage modules or devices.

Figure 8 illustrates a block diagram of an example operational and control environment 800 for a memory cell array 802 in accordance with the present invention. In at least one aspect of the present invention, memory cell array 802 can include a variety of memory cell technologies. In particular, as described herein, memory cell array 802 can include a resistive switching memory cell having rectifying characteristics.

Column controller 804 or row controller 806 can be formed adjacent to memory cell array 802. Moreover, row controller 806 can be electrically coupled to bit lines of memory cell array 802. Row controller 806 can control individual bit lines, apply appropriate programming, erase or sense voltages to selected bit lines.

Column controller 804 can be formed adjacent row controller 806 and electrically coupled to word lines of memory cell array 802. Column controller 804 can select a particular column of memory cells with a suitable selection voltage. In addition, column controller 804 can facilitate programming, erase or read operations by applying a suitable voltage to the selected word line.

Clock source 808 can provide respective clock pulses for timing of read, write, and program operations for column controller 804 and row controller 806. The clock source 808 can further facilitate selection of word lines or bit lines in response to external or internal lives received by the operating and control environment 800. make. The input/output buffer 812 can be connected to an external host device, such as a computer or other processing device, through an I/O buffer or other I/O communication interface (not shown, but for example, the computer 902 of FIG. 9 and epilogue). Input/output buffer 812 can be configured to receive write data, receive erase instructions, output read data, and receive address data and command data, as well as address data for respective instructions. The address data can be transferred to the column controller 804 and the row controller 806 by the address register 810. Additionally, input data can be passed to the memory cell array 802 via the signal input lines and output data can be received from the memory cell array 802 via the signal output lines. Input data can be received from the master device and the output data can be transferred to the master device via the I/O buffer.

Commands received from the master device can be provided to the command interface 814. The command interface 814 can be configured to receive an external control signal from the master device and determine if the data input to the input/output buffer 812 is a write data, command, or address. The entered commands can be passed to state machine 816.

State machine 816 can be configured to manage programming and reprogramming of memory cell array 802. State machine 816 receives commands from the host device via input/output buffer 812 and command interface 814 and manages read, write, erase, data input, data output, and similar functions associated with memory cell array 802. In some aspects, state machine 816 can send and receive acknowledgments and negative acknowledgments regarding successful receipt or execution of various commands.

For read, write, erase, input, and output The state machine 816 can control the clock source 808. Control of the clock source 808 can cause the output pulses to be configured to facilitate the column controller 804 and row controller 806 to perform particular functions. The output pulses can be transmitted to the selected bit line by, for example, row controller 806 or to the selected word line by, for example, column controller 804.

In conjunction with FIG. 8, the systems and processes described below can be implemented in hardware, such as a single integrated circuit (IC) die, multiple ICs, dedicated integrated circuits (ASIC), and the like. In addition, the order of some or all of the process blocks appearing in each process should not be considered limiting. It should be understood that some process blocks may be performed in various sequences, and not all possible sequences may be explicitly recited herein.

Referring to FIG. 9, a plurality of orientation-oriented appropriate operating environments 900 for implementing the claimed subject matter include a computer 902. Computer 902 includes processing unit 904, system memory 906, codec 935, and system bus 908. System bus 908 couples system components to processing unit 904, which includes, but is not limited to, system memory 906. Processing unit 904 can be any of a variety of processors that can be used. Dual microprocessors and other multiprocessor architectures can also be utilized as processing unit 904.

System bus 908 can be any number of types of bus bar structures including memory bus or memory controllers, peripheral bus bars or external bus bars, or local bus bars using any of a variety of available bus bar structures, including but Not limited to: Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card bus, Universal Serial Bus (USB), Advanced Graphics (AGP), Personal Computer Memory Card International Compact Bus (PCMCIA), Firewire (IEEE 1394), and Small Computer System Interface (SCSI).

In various embodiments, system memory 906 includes volatile memory 910 and non-volatile memory 912, which may use one or more of the disclosed memory structures. A basic input/output system (BIOS) is stored in non-volatile memory 912, which contains the basic routine for transferring information between elements within computer 902 (e.g., during startup). Further, according to the present invention, the codec 935 may include at least one of an encoder or a decoder, wherein at least one of the encoder or the decoder may be composed of hardware, software, or a combination of hardware and software. Although codec 935 is depicted as a separate component, codec 935 can be included in non-volatile memory 912.

By way of illustration and not limitation, non-volatile memory 912 may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), Or flash memory. In at least some of the disclosed embodiments, the non-volatile memory 912 can use one or more of the disclosed memory structures. In addition, the non-volatile memory 912 can be a computer memory (eg, a physical integrated computer 902 or its motherboard), or a removable memory. Examples of suitable removable memory of the disclosed embodiments can be implemented including a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) memory stick, and the like. Volatile memory 910 includes cache memory or random access memory (RAM) as an external cache Memory, and one or more of the disclosed memory structures in various embodiments may also be employed. By way of illustration and not limitation, RAM can be used in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), and enhanced SDRAM (ESDRAM). Wait.

Computer 902 may also include removable/non-removable, volatile/volatile computer storage media. Figure 9 shows, for example, disk storage 914. Disk storage 914 includes, but is not limited to, a device such as a magnetic disk drive, a solid state disk (SSD), a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash card, or a memory stick. In addition, the disc storage 914 can include storage media, either alone or in combination with other storage media, including but not limited to optical disc drives such as compact disc ROM devices (CD-ROMs), CD recordable drives (CD-R drives), CD rewritable drive (CD-RW drive) or digital versatile CD ROM drive (DVD-ROM). To facilitate the connection of the disk storage 914 to the system bus 908, a removable or non-removable interface such as interface 916 is typically used. It will be appreciated that the disc storage 914 can store information about the user. Such information can be stored or provided to an application running on a server or user device. In one embodiment, the user may be notified (eg, via output device 936) the type of information that is stored to the disc storage 914 and/or sent to the server or application. The user has the opportunity to opt-in or opt-out of information having such collection and/or sharing with a server or application (e.g., via input device 928).

However, it should be understood that Figure 9 depicts the software, which As an intermediary between the user and the basic computer resources described in the appropriate operating environment 900. Such software includes an operating system 918. Operating system 918 can be stored on disk storage 914 for controlling and distributing resources of computer 902. The application 920 utilizes the management of resources by the operating system 918, which is stored in the system memory 906 or on the disk storage 914 by a program module 924 such as a startup/shutdown processing table or program data 926. However, it should be understood that the claimed subject matter can be implemented in various operating systems or combinations of operating systems.

The user inputs a command or information through the input device 928 to the computer 902. Input device 928 includes, but is not limited to, pointing devices such as: mouse, trackball, sensor pen, touch pad, keyboard, microphone, joystick, game handle, satellite dish, scanner, TV adjustment card, digital camera, digital camera , webcams, and more. These and other input devices are coupled to processing unit 904 via system bus 908 via interface bus 930. The interface 930 includes, for example, a serial port, a parallel port, a game pad, and a universal serial bus (USB). Output device 936 uses some of the same type of ports as input device 928. Thus, for example, a USB port can be used to provide input to the computer 902 and output information from the computer 902 to the output device 936. Output adapter 934 is provided to illustrate the presence of some output devices such as displays, speakers, and printers, as well as other output devices that require special adapters. The output adapter 934 includes, by way of example but not limitation, an image and sound card that provides a means of connection between the output device 936 and the system bus 908. It should be noted that devices of other devices or systems provide both input and output capabilities, such as remote computer 938.

Computer 902 can operate in a network environment using logical connections to one or more remote computers, such as remote computer 938. The remote computer 938 can be a personal computer, a server, a router, a network PC, a workstation, a microprocessor based appliance, a peer device, a smart phone, a tablet, or other network node, and typically includes a description of a number of components relative to Computer 902. For the sake of brevity, only the memory storage device 940 having the remote computer 938 is illustrated. Remote computer 938 is logically coupled to computer 902 via network interface 942 and then coupled via communication connection 944. Network interface 942 includes wired or wireless communication networks such as local area networks (LANs) and wide area networks (WANs) and cellular networks. LAN technologies include Fiber Decentralized Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, and others. WAN technologies include, but are not limited to, point-to-point links, circuit switched switching networks such as Integrated Services Digital Network (ISDN) and variants thereof, packet switched networks, and Digital Subscriber Line (DSL).

Communication connection 944 refers to the hardware/software used to connect network interface 942 to system bus 908. Although communication connection 944 is illustrated to clearly illustrate internal computer 902, it can also be an external computer 902. Hardware/software necessary for connection to the network interface 942 includes, by way of example only, internal and external technologies such as data machines including conventional telephone-grade data machines, cable modems and DSL modems, ISDN adapters, And wired and wireless Ethernet cards, hubs, and routers.

The illustrated aspects of the present disclosure can also be implemented in a distributed computing environment where certain tasks are performed by remote processing devices that are linked through a communications network. In a decentralized computing environment, program modules or stored Information, instructions, etc. can be located in local or remote memory storage devices.

In addition, it is to be understood that the various components described herein can include circuitry that can include components and circuit components of suitable values to implement various embodiments of the present invention. Moreover, it will be appreciated that many of the various components can be implemented on one or more integrated circuit wafers. For example, in one embodiment, a set of components can be implemented on a single IC wafer. In other embodiments, one or more of the individual components are fabricated or implemented in a separate IC wafer.

As used herein, the terms "component," "system," "structure," and the like are intended to mean a computer or an electronic related entity, or a combination of hardware, hardware, and software, software (eg, in execution), Or firmware. For example, the component can be one or more of a transistor, a memory cell, a transistor or a memory cell configuration, a gate array, a programmable gate array, a dedicated integrated circuit, a controller, a processor, on a processor The running program utilizes a semiconductor memory access or interface program or an executable object of the application, a computer, etc., or a suitable combination thereof. Components may include erasable programming (eg, program instructions are at least partially stored in erasable memory) or hard programming (eg, program instructions are burned into non-erasable memory at the time of manufacture).

By way of illustration, a program that is executed concurrently from a memory and a processor can be a component. As another example, the structure may include processing instructions for electronic hardware (eg, parallel or serial transistors), processing instructions, and processor configurations that are implemented in a suitable electronic hardware configuration. In addition, the structure may include a single component (eg, a transistor, a gate array, etc.) or a configuration of components (eg, a parallel or serial configuration of the transistor, connected Gate array of the circuit, power line, electrical ground, input signal line and output signal line, etc.). A system can include one or more components, as well as one or more structures. An exemplary system can include a switching block structure that includes across a input/output line and through a gate transistor, as well as a power supply, a signal generator, a communication bus, a controller, an I/O interface, an address register, and the like. However, it should be understood that certain overlapping definitions are contemplated, and that the structure or system can be a separate component, or another structure, a component of a system, or the like.

In addition to the above, the disclosed subject matter can be implemented as a method, apparatus, or use of a commonly manufactured article of manufacture, programming or engineering techniques for producing hardware, firmware, software, or any suitable combination thereof to control an electronic device. To achieve the disclosed subject matter. The terms "device" and "article of manufacture" as used herein are intended to encompass an electronic device, a semiconductor device, a computer, or a computer program accessible from any computer-readable device, carrier, or media. Computer readable media can include hardware or software media. In addition, the media may include non-transitory media or transmission media. In one example, the non-transitory media can include computer readable hardware media. Specific examples of computer readable hardware media may include, but are not limited to, magnetic storage devices (eg, hard disks, floppy disks, magnetic strips, etc.), optical disks (eg, compact discs (CDs), digital versatile discs (DVD), etc.) , smart cards, and flash memory devices (eg, cards, sticks, key drives, etc.). The computer readable transmission medium can include a carrier wave or the like. Of course, those skilled in the art will appreciate that many modifications can be made without departing from the scope or spirit of the invention.

What has been described above includes examples of the invention. Of course, for the purpose of describing the invention, it is not possible to describe every conceivable element or method. Combinations, but one of ordinary skill in the art will appreciate that many further combinations and permutations of the present invention are possible. Accordingly, the disclosed subject matter is intended to cover all such modifications, modifications and variations In addition, the term "comprising", "including" or "having" and its variants, whether used in the context of the detailed description or claim, is intended to be inclusive. Similar to the use of the term "including", as it is interpreted as a conjunction in the scope of the patent application.

Further, the word "exemplary" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, the exemplary use of words is intended to present concepts in a specific manner. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified, or clearly visible from the context, "X uses A or B" is intended to mean any natural inclusive permutation. That is, if X uses A; X uses B; or X uses both A and B, then "X employs A or B" can satisfy any of the above examples. In addition, the articles "a" and "an" are used in the claims and the claims

Moreover, some of the detailed description has been presented in the algorithm or program operation of the data bits in the electronic memory. These program descriptions or representations refer to the mechanisms used by those of ordinary skill in the art to effectively convey the substance of their work to other knowledge in the art. Know the same skilled person. Here, a process or procedure is generally a series of self-consistent behaviors that are conceived to result in a desired result. This behavior is a physical manipulator that requires physical quantities. Typically, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and/or otherwise manipulated, although not necessarily.

These signals have been shown to mean bits, values, elements, symbols, characters, terms, numbers, etc., primarily for reasons of public use. However, it should be borne in mind that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise, or explicitly derived from the foregoing discussion, it should be understood that in the overall subject matter of the present disclosure, the use of terms such as processing, computing, copying, iding, determining, or transmitting, and similar terms refers to Is the action and procedure of a processing system, or a similar consumer or industrial electronic device or machine that represents information or signals as physical (electrical or electronic) operations in the circuitry, registers or memory of an electronic device or Converted to other data or signals that approximate physical quantities within a machine or computer system memory or scratchpad or other such information storage, transmission or display device.

The terms used to describe these elements (including the "means" referred to) are intended to correspond to (unless specifically indicated) any execution of the various functions performed by the components, structures, circuits, processes, etc. described above. An element of a specified function of an element (e.g., functionally equivalent), even if it is not structurally equivalent to the disclosed structure, performs the aspect-oriented function of the example embodiments described herein. Additionally, although certain features may have been disclosed with respect to only one of several instances, these features may One or more other feature combinations of his instances may be desirable and advantageous for any given or particular application. It should also be understood that the embodiments include systems, and computer readable media having computer executable instructions for performing the acts or events of the various programs.

Claims (20)

A memory device comprising: a substrate comprising one or more complementary metal oxide semiconductor devices; a first insulator layer formed over the substrate; and a monolithic stack comprising: being fabricated as part of a single stone process a plurality of layers above the first insulator layer, wherein the plurality of layers comprise a first metal layer, a second insulator layer, and a second metal layer, wherein the resistive memory device structure is formed on the second insulator The resistive memory device structure is implemented as a pillar device within the layer and within a thermal budget of the one or more complementary metal oxide semiconductor devices, and wherein the first metal layer is electrically connected to the first via a conductor material At least a portion of the two metal layers. The memory device of claim 1, wherein the single stone stack is formed within a limit of a casting compatible process, and a defined distance between the first metal layer and the second metal layer It is substantially similar to the distance between the second metal layer and the third metal layer. The memory device according to claim 1, wherein the resistive memory device structure is manufactured at a temperature of 450 degrees Celsius or lower. The memory device of claim 1, wherein the pillar device comprises a pillar and a collar formed on the first metal layer, wherein the collar comprises contacting the second metal layer on the first surface Two layers of material. The memory device of claim 4, wherein the first layer of material of the two layers of material comprises a first side contacting the pillar and a second surface contacting the second layer of material of the two layers of material a second side, wherein the first surface of the second layer of material contacts the first surface of the second metal layer, and wherein the first surface and the second surface of the second layer of material are located in the second layer of material On the opposite side. The memory device of claim 1, wherein the pillar device comprises a substrate, a first layer and a second layer, the substrate comprising a conductive material, the first layer being over the substrate and comprising a switching material, The second layer is above the first layer and contains another electrically conductive material. The memory device of claim 6, wherein at least one of: the substrate comprises a first thickness, and the first layer above the substrate or the second layer above the first layer The layer includes a second thickness different from the first thickness; or the cross section of the substrate has a first perimeter, and the first layer is above the substrate or the second layer is a second cross section above the first layer Having a second perimeter, and wherein the length of the first perimeter is less than the second perimeter. The memory device of claim 1, wherein the pillar device comprises a first cylinder or a first approximate cylinder comprising a resistance switching material and a second cylinder or a second approximate cylinder comprising an active material. The memory device of claim 1, wherein the pillar device comprises: a substrate including a crucible, and a resistor cut including SiOx Change materials, and active materials including silver materials, aluminum materials, or copper materials. A method of fabricating a memory device, comprising: fabricating a pair of metal layers having a defined distance therebetween; and fabricating a monolithic stack comprising a plurality of layers, wherein the fabrication is on a substrate of the memory device Manufactured within the thermal budget and having a stack height less than or equal to the defined distance, the manufacturing comprising: providing the substrate comprising one or more complementary metal oxide semiconductor devices; fabricating the first over the substrate An insulator layer; a first metal layer of the pair of metal layers is formed over the first insulator layer; an interlayer dielectric material layer is formed over the first metal layer; and a resistive memory device is fabricated in the interlayer dielectric material layer a structure comprising: forming a pillar device; fabricating a second metal layer of the pair of metal layers over the resistive memory device structure, the second metal layer being segmented into a plurality of portions; and the first metal layer and the Electrical contact is formed between at least a portion of portions of the second metal layer. The method of claim 10, wherein the method is a casting compatible process and includes forming a third metal layer at a distance from the second metal layer that is approximately equal to the defined distance. The method of claim 10, wherein the manufacturing the monolithic stack comprises: fabricating the monolithic stack at a temperature of about 450 degrees Celsius or less. The method of claim 12, wherein the manufacturing the monolithic stack comprises: fabricating the monolithic stack at a temperature between about 400 and 450 degrees Celsius. The method of claim 12, wherein the manufacturing the monolithic stack comprises: fabricating the monolithic stack at a temperature between about 350 and 400 degrees Celsius. The method of claim 12, wherein the manufacturing the monolithic stack comprises: fabricating the monolithic stack at a temperature between about 300 and 350 degrees Celsius. The method of claim 10, wherein the forming the pillar device comprises depositing, patterning, and etching a material layer stack, the material layer stack comprising a conductive substrate layer, a resistance switching layer above the conductive substrate layer, and And a second conductive layer above the resistance switching layer, and further comprising forming the resistance switching layer or the second conductive layer to have a cross-sectional area larger than a second cross-sectional area of the conductive substrate layer. A memory unit comprising: a substrate comprising one or more complementary metal oxide semiconductor devices; a first insulator layer formed over the substrate; and a monolithic stack comprising: being fabricated as part of a single stone process a plurality of layers above the first insulator layer, wherein the plurality of layers comprise a first metal layer formed on a top surface of the substrate, a first conductive layer formed on the first metal layer, and a second insulator And a second metal layer, wherein the resistive memory device structure is formed in the second insulator layer and within a thermal budget of the one or more complementary metal oxide semiconductor devices, and wherein the conductive material The first metal layer is coupled to at least a portion of the second metal layer. The memory unit according to claim 17, wherein the resistive memory device structure is manufactured at a temperature of 450 degrees Celsius or lower. The memory unit of claim 17, wherein the resistive memory device structure comprises a pillar device, the pillar device comprising a base material formed on the first metal layer and a collar formed on the base material Wherein the collar comprises two or more layers of material and contacts the second metal layer on a first surface of the collar. The memory unit of claim 19, wherein the first layer of the collar includes a first side contacting the first side of the pillar and a second side contacting the second surface of the second layer of the collar, and Wherein the first surface and the second surface are on opposite sides of the second layer of the collar.