TWI669713B - Memory device and control method thereof - Google Patents

Abstract

The present invention provides a memory device including a memory array, a switching device disposed between a first voltage node and a second voltage node, and the second voltage node coupled to the memory array; and a control The device outputs an update mode signal, an update trigger signal, and a pre-start signal. The memory device should update the mode signal and enter a self-updating mode; in the self-updating mode, the memory device should update the trigger signal to perform a self-updating operation on the memory array; in the self-updating mode The controller outputs the pre-start signal before outputting the update trigger signal. The switch device returns to the pre-start signal and turns on to increase the potential of the second voltage node to the potential of the first voltage node.

Description

Memory device and control method thereof

The present invention relates to a memory device, and more particularly to a control method for the memory device to enter a self-refresh mode.

Dynamic Random Access Memory (DRAM) is commonly used in various electronic devices today. DRAM is a volatile memory (Volatile Memory). In other words, in the state of losing power, DRAM will lose its stored state. Because the data stored in the DRAM is gradually degraded or invalid due to the internal leakage current, in order to maintain its internal valid data, the DRAM needs to continuously and periodically update its internal data bits.

When DRAM operates in self-refresh mode, most of the time is idle. Figure 1 is a schematic diagram of a leakage current path in a memory device. As shown in FIG. 1, the memory device 100 includes a decoder 102 powered by a positive power supply VP and a negative power supply VN, the decoder 102 being coupled to a gate terminal of a transistor 110 via a word line 104, and The transistor 110 is coupled between a word line 106 and a storage unit capacitor 108, and the storage unit capacitor 108 is coupled between the transistor 110 and a buried plate voltage VPL. .

Since the voltage of the positive power source VP is high, even if the memory device 100 does not perform an operation, the positive current source VP flows through the decoder 102 to a leakage current path 112 of the negative power source VN, so that the leakage current continues to exist. One method of power saving is to reduce the voltage of the positive power supply VP before the memory device 100 enters the self-refresh mode, although the above method can make the leakage current on the leakage current path 112 small, but if the positive power supply VP cannot When the waiting time tXSR returns to the original potential, if the positive power source VP has not reached the normal operating voltage of the memory device 100, an external device command is received to perform an action, which causes the memory device to be activated. 100 caused an error.

Since the leakage current originates from inside the memory device 100, in order to reduce the leakage current without affecting the operation of the memory device, the present invention provides a new architecture for using the switching device to store the memory array. The internal positive power supply VP is separated from the positive power supply VP outside the memory array and stepped down, and a pre-opening mechanism is utilized to recover the positive power supply VP inside the memory array.

A memory device according to an embodiment of the present invention includes a memory array, a switching device disposed between a first voltage node and a second voltage node, and the second voltage node coupled to the memory array; And a controller that outputs an update mode signal, an update trigger signal, and a pre-start signal. The memory device should update the mode signal and enter a self-updating mode; in the self-updating mode, the memory device should update the trigger signal to perform a self-updating operation on the memory array; in the self-updating mode After the self-updating operation is performed by the memory device, the controller outputs the pre-start signal before re-outputting the update trigger signal, and the switch device responds to the pre-start signal and turns on to enable the second voltage. The potential of the node increases toward the potential of the first voltage node.

According to a method of controlling a memory device according to an embodiment of the present invention, the memory device includes a memory array, a switching device disposed between a first voltage node and a second voltage node, and the second voltage node The controller is coupled to the memory array and outputs a refresh mode signal, an update trigger signal, and a pre-start signal, and the memory device returns to the self-updating mode by updating the mode signal; the control method includes After the self-updating mode is performed, the controller re-outputs the pre-start signal and turns the switching device on, so that the potential of the second voltage node is toward the first voltage. The potential of the node is increased; afterwards, the controller outputs the update trigger signal to cause the memory device to perform a self-updating operation on the memory array.

FIG. 2 is a schematic diagram of a memory device according to an embodiment of the present disclosure. As shown in FIG. 2, the memory device 200 includes a memory array 202, a switching device 204, a controller 206, a voltage clamp 208, a decoupling capacitor 210, and a power charge pump (charge). Pump circuit 212, and a logic device 214. The memory array 202 includes a plurality of memory cells for storing valid bit data. The memory device 200 further includes a column decoder, a row decoder, and a timing control circuit which are not shown in FIG. When the memory device 200 is in a self-updating mode, the timing controller, the column decoder, and the row decoder cooperate to perform self-updating of the memory array according to an update trigger signal REFRI output by the controller 206. (self-refresh) action. Memory array 202 can also be represented in the form of a memory bank. The switching device 204 is disposed between a first voltage node VPP and a second voltage node VPPA, and the second voltage node VPPA is coupled to the memory array 202. The second voltage node VPPA is coupled to the memory array, for example, by providing power to the column decoder and/or row decoder or the like.

The controller 206 can output an update mode signal SRMOD, the aforementioned update trigger signal REFRI, and a pre-start signal PRESR. The memory device 200 enters the self-updating mode in response to the update mode signal SRMOD output by the controller 206. In the self-updating mode, the memory device 200 should update the trigger signal REFRI to perform a self-updating operation on the memory array 202. The logic device 214 controls the switching device 204 according to the update mode signal SRMOD output by the controller 206 and the pre-activation signal PRESR. In the self-updating mode, if the logic device 214 does not receive the pre-start signal PRESR, the switching device 214 is controlled to be in a turn-off state. In the self-updating mode, after the controller 206 outputs the update trigger signal REFRI and the memory device 200 performs the self-updating operation, if the controller 206 is to re-output the update trigger signal REFRI, the pre-output will be output first. The start signal PRESR is caused to cause the switching device 204 to return to the pre-start signal PRESR and turn on-turn to increase the potential of the second voltage node VPPA to the potential of the first voltage node VPP. When the controller 206 stops outputting the update mode signal SRMOD to cause the memory device 200 to leave the self-refresh mode, the logic device 214 controls the switching device 204 to turn on, so that the memory array 202 can perform the general read and write operations.

The voltage clamp 208 is disposed between the first voltage node VPP and the second voltage node VPPA; when the switching device 204 is turned off, the potential of the second voltage node VPPA is maintained above a reference voltage. The decoupling capacitor 210 is coupled between the first voltage node VPP and a ground to quickly restore the potential of the first voltage node VPP when the switching device 204 is turned on. The power supply charge pump 212 is coupled between the power supply voltage VDD1 and the first voltage node VPP, and is used to pull the potential of the first voltage node VPP to a rated voltage when the switching device 204 is turned on.

FIG. 3 is a circuit diagram of the switching device 204 and the logic device 214 according to the second embodiment of the present disclosure. In the present embodiment, as shown in FIG. 3, the switching device 204 includes, for example, an inverter 300 and a PMOS transistor 302. The PMOS transistor 302 is coupled to the first voltage node VPP and the second voltage node. Between the VPPAs, the gate terminal of the PMOS transistor 302 is coupled to the output terminal of the inverter 300, and the input terminal of the inverter 300 is configured to receive the control signal SWEN output from the logic device 214. In the present embodiment, the logic device 214 includes, for example, a NAND gate 304 and an inverter 306. The first input end of the NAND gate 304 is coupled to the output end of the inverter 306, and the input end of the inverter 306 receives the pre-start signal PRESR from the controller 206; The second input of the gate 304 receives the update mode signal SRMOD from the controller 206; the output of the inverse gate 304 (ie, the output of the logic device 214) is coupled to the switching device 204 for The opening or closing of the switching device 204 is controlled.

Fig. 4 is a timing chart showing the relationship between the potential of the second voltage node VPPA and the plurality of control signals of the memory device of the second embodiment of the present invention. Referring to FIG. 4, before the controller 206 outputs the update status signal SRMOD, the update status signal SRMOD has a low level. Since the pre-start signal PRESR is also a low level, according to the logic circuit of the logic device 214 of FIG. 3, the logic device. 214 will output a high level control signal SWEN. The high level control signal SWEN then goes through the inverter 300 in the switching device 204 to become a low level, so that the PMOS transistor 302 is turned on, that is, the switching device 204 is turned on.

After the controller 206 outputs the update status signal SRMOD, the memory device 200 enters the self-updating mode. At this time, since the update status signal SRMOD changes from the low level to the high level, the pre-start signal PRESR remains at the original low level, causing the control signal SWEN outputted by the logic device 214 to become a low level and the switch The device 204 is turned off, and the electrical coupling of the first voltage node VPP and the second voltage node VPPA is interrupted. Next, in the self-updating mode, the controller 206 outputs an update trigger signal REFRI such that the memory array 202 begins performing a self-updating operation (time interval A). After the time interval A, due to the leakage current inside the memory array 202 (ie, the leakage current path 112 shown in FIG. 1), the potential of the second voltage node VPPA will gradually decrease until the voltage clamp 208 will be the second voltage node. The potential of the VPPA is limited to a reference voltage of 400 (time interval B, C).

Then, in the self-updating mode, the controller 206 outputs the pre-start signal PRESR (becomes a high level). At this time, since the update mode signal SRMOD is already at the high level, the output of the inverse gate 304 in the logic device 214 is controlled. The signal SWEN becomes a high level, and the PMOS transistor 302 in the switching device 204 is turned on. Here, since the potential of the decoupling capacitor 210 is equal to the potential of the first voltage node VPP, the potential of the second voltage node VPPA can be increased to the potential of the first voltage node VPP (time interval D). Then, the power supply charge pump 212 detects that the potential of the first voltage node VPP has not reached a rated voltage 402 when the memory device 200 operates, and pulls up the potential of the first voltage node VPP and the second voltage node VPPA. Up to the rated voltage 402 (between time intervals D and E).

After the potential of the second voltage node VPPA reaches the rated voltage 402, in the time interval A1, when the controller 206 outputs the update trigger signal REFRI again, the output pre-start signal PRESR is stopped at the same time, because the pre-start signal PRESR is changed from the high level to the high level. At the low level, the corresponding control signal SWEN also changes from the high level to the low level, causing the switching device 204 to be turned off, and the memory array 202 begins to perform the self-updating operation of the next cycle (time interval A1). Since the time interval B, C when the memory array 202 performs the self-updating operation accounts for more than 95% of the total time of the self-refresh period, that is, the memory array 202 is in an idle state, the above-mentioned memory disclosed by the present invention The body device and its control method can effectively reduce the leakage current (ie, the leakage current path 112 shown in FIG. 1), and achieve the purpose of power saving. In addition, in order to ensure that the self-updating operation started in the time interval A1 can be correctly completed, the controller 206 outputs the pre-start signal PRESR first, and turns on the switching device 204, so that the controller 206 turns off the update trigger signal REFRI in the time interval A1. The voltage of the VPPA of the two voltage nodes can rise rapidly.

FIG. 5 is a timing diagram of the potential of the second voltage node VPPA and the plurality of control signals of the memory device leaving the self-refresh mode according to the second embodiment of the present disclosure. As shown in FIG. 5, when the memory device 200 needs to leave the self-refresh mode to execute a general read/write command, the controller 206 first outputs the update status signal SRMOD (the time interval C is converted to the time interval F), so that the memory device 200 is enabled. Leave the self-updating mode and enter the normal working mode. At this time, since the update status signal SRMOD becomes a low level, the control signal SWEN outputted by the inverse gate 304 in the logic device 214 becomes a high level, and the PMOS transistor 302 in the switching device 204 is turned on. At this time, since the potential of the decoupling capacitor 210 is equal to the potential of the first voltage node VPP, the potential of the second voltage node VPPA can be increased to the potential of the first voltage node VPP (the first stage of the time interval F has a larger slope) Slash). Then, the power supply charge pump 212 detects that the potential of the first voltage node VPP has not reached a rated voltage 402 when the memory device 200 is operating, and activates the charge pump function to connect the first voltage node VPP with the second voltage node VPPA. The potential is pulled up to the rated voltage 402 (the oblique line of the second stage of the time interval F is smaller and the third horizontal line). After the potential of the second voltage node VPPA reaches the rated voltage 402, that is, after the operating voltage of the memory device 200 is reached, the memory array 200 receives the command signal CMD output by the controller 206 to start the reading and writing operation (time interval). G). In the time interval F, since it is necessary to wait for the potential of the second voltage node VPPA to rise to the rated voltage 402, the controller 206 can output the command signal CMD after a waiting time tXSR to avoid the memory array 202 from operating voltage. An error caused by being too low.

Figure 6 is a control flow chart of the memory device of the second embodiment of the present disclosure. After receiving the update mode signal SRMOD outputted by the controller 206, the memory device 200 enters the self-updating mode, and the switching device 204 is turned off (S600). Step S600 interrupts the electrical coupling of the first voltage node VPP and the second voltage node VPPA, and the potential of the second voltage node VPPA gradually decreases due to the leakage current inside the memory array 202. In the self-updating mode, after the self-updating operation is performed by the memory array 202, the controller 206 re-outputs a pre-start signal PRESR to turn on the switching device 204 (S602). Step S602 is to increase the potential of the second voltage node VPPA to the potential of the first voltage node VPP, and cooperate with the operation of the power charge pump 212 to complete the pre-operation before the memory array 202 performs self-updating (making the first voltage node The potential of the VPP reaches a rated voltage of 402), avoiding the error in the memory array 202 due to the low potential of the first voltage node VPP. Next, the controller 206 outputs an update trigger signal REFRI such that the memory array 202 performs self-updating and simultaneously turns off the switching device 204 (S604). Since the memory array 202 is in an idle state for a long period of time from the update, the step S604 turns off the switching device 204 to reduce the leakage current. If the memory device 200 needs to continue to perform the self-updating operation of the next cycle, the controller 206 outputs the update trigger signal REFRI again, that is, step 604 returns to step 602 again. To leave the self-updating mode, the controller 206 stops outputting the update status signal SRMOD, causing the memory device 200 to leave the self-updating mode, and the switching device 204 is turned on (S606). Step S606 is such that the potential of the second voltage node VPPA reaches the rated voltage 402, so that the memory device 200 can perform the operation of the general read/write command at a sufficient voltage.

While the embodiments of the invention have been described above, it is to be understood that Many variations of the above-described exemplary embodiments in accordance with the present embodiments can be performed without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention should not be limited Rather, the scope of the invention should be defined by the following claims and their equivalents.

100‧‧‧ memory device

102‧‧‧Decoder

104‧‧‧ character line

106‧‧‧ bit line

108‧‧‧Storage unit capacitance

110‧‧‧Optoelectronics

112‧‧‧Leakage current path

200‧‧‧ memory device

202‧‧‧Memory array

204‧‧‧Switching device

206‧‧‧ Controller

208‧‧‧Voltage clamp

210‧‧‧Decoupling capacitor

212‧‧‧Power Charge Pump

214‧‧‧Logical device

300‧‧‧Inverter

302‧‧‧PMOS transistor

304‧‧‧ NAND gate

306‧‧‧Inverter

400‧‧‧reference voltage

402‧‧‧Rated voltage

SRMOD‧‧‧ update mode signal

SWEN‧‧‧ control signal

REFRI‧‧‧Update trigger signal

PRESR‧‧‧ pre-start signal

VDD1‧‧‧Power supply voltage

VN‧‧‧Negative power supply

VP‧‧‧ positive power supply

VPP‧‧‧ first voltage node

VPPA‧‧‧second voltage node

VPL‧‧‧ buried layer voltage

Figure 1 is a schematic diagram of the leakage current path in the memory device. FIG. 2 is a schematic diagram of a memory device according to an embodiment of the present disclosure. FIG. 3 is a circuit diagram of a switching device and a logic device according to a second embodiment of the present disclosure. FIG. 4 is a timing diagram of the potential of the second voltage node VPPA and the plurality of control signals of the memory device of the second embodiment of the present disclosure. FIG. 5 is a timing diagram of the potential of the second voltage node VPPA and the plurality of control signals after the memory device leaves the self-refresh mode according to the second embodiment of the present disclosure. Figure 6 is a control flow chart of the memory device of the second embodiment of the present disclosure.

Claims (12)

A dynamic random access memory (DRAM) device includes: a memory array; a switching device disposed between a first voltage node and a second voltage node, and the second voltage node is coupled to the memory An array, and a controller, outputting an update mode signal, an update trigger signal, and a pre-start signal; wherein the DRAM device should update the mode signal to enter a self-updating mode; In the mode, the DRAM device should update the trigger signal to perform a self-updating operation on the memory array; in the self-updating mode, after the DRAM device performs the self-updating operation, The controller outputs the pre-start signal before re-outputting the update trigger signal, and the switch device returns to the pre-start signal and turns on to increase the potential of the second voltage node to the potential of the first voltage node. The dynamic random access memory device of claim 1, further comprising a voltage clamp disposed between the first voltage node and the second voltage node; and when the switch device is turned off, The potential of the second voltage node is maintained above a reference voltage. The dynamic random access memory device of claim 1, further comprising a decoupling capacitor coupled between the first voltage node and a ground for quickly recovering when the switching device is turned on The potential of the first voltage node. The dynamic random access memory device of claim 1, further comprising a power charge pump, the output end of which is coupled to the first voltage node; and when the switching device is turned on, the first voltage is used The potential of the node is pulled up to a rated voltage. The dynamic random access memory device of claim 1, further comprising a logic device for controlling the switching device according to the updated mode signal output by the controller and the pre-start signal. The dynamic random access memory device of claim 5, wherein the logic device controls the switching device when the controller stops outputting the update mode signal to cause the dynamic random access memory device to leave the self-refresh mode Turn it on. A control method for a dynamic random access memory device, the dynamic random access memory device comprising a memory array, a switching device disposed between a first voltage node and a second voltage node, and the second The voltage node is coupled to the memory array, and a controller capable of outputting an update mode signal, an update trigger signal, and a pre-start signal, and the DRAM device should update the mode signal to enter a self-updating The control method includes: in the self-updating mode, after the self-updating operation is performed by the DRAM device, the controller re-outputs the pre-start signal and turns the switching device on, so that the The potential of the two voltage nodes increases to the potential of the first voltage node; afterwards, the controller outputs the update trigger signal to cause the dynamic random access memory device to perform a self-updating operation on the memory array. The method for controlling a dynamic random access memory device according to claim 7 of the patent scope further includes: A voltage clamp disposed between the first voltage node and the second voltage node is configured to maintain a potential of the second voltage node above a reference voltage when the switching device is turned off. The control method of the dynamic random access memory device of claim 7, further comprising: using a decoupling capacitor coupled between the first voltage node and a ground, when the switching device is turned on, The potential of the first voltage node is quickly restored. The control method of the dynamic random access memory device of claim 7, further comprising: a power supply charge pump coupled to the first voltage node by an output terminal, when the switching device is turned on, the first The potential of a voltage node is pulled up to a nominal voltage. The control method of the dynamic random access memory device of claim 7, further comprising: using a logic device to control the switching device according to the updated mode signal output by the controller and the pre-start signal . The control method of the dynamic random access memory device of claim 11, further comprising: when the controller stops outputting the update mode signal to cause the dynamic random access memory device to leave the self-updating mode, the logic The device controls the switching device to turn it on.