TWI667881B - Power on clear circuit - Google Patents

Abstract

A power-on cleaning circuit includes: a bandgap voltage generating circuit, a voltage dividing circuit, a common gate comparing circuit, and a hysteresis buffer. The bandgap voltage generating circuit is connected between the power terminal and the grounding terminal, and comprises: a power taking circuit, a voltage stabilizing circuit and a feedback circuit; the voltage dividing circuit is connected between the power source and the ground end; the common gate comparing circuit is connected to Between the power supply and the ground; the hysteresis buffer is connected to the feedback loop, and the hysteresis buffer performs hysteresis buffering according to the voltage of the feedback loop, thereby generating a power-on clear signal.

Description

Power-on clear circuit

The present invention relates to a power-on cleaning circuit, and more particularly to an electrical-clearing circuit having a fixed bandgap voltage and a streamlined structure.

When designing the circuit, a reset mechanism is often added to avoid the logic error of the system components when the power is raised but the operating voltage of each component is not reached at the beginning of the power supply.

Referring to Fig. 1, there is shown an example of an electrical clearing circuit in accordance with the prior art. The power-on clearing circuit 100 is characterized by a general band-gap voltage circuit modification to achieve a power-on clear reset, but ultimately does not provide a steady-state bandgap voltage.

Referring to Figure 2, another example of an electrical clear circuit in accordance with conventional techniques is illustrated. The power-on-clear circuit 200 specifically implements a power-on reset reset characteristic with the bandgap voltage circuit in conjunction with the comparator 201, which provides a steady-state bandgap voltage compared to the power-on-clear circuit 100, but the comparator 201 has a complicated configuration. , costing wafer area and cost.

In view of the above problems of the prior art, the present invention provides a power-on cleaning circuit including: a bandgap voltage generating circuit, a voltage dividing circuit, a common gate comparing circuit, and a hysteresis buffer. The bandgap voltage generating circuit is connected between the power terminal and the grounding terminal, and generates a bandgap voltage. The bandgap voltage generating circuit comprises: a power taking loop, a voltage stabilizing circuit and a feedback loop, and the power take loop is connected to the power terminal, and the voltage regulator is connected. The circuit is connected between the power take-off circuit and the ground end, and the feedback circuit is connected between the voltage stabilizing circuit and the power take-off circuit, wherein the power take-off circuit comprises a switch, the switch comprises an input end, an output end and a control end, and the input end is connected to The power end, the output end is connected to the voltage stabilizing circuit, the control end is connected to the feedback loop, and the control end controls the degree of conduction of the switch from the input end to the output end to generate a band gap voltage between the voltage stabilizing circuit and the power take-off circuit. The voltage dividing circuit is connected to the power supply end and includes a voltage dividing point; the common gate comparing circuit is connected between the power source and the ground end, and includes a first transistor, a second transistor, a first reference current source, and a second a reference current source, the first transistor is connected in series between the power take-off circuit and the voltage stabilizing circuit, the drain of the second transistor and the gate are connected, and are connected to the first transistor in a common gate manner, first The current source is connected between the power terminal and the second transistor, the second reference current source is connected between the second transistor and the ground, and the second reference current source is connected to the second transistor. The connection is connected to the voltage dividing point; the hysteresis buffer is connected to the feedback loop, and the hysteresis buffer performs hysteresis buffering according to the voltage of the feedback loop, thereby generating a power-on clear signal.

Preferably, the voltage stabilizing circuit can include an error amplifier.

Preferably, the voltage dividing circuit may include a first resistor and a second resistor connected in series with the first resistor, the voltage dividing point is located at a junction of the first resistor and the second resistor, and the voltage dividing circuit generates a fraction at the voltage dividing point. Voltage.

Preferably, the voltage stabilizing circuit may include a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a third transistor, and a fourth transistor; wherein the third resistor is connected in series with the fourth resistor, and the error amplifier is positive The terminal input is connected between the third resistor and the fourth resistor; the sixth resistor is connected between the fifth resistor and the negative terminal input of the error amplifier; and the third resistor is connected to the other end of the positive terminal and connected to the fifth resistor. And a sixth resistor; the third transistor is connected between the opposite end of the fourth terminal connected to the positive terminal input and the ground terminal; and the fourth transistor is connected between the negative terminal input and the ground terminal.

Preferably, the fifth resistor can be connected to the first transistor, and the output of the error amplifier is connected to the control terminal.

Preferably, the switch may be a transistor, the input end is a source of the transistor, the output end is a drain of the transistor, and the control end is a gate of the transistor.

Preferably, the hysteresis buffer can contain two inverters.

Preferably, the first resistor and the second resistor may be variable resistors.

Preferably, the steady state voltage of the bandgap voltage generating circuit can be 1.2 volts.

Preferably, the resistance values of the first resistor and the second resistor may be equal.

Preferably, the voltage of the power supply can be at least 2 volts.

The technical features, contents, advantages and advantages of the present invention will be understood by the reviewing committee, and the present invention will be described in detail with reference to the accompanying drawings. The subject matter is only for the purpose of illustration and supplementary instructions. It is not necessarily the true proportion and precise configuration after the implementation of the present invention. Therefore, the proportion and configuration relationship of the attached drawings should not be interpreted or limited. , first and foremost.

Please refer to FIG. 3, which illustrates an electrical clear circuit in accordance with an embodiment of the present invention.

The power-on cleaning circuit 300 includes a bandgap voltage generating circuit 301, a voltage dividing circuit 302, a common gate comparing circuit 303, and a hysteresis buffer 304.

The bandgap voltage generating circuit 301 is connected between the power supply terminal VDD and the ground terminal, and generates a bandgap voltage. The bandgap voltage generating circuit 301 includes: a power taking circuit 3011, a voltage stabilizing circuit 3012, and a feedback circuit 3013. The circuit 3011 is connected to the power supply terminal, the voltage stabilization circuit 3012 is connected between the power take-off circuit 3011 and the ground terminal, and the feedback circuit 3013 is connected between the voltage stabilization circuit 3012 and the power take-off circuit 3011. The power take-off circuit 3011 includes the switch 3010. The switch 3010 includes an input end, an output end, and a control end (not shown). The input end is connected to the power supply terminal VDD, the output end is connected to the voltage stabilizing circuit 3012, the control end is connected to the feedback loop 3013, and the control end is a control switch. The degree of conduction from the input terminal to the output terminal generates a bandgap voltage between the voltage stabilizing circuit 3012 and the power take-off circuit 3011.

The voltage dividing circuit 302 is connected between the power source and the ground. The voltage dividing circuit 302 includes a first resistor R1 and a second resistor R2 connected in series with the first resistor R1. In an embodiment, the voltage dividing circuit 302 The junction of the first resistor R1 and the second resistor R2 is a voltage dividing point, and a voltage dividing voltage V _A is generated at the voltage dividing point.

The common gate comparison circuit 303 is connected between the power supply VDD and the ground, and includes a first transistor 3031, a second transistor 3032, a first reference current source 3033, and a second reference current source 3034. The first transistor 3031 string Connected between the power take-off circuit 3011 and the voltage stabilizing circuit 3012, the drain of the second transistor 3032 and the gate are connected, and are connected to the first transistor 3031 in a common gate manner, and the first reference current source 3033 is connected. Connected between the power supply terminal VDD and the second transistor 3032, the second reference current source 3034 is connected between the second transistor 3032 and the ground, and the second reference current source 3034 is connected to the second transistor 3032. The system is electrically connected between the first resistor R1 and the second resistor R2.

The hysteresis buffer 304 is connected to the feedback loop 3013, and the hysteresis buffer 304 performs hysteresis buffering according to the voltage of the feedback loop 3013 to generate a power-on clear signal.

According to an embodiment of the invention, the voltage stabilizing circuit 3012 includes an error amplifier 3014, a third resistor 3015, a fourth resistor 3016, a fifth resistor 3017, a sixth resistor 3018, a third transistor 3019, and a fourth transistor 3020; The third resistor 3015 is connected in series with the fourth resistor 3016, and the positive terminal input of the error amplifier 3014 is connected between the third resistor 3015 and the fourth resistor 3016; the sixth resistor 3018 is connected in series with the fifth resistor 3017 and the negative terminal of the error amplifier 3014. The third resistor 3015 is connected between the other end of the positive terminal input of the error amplifier 3014 and the other end is connected between the fifth resistor 3017 and the sixth resistor 3018; the third transistor 3019 is connected to the fourth resistor 3016 and connected to the error amplifier 3014. One end of the positive terminal input is opposite the other end and the ground terminal; and the fourth transistor 3020 is connected between the negative terminal input of the error amplifier 3014 and the ground terminal. The fifth resistor 3017 is connected to the first transistor 3031, and the output of the error amplifier 3014 is connected to the control terminal. The switch 3010 is a transistor, the input end is the source of the transistor, the output end is the drain of the transistor, and the control end is the gate of the transistor. In one embodiment, the switch 3010, the first transistor 3031, and the second transistor 3032 may be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a third transistor 3019, and a third The quad transistor 3020 may be a bipolar junction transistor (BJT), but is not limited thereto.

Please refer to FIG. 3 and FIG. 4 at the same time. FIG. 4 is a diagram showing the voltage curve of the electric cleaning circuit according to the embodiment shown in FIG. 3. As shown in FIG. 4, the power-on cleaning circuit 300 generates the accurate upper power-clearing signal POC, and at the same time, the steady-state bandgap voltage BG can be maintained after the power supply VDD rises. Wherein, as the power supply VDD is slowly started, the bandgap voltage BG is also slowly activated, so that the error amplifier 3014 starts with the negative terminal voltage IN- being greater than the positive terminal voltage IN+, and the hysteresis buffer 304 generates the output to be negative, and the power-on clear signal POC is negative; when the error amplifier 3014 voltage is slowly increased, it is just the set value of the precise power supply VDD. At this time, the positive terminal voltage IN+ is gradually equal to the negative terminal voltage IN-, and an output voltage is generated at this time, and the hysteresis buffer 304 is passed. The output is positive, and the power-on clear signal POC is equal to the power supply VDD.

Referring to FIG. 4, when the power supply climbs and is in phase A, the bandgap voltage BG is not steady state, and the negative terminal voltage IN- of the error amplifier 3014 is greater than the positive terminal voltage IN+, and the OPOUT signal is low, and the current Ip is greater than the current In, The hysteresis buffer 304 generates an upper power clear signal POC that is negative. When in phase B, the bandgap voltage BG is steady state, the negative terminal voltage IN- of the error amplifier 3014 is equal to the positive terminal voltage IN+, at which time the OPOUT signal is high, and the current Ip is equal to the current In, and the hysteresis buffer 304 generates a power. Clear the signal POC to positive.

Referring to FIG. 3 and FIG. 4 simultaneously, according to an embodiment of the invention, the steady state voltage of the bandgap voltage generating circuit 301 is 1.2 volts, and the first resistor R1 and the second resistor R2 are equal (R1=R2) due to The divided voltage V _A = VDD * R1/(R2 + R1), when the power supply VDD is 2 volts, the divided voltage V _A is 1 volt, which is less than the steady-state point of the bandgap voltage BG (1.2 volts), and the current Ip is greater than the current In, and the error amplifier 3014 negative terminal voltage IN- is greater than the positive terminal voltage IN+, the OPOUT signal is low, and the hysteresis buffer 304 generates the upper power clear signal POC to be negative. When the power supply VDD continues to climb until the divided voltage V _A is equal to or greater than the steady-state point of the bandgap voltage BG (1.2 volts), the current Ip is equal to the current In, and the negative terminal voltage IN- of the error amplifier 3014 is equal to the positive terminal voltage IN+, and the OPOUT signal is High, hysteresis buffer 304 generates a power-on clear signal POC that is positive.

As described above, the resistance values of the first resistor R1 and the second resistor R2 determine the magnitude of the power supply VDD of the power-on clear signal POC from the negative turn-off timing, that is, the different resistance values through the first resistor R1 and the second resistor R2. , can change the power-on clear signal POC.

According to the above discussion, according to the present invention, the upper power clearing circuit generates the upper power clear signal POC having a fixed bandgap voltage BG, and according to the invention, the structure of the power clearing circuit is simplified, thereby saving the occupied area and further reducing the cost. .

The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.

100, 200, 300‧‧‧ power-on cleaning circuit

201‧‧‧ Comparator

301‧‧‧gap voltage generation circuit

302‧‧‧voltage circuit

303‧‧‧Common gate comparison circuit

304‧‧‧ hysteresis buffer

3010‧‧‧ switch

3011‧‧‧Electric circuit

3012‧‧‧Variable circuit

3013‧‧‧Return loop

3014‧‧‧Error amplifier

3015‧‧‧ Third resistor

3016‧‧‧fourth resistor

3017‧‧‧ fifth resistor

3018‧‧‧6th resistor

3019‧‧‧ Third transistor

3020‧‧‧4th transistor

3031‧‧‧First transistor

3032‧‧‧Second transistor

3033‧‧‧First reference current source

3034‧‧‧Second reference current source

BG‧‧‧gap voltage

EA‧‧‧Error Amplifier

IN-‧‧‧Error amplifier negative terminal voltage

IN+‧‧‧Error amplifier positive terminal voltage

Ip‧‧‧ current

In‧‧‧ Current

POC‧‧‧Power-on clear signal

R1‧‧‧first resistance

R2‧‧‧second resistance

VDD‧‧‧ power terminal

GND‧‧‧ ground terminal

V _A ‧‧ ‧ voltage divider

Fig. 1 is a diagram showing an example of an electric cleaning circuit according to the prior art.

Figure 2 is a diagram showing another example of an electrical clearing circuit in accordance with the prior art.

Figure 3 is a diagram showing an electrical clear circuit in accordance with an embodiment of the present invention.

Figure 4 is a diagram showing voltage curves of an electrical clear circuit in accordance with an embodiment of the present invention.

Claims (10)

A power-on cleaning circuit includes: a bandgap voltage generating circuit connected between a power terminal and a ground terminal, and generating a bandgap voltage, the bandgap voltage generating circuit comprising: a power take-off loop, connected to a power supply terminal; a voltage stabilizing circuit connected between the power take-off circuit and the ground terminal; and a feedback circuit connected between the voltage stabilizing circuit and the power take-off circuit; wherein the power take-off circuit includes a a switch, the switch includes an input end connected to the power supply end; an output end connected to the voltage stabilizing circuit; and a control end connected to the feedback loop, and the control end controls the switch from the input end a level of conduction to the output terminal to generate the bandgap voltage between the voltage stabilizing circuit and the power take-off circuit; a voltage dividing circuit connected to the power terminal and including a voltage dividing point; a common gate comparing circuit Connected between the power source and the ground terminal, comprising: a first transistor connected in series between the power take-off circuit and the voltage stabilizing circuit; a second transistor having a drain and a gate Connected with the system The second crystal is connected to the second transistor and the ground Between the terminals, and the second reference current source and one end of the second transistor are electrically connected to the voltage dividing point; a hysteresis buffer is connected to the feedback loop, and the hysteresis buffer is based on the back The voltage of the loop is subjected to hysteresis buffering, thereby generating a power-on clear signal. The upper power clearing circuit of claim 1, wherein the voltage stabilizing circuit comprises an error amplifier. The power-clearing circuit of claim 2, wherein the voltage dividing circuit comprises a first resistor and a second resistor connected in series with the first resistor, wherein the voltage dividing point is located at the first resistor At the junction of the second resistor, the voltage dividing circuit generates a divided voltage at the voltage dividing point. The power-removing circuit of claim 3, wherein the voltage stabilizing circuit comprises a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a third transistor, and a fourth a transistor; wherein the third resistor is connected in series with the fourth resistor, and one positive terminal input of the error amplifier is connected between the third resistor and the fourth resistor; the sixth resistor is serially connected to the fifth resistor and Between one of the negative terminals of the error amplifier; the third resistor is connected to the other end of the positive terminal and is connected between the fifth resistor and the sixth resistor; the third transistor is connected to the fourth resistor Connecting the opposite end of one end of the positive input and the ground; and the fourth transistor is coupled between the negative input and the ground. The upper power removing circuit of claim 4, wherein the fifth resistor is connected to the first transistor, and an output terminal of the error amplifier is connected to the control terminal. The electric power clear circuit according to claim 1, wherein the open circuit is a transistor, the input end is a source of the transistor, and the output end is a drain of the transistor, and the control is The end is one of the gates of the transistor. The upper power clearing circuit of claim 1, wherein the hysteresis buffer comprises two inverters. The upper power removal circuit of claim 3, wherein the first resistor and the second resistor are variable resistors. The upper power clearing circuit of claim 1, wherein the one of the bandgap voltage generating circuits has a steady state voltage of about 1.2 volts. The upper power clearing circuit of claim 3, wherein the first resistor and the second resistor have equal resistance values.