TWI667793B - Semiconductor device and method for forming the same - Google Patents

Abstract

Embodiments of the present invention relate to a semiconductor device. The semiconductor device includes a substrate and a first III-V semiconductor layer disposed on the substrate. The first III-V semiconductor layer includes a fin structure, and the fin structure includes a top surface, a first sidewall, and a second sidewall opposite the first sidewall. The above semiconductor device also includes a second III-V semiconductor layer disposed on the first III-V semiconductor layer. The first III-V semiconductor layer and the second III-V semiconductor layer comprise a different material, and the second III-V semiconductor layer covers the top surface, the first sidewall and the second sidewall of the fin structure, A heterojunction is formed along the top surface, the first sidewall, and the second sidewall of the fin structure. The above semiconductor device also includes a gate electrode disposed on the second III-V semiconductor layer.

Description

Semiconductor device and method of forming same

Embodiments of the present invention relate to a semiconductor device, and more particularly to a High Electron Mobility Transistor (HEMT) or a High Hole Mobility Transistor (HHMT).

Semiconductor devices have been widely used in various electronic products such as, for example, high power devices, personal computers, mobile phones, and digital cameras. The semiconductor device is usually fabricated by sequentially depositing an insulating layer or a dielectric layer material, a conductive layer material, and a semiconductor layer material on a semiconductor substrate, and then patterning the various material layers formed by using a lithography process, whereby the semiconductor substrate is formed thereon. Circuit parts and components are formed on top.

Among them, high electron mobility transistor or high hole mobility transistor is widely used in high power devices due to its high output voltage and high breakdown voltage.

However, existing high electron mobility transistors or high hole mobility transistors still have some disadvantages and are not satisfactory in all respects.

Embodiments of the present invention provide a semiconductor device. The semiconductor device includes a substrate and a first III-V semiconductor layer disposed on the substrate. The first III-V semiconductor layer includes a fin structure, and the fin structure includes a top surface, a first sidewall, and a second sidewall opposite to the first sidewall. The semiconductor device further includes a second III-V semiconductor layer disposed on the first III-V semiconductor layer. The first III-V semiconductor layer and the second III-V semiconductor layer comprise a different material, and the second III-V semiconductor layer covers a top surface, a first sidewall, and a second of the fin structure a sidewall to form a heterojunction along a top surface, a first sidewall, and a second sidewall of the fin structure. The semiconductor device also includes a gate electrode disposed on the second III-V semiconductor layer.

Embodiments of the present invention also provide a method of forming a semiconductor device. The above method includes providing a substrate and forming a first III-V semiconductor layer on the substrate. The first III-V semiconductor layer includes a fin structure, and the fin structure includes a top surface, a first sidewall, and a second sidewall opposite to the first sidewall. The above method also includes forming a second III-V semiconductor layer on the first III-V semiconductor layer. The first III-V semiconductor layer and the second III-V semiconductor layer comprise a different material, and the second III-V semiconductor layer covers a top surface, a first sidewall, and a second of the fin structure a sidewall to form a heterojunction along a top surface, a first sidewall, and a second sidewall of the fin structure. The above method also includes forming a gate electrode on the second III-V semiconductor layer.

10‧‧‧ Vacant high electron mobility transistor

10'‧‧‧Enhanced high electron mobility transistor

100‧‧‧Substrate

200‧‧‧First III-V semiconductor layer

202‧‧‧Fin structure

Top surface of the 202T‧‧‧ fin structure

The first side wall of the 202S1‧‧‧ fin structure

The second side wall of the 202S2‧‧‧ fin structure

402‧‧‧Second III-V semiconductor layer

404‧‧‧Two-dimensional electronic cloud

502‧‧‧Insulation

504‧‧‧gate electrode

506‧‧‧Source/drain electrodes

508‧‧‧First doped III-V semiconductor layer

20‧‧‧ Vacant high hole mobility transistor

20'‧‧‧Enhanced high hole mobility transistor

600‧‧‧Substrate

602‧‧‧First III-V semiconductor layer

604‧‧‧Fin structure

Top surface of the 604T‧‧‧ fin structure

First side wall of the 604S1‧‧‧ fin structure

The second side wall of the 604S2‧‧‧ fin structure

606‧‧‧Second III-V semiconductor layer

608‧‧‧First doped III-V semiconductor layer

610‧‧‧Insulation

612‧‧‧gate electrode

614‧‧‧Source/drain electrodes

616‧‧‧Two-dimensional hole cloud

618‧‧‧Second-doped III-V semiconductor layer

w‧‧‧Width

H‧‧‧height

t ₁ ‧‧‧thickness

X ₁ -X ₂ ‧‧‧ hatching

Y ₁ -Y ₂ ‧‧‧ hatching

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It is noted that the various features are not drawn to scale and are merely illustrative. In fact, the size of the components may be enlarged or reduced to clearly show an embodiment of the present invention. Technical characteristics.

The figures 1, 2, 3, 4A, and 5A are a series of partial perspective views for explaining the formation method of the high electron mobility transistor 10 of the first embodiment of the present invention.

Fig. 4B is a cross-sectional view showing the process of the high electron mobility transistor 10 of the first embodiment of the present invention taken along the section line X ₁ -X _{2 of} Fig. 4A.

Fig. 5B is a partial cross-sectional view showing the high electron mobility transistor 10 of the first embodiment of the present invention taken along the line Y _{1 -} Y _{2 of} Fig. 5A.

Figure 5C is a partial perspective view of a high electron mobility transistor 10', in accordance with some embodiments of the present invention.

5D based on FIG. 5C along line Y ₁ -Y ₂ of FIG depicts a portion of some of the high electron mobility transistor of embodiment 10 'of a cross-sectional view of the invention.

Figure 6A is a partial perspective view of a high hole mobility transistor 20 in accordance with a second embodiment of the present invention.

Fig. 6B is a partial cross-sectional view showing the high hole mobility transistor 20 of the second embodiment of the present invention taken along the section line X ₁ -X _{2 of} Fig. 6A.

Fig. 6C is a partial cross-sectional view showing the high hole mobility transistor 20 of the second embodiment of the present invention taken along the line Y _{1 -} Y _{2 of} Fig. 6A.

Figure 6D is a partial perspective view of a high hole mobility transistor 20', in accordance with some embodiments of the present invention.

Based on a partial sectional view of FIG. 6E Y ₁ -Y ₂ illustrates a cross-sectional view along the line of FIG. 6D some of the embodiments of the high hole mobility transistor according to the present invention, 20 'of.

The following disclosure provides many different embodiments or examples to Implement the different features of the case. The following disclosure sets forth specific examples of various components and their arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if an embodiment of the present invention describes that a first feature is formed on or above a second feature, that is, it may include an embodiment in which the first feature is in direct contact with the second feature, and may also include Additional features are formed between the first feature and the second feature described above, such that the first feature and the second feature may not be in direct contact with each other. In addition, the different examples disclosed below may reuse the same reference symbols and/or labels. These repetitions are not intended to limit the specific relationship between the various embodiments and/or structures discussed.

It will be appreciated that additional operational steps may be performed before, during or after the method, and that in other embodiments of the method, portions of the operational steps may be substituted or omitted.

In addition, space-related terms such as "below", "below", "lower", "above", "higher" and similar terms may be used. To facilitate the description of the relationship between one element or feature(s) and another element or feature(s) in the drawings, these spatially related terms include the various orientations of the device in operation or operation, and the description Orientation. When the device is turned to a different orientation (rotated 90 degrees or other orientation), the spatially related adjectives used therein will also be interpreted in terms of the orientation after the turn.

The high electron mobility transistor (HEMT) or high hole mobility transistor (HHMT) of the embodiment of the invention includes a III-V semiconductor layer having a fin structure. The above fin structure can increase a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (two-dimensional hole gas). The area of 2DHG) therefore has better device performance.

[First Embodiment: High Electron Mobility Transistor]

Fig. 1 is a partial perspective view showing the initial steps of the method for forming a high electron mobility transistor of the present embodiment. First, as shown in Fig. 1, a substrate 100 is provided. In the present embodiment, the substrate 100 is a sapphire substrate, but the invention is not limited thereto. For example, the substrate 100 may include an elemental semiconductor such as germanium or germanium. In some embodiments, substrate 100 can include a compound semiconductor such as SiC, GaAs, InAs, or InP. In some embodiments, substrate 100 can include an alloy semiconductor such as SiGe, SiGeC, GaAsP, or GaInP. In some embodiments, the substrate 100 can be a single crystal substrate, a multi-layer substrate, a gradient substrate, other suitable substrates, or a combination thereof. In some embodiments, the substrate 100 may further include a semiconductor on insulator (SOI) substrate (eg, an insulating layer upper germanium substrate or an insulating layer upper germanium substrate), and the insulating layer upper semiconductor substrate may include a bottom plate and a set a buried oxide layer on the bottom plate and a semiconductor layer disposed on the buried oxide layer.

In some embodiments, the substrate 100 can include a buffer layer (not shown) to avoid or reduce defects due to lattice mismatch between the substrate 100 and the semiconductor layers thereon. For example, the buffer layer may include AlN, AlGaN, other suitable materials, or a combination thereof.

Next, as shown in FIG. 2, the first III-V semiconductor layer 200 is formed on the substrate 100. In some embodiments, the first III-V semiconductor layer 200 can include an undoped III-V semiconductor material. For example, in the present embodiment, the first III-V semiconductor layer 200 is formed of undoped GaN, but the present invention Not limited to this. In some other embodiments, the first III-V semiconductor layer 200 may also include AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V materials, or combinations thereof. In some embodiments, molecular-beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy can be used. , HVPE), other suitable methods, or a combination thereof, to form the first III-V semiconductor layer 200 over the substrate 100.

Next, as shown in FIG. 3, the first III-V semiconductor layer 200 is patterned to form one or more fin structures 202. For example, low-pressure chemical vapor deposition (LPCVD), plasma-assisted chemical vapor deposition (PECVD), other suitable processes, or a combination thereof may be used. Forming a hard mask layer (not shown) on the first III-V semiconductor layer 200, including a material such as tantalum nitride, tantalum oxide, etc., and then performing a lithography process (for example, photoresist coating (resist) Coating), soft baking, exposure, post-exposure baking, developing, forming a patterned photoresist on the hard mask layer, and then using the above pattern The photoresist is used as an etch mask for an etching process (eg, wet etching, dry etching) to pattern the hard mask layer. Next, the first III-V semiconductor layer 200 may be etched using an etched mask of the pattern as an etch mask (eg, wet etch, dry etch) to form one or more fin structures 202. . For example, the dry etching process described above may include a plasma etching process or a reactive ion etching process.

It should be understood that, for the sake of brevity, the present embodiment is described by taking two fin structures 202 as an example. However, the present invention is not limited thereto, and those skilled in the art may also form other numbers of fins according to design requirements. Sheet structure 202.

In some embodiments, an isolation structure (not shown) may be formed on the substrate 100. For example, chemical vapor deposition (for example, sub-atmospheric chemical vapor deposition (SACVD), high-density plasma chemical vapor deposition (high-density plasma chemical vapor deposition) can be used. , HDPCVD) forms a dielectric material on the first III-V semiconductor layer 200 and its fin structure 202, and then performs an etch-back process to remove excess dielectric material to form isolation between the fin structures 202. In some embodiments, the top surface of the isolation structure is lower than the top surface 202T of the fin structure 202. For example, the isolation structure may include hafnium oxide, tantalum nitride, niobium carbide, niobium oxycarbonate, and the like. Suitable materials or combinations of the above.

Referring to FIG. 3, the fin structure 202 can have a top surface 202T, two opposing first sidewalls 202S1, and a second sidewall 202S2. In some embodiments, the second III-V semiconductor layer (such as the second III-V semiconductor layer 402 shown in FIG. 4A) formed in the subsequent process covers the top surface 202T of the fin structure 202. The first sidewall 202S1 and the second sidewall 202S2 can increase the area of the two-dimensional electron cloud (2DEG) to enhance the performance of the high electron mobility transistor, which will be described in detail later.

As shown in FIG. 3, the fin structure 202 has a height h and a width w. In some embodiments, the ratio of the width w to the height h (ie, w/h) is less than 0.2, and the two-dimensional electron cloud cannot be formed on the first sidewall 202S1 and the second sidewall 202S2. on. In some other embodiments, the ratio of width w to height h is greater than 10, and a two-dimensional electron cloud cannot be formed on top surface 202T. Therefore, in the present embodiment, the ratio of the width w to the height h is 0.2 to 10 to avoid the above disadvantages caused by the ratio of the width w to the height h being too large or too small. For example, the height h may be 0.1 to 2 μm, and the width w may be 0.1 to 2 μm.

In some embodiments, the distance (or pitch) d of two adjacent fin structures 202 may be 0.04 to 10 μm in a direction perpendicular to the sidewalls of the fin structure 202.

Next, as shown in FIGS. 4A and 4B, the second III-V semiconductor layer 402 is formed on the first III-V semiconductor layer 200. In detail, FIG. 4B is a cross-sectional view taken along section line X ₁ -X ₂ of FIG. 4A, and the section lines X ₁ -X ₂ are substantially perpendicular to the side walls of the fin structure 202.

In some embodiments, the second III-V semiconductor layer 402 and the first III-V semiconductor layer 200 comprise different materials to form a heterojunction, and may be in the first III-V semiconductor layer 200. A two-dimensional electron cloud 404 is formed that can act as a carrier for a high electron mobility transistor. In some embodiments, the second III-V semiconductor layer 402 comprises an undoped III-V semiconductor material. For example, in the present embodiment, the second III-V semiconductor layer 402 is formed of undoped AlGaN, and thus can be formed with the first III-V semiconductor layer 200 formed of undoped GaN. Together, a heterojunction is formed, but the invention is not limited thereto. In some other embodiments, the second III-V semiconductor layer 402 can also include GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V materials, or combinations thereof. For example, molecular beam epitaxy, organometallic chemical vapor deposition, hydride vapor epitaxy, and other suitable methods can be used. The method or a combination thereof forms a second III-V semiconductor layer 402 over the first III-V semiconductor layer 200.

As shown in FIG. 4B, the second III-V semiconductor layer 402 simultaneously covers the top surface 202T, the first sidewall 202S1, and the second sidewall 202S2 of the fin structure 202 of the first III-V semiconductor layer 200. In other words, the second III-V semiconductor layer 402 of the high electron mobility transistor of the embodiment of the present invention has a larger contact area with the first III-V semiconductor layer 200 than the conventional planar device. Therefore, the area of the two-dimensional electron cloud can be increased, so that the high electron mobility transistor of the embodiment of the present invention can have a larger current during operation to improve device performance. For example, high electron mobility transistors of some embodiments of the invention operate at currents that are two to five times greater than conventional planar devices.

In some embodiments, as shown in FIGS. 4A and 4B, the second III-V semiconductor layer 402 is conformally formed over the fin structure 202 of the first III-V semiconductor layer 200. In other words, in such embodiments, the space between the fin structures 202 is not filled by the second III-V semiconductor layer 402, so that the subsequently formed gate electrodes can extend between the fin structures 202. In the space (such as the gate electrode 504 shown in FIG. 5A), the contact area between the gate electrode and the second III-V semiconductor layer 402 can be increased, so that the gate electrode can be more effective when the device is operated. Control the current.

In some embodiments, as shown in Figure 4B, the thickness of the second III-V semiconductor layer 402 may be t ₁ of 0.005 to 0.1μm.

Next, as shown in FIG. 5A, an insulating layer 502 is formed over the second III-V semiconductor layer 402, which protects the underlying film layer and provides physical isolation and structural support. For example, the insulating layer 502 may include SiO ₂ , SiN ₃ , SiON, Al ₂ O ₃ , AlN, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole ( Polybenzoxazole, PBO), other insulating materials or combinations of the above. In some embodiments, the insulating layer 502 can be formed using chemical vapor deposition (eg, organometallic chemical vapor deposition), spin-coating, other suitable methods, or a combination thereof. In some embodiments, the insulating layer 502 has a flat top surface via a chemical mechanical polishing (CMP) process.

Next, as shown in FIG. 5A, a gate electrode 504 is formed over the second III-V semiconductor layer 402, and a source/drain electrode 506 is formed on both sides of the gate electrode 504 to form the embodiment. High electron mobility transistor 10. In some embodiments, as shown in FIG. 5A, the gate electrode 504 covers the second III-V semiconductor layer 402 on the top surface 202T of the fin structure 202, and further covers the sidewalls 202S1 and 202S2 of the fin structure 202. The second III-V semiconductor layer 402 is on. In other words, in such embodiments, the contact area between the gate electrode 504 and the second III-V semiconductor layer 402 is relatively large, such that the gate electrode 504 can more effectively control current during device operation.

For example, the gate electrode 504 can comprise a metal material, a metal telluride, a polysilicon, other suitable conductive materials, or a combination thereof. For example, source/drain electrodes 506 can include Ti, Al, Au, Pd, other suitable metallic materials, alloys thereof, or combinations thereof. In some embodiments, a lithography process and an etch process may be performed to form a trench corresponding to the gate electrode 504 and a trench corresponding to the source/drain electrode 506 in the insulating layer 502, followed by a chemical gas. Phase deposition method, physical vapor deposition method (such as evaporation or sputtering), electroplating, atomic layer deposition, other suitable methods, or a combination thereof, in which the conductive material is filled in the trench The gate electrode 504 and the source/drain electrode 506 are formed.

Referring to Fig. 5B, a partial cross-sectional view of the high electron mobility transistor 10 of the present embodiment is shown along the section line Y ₁ -Y _{2 of} Fig. 5A. In detail, the hatching line Y ₁ -Y ₂ is perpendicular to the aforementioned section line X ₁ -X ₂ . As shown in FIG. 5B, the high electron mobility transistor 10 is a depletion mode (normally-on) semiconductor device, and the fin structure 202 under the gate electrode 504 can serve as a channel region. The fin structure 202 on either side of the gate electrode 504 can serve as a source/drain region.

In summary, the high electron mobility electron crystal system of the present embodiment includes a III-V semiconductor layer having a fin structure. The above fin structure can increase the contact area of the heterojunction, thereby increasing the area of the two-dimensional electron cloud and improving the device performance.

Some variations of this embodiment are provided below. In some embodiments, as shown in FIGS. 5C and 5D, the first doping III-V is further disposed between the gate electrode 504 of the high electron mobility transistor 10 ′ and the second III-V semiconductor layer 402 . The family semiconductor layer 508 is such that the high electron mobility transistor 10' is an enhanced mode (ie, a normally-off) semiconductor device.

In some embodiments, the first doped III-V semiconductor layer 508 can comprise a P-type doped III-V semiconductor material, which can include magnesium, other suitable dopants, or a combination thereof. For example, in the present embodiment, the first doped III-V semiconductor layer 508 is formed of P-doped GaN (P-GaN), but the invention is not limited thereto. In some other embodiments, the first doped III-V semiconductor layer 508 may also include P-type doped AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V families. Material or a combination of the above.

For example, the dopant concentration of the dopant in the first doped III-V semiconductor layer 508 may be 1E15/cm ³ to 1E20/cm ³ .

In some embodiments, undoped may be formed using molecular beam epitaxy, metal chemical vapor deposition, hydride vapor epitaxy, other suitable methods, or combinations thereof, prior to the step of forming insulating layer 502. The III-V semiconductor blanket is overlying the second III-V semiconductor layer 402, and the dopant is implanted in the undoped III-V semiconductor blanket layer using a process such as ion implantation. To form a doped III-V semiconductor blanket layer, and then pattern the doped III-V semiconductor blanket layer to form a first doped III-V semiconductor layer 508. For example, the above-described patterning process may include a lithography process, an etching process, other suitable processes, or a combination thereof. In some other embodiments, the first doped III-V semiconductor layer 508 can also be formed using in-situ doping.

Since the enhanced high electron mobility transistor 10' also includes a III-V semiconductor layer having a fin structure, it also has a large-area two-dimensional electron cloud to improve device performance.

[Second embodiment: high hole mobility transistor]

6A, 6B, and 6C are a partial perspective view and a partial cross-sectional view showing the depletion type high hole mobility transistor 20 of the present embodiment. In detail, FIG. 6B is a partial cross-sectional view of the depletion-type high-porosity mobility transistor 20 taken along the section line X ₁ -X _{2 of} FIG. 6A, and FIG. 6C is along the A partial cross-sectional view of the depleted high-porosity mobility transistor 20 depicted by the section line Y ₁ -Y _{2 of} Figure 6A.

As shown in FIGS. 6A, 6B, and 6C, the depletion type high hole mobility transistor 20 may include a substrate 600 and a first III-V semiconductor disposed on the substrate 600. The layer 602, the second III-V semiconductor layer 606 disposed on the first III-V semiconductor layer 602, and the first doped III-V semiconductor layer 608 disposed on the second III-V semiconductor layer 606 The insulating layer 610 disposed on the first doped III-V semiconductor layer 608, the gate electrode 612, and the source/drain electrodes 614 disposed on both sides of the gate electrode 612.

For example, substrate 600 can be the same or similar to substrate 100 of the previous embodiment. For example, the insulating layer 610 may be the same or similar to the insulating layer 502 of the foregoing embodiment, and the insulating layer 610 may be formed using the same or similar to the foregoing forming the insulating layer 502. For example, the gate electrode 612 and the source/drain electrode 614 can be the same or similar to the gate electrode 504 and the source/drain electrode 506 of the previous embodiment, and the gate can be formed using the same or similar to the foregoing. The gate electrode 612 and the source/drain electrode 614 are formed by the electrode 504 and the source/drain electrode 506.

In some embodiments, the second III-V semiconductor layer 606 and the first III-V semiconductor layer 602 comprise different materials to form a heterojunction and on the second III-V semiconductor layer 606. A first doped III-V semiconductor layer 608 is provided to form a two-dimensional hole cloud 616 (as shown in Figures 6A, 6B, 6C) that can serve as a carrier for a high hole mobility transistor.

As shown in FIGS. 6A, 6B, and 6C, the first III-V semiconductor layer 602 of the depletion-type high-porosity mobility transistor 20 also includes a fin structure 604, and the second III-V semiconductor layer 606 and the A doped III-V semiconductor layer 608 covers the top surface 604T of the fin structure 604 and the opposite first sidewalls 604S1 and 604S2, thereby increasing the area of the two-dimensional hole cloud 616 and enhancing the depletion high hole The efficiency of the mobility transistor 20.

In some embodiments, each of the first III-V semiconductor layer 602 and the second III-V semiconductor layer 606 may include the undoped III-V semiconductor material in the foregoing embodiments (eg, GaN, AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V materials or a combination thereof, and the first doped III-V semiconductor layer 608 may include the P-type doping in the foregoing embodiment. A hetero-III-V semiconductor material (eg, P-doped GaN, AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V materials, or combinations thereof). For example, in the present embodiment, the first III-V semiconductor layer 602 includes undoped AlGaN, and the second III-V semiconductor layer 606 includes undoped GaN, and the first doped III-V The family semiconductor layer 608 includes P-doped GaN (P-GaN).

In some embodiments, the dopant concentration in the first doped III-V semiconductor layer 608 can range from 1E13/cm ³ to 1E22/cm ³ .

In some embodiments, the step of forming the III-V semiconductor layer described above may include molecular beam epitaxy, metal chemical vapor deposition, hydride vapor epitaxy, other suitable methods, or a combination thereof. For example, the first doped III-V semiconductor layer 608 can be formed using ion implantation or in-situ doping.

In some embodiments, as shown in FIGS. 6A and 6B, the second III-V semiconductor layer 606 is conformally formed on the fin structure 604 of the first III-V semiconductor layer 602, and the first doping A hetero III-V semiconductor layer 608 is also conformally formed on the second III-V semiconductor layer 606. In other words, in such embodiments, the space between the fin structures 604 is not filled by the second III-V semiconductor layer 606 and the first doped III-V semiconductor layer 608, thus the gate electrode 612 Extendable into the fin The area of contact between the gate electrode 612 and the first doped III-V semiconductor layer 608 is increased in the space between the sheet structures 604 such that the gate electrode 612 can more effectively control current during device operation.

In summary, the depletion type high hole mobility electro-ecological system of the present embodiment includes a III-V semiconductor layer having a fin structure. The above fin structure can increase the contact area of the heterojunction, thereby increasing the area of the two-dimensional hole cloud and improving the device performance.

Some variations of this embodiment are provided below. In some embodiments, as shown in FIGS. 6D and 6E, a second doping III is further disposed between the gate electrode 612 of the high electron mobility transistor 20 ′ and the first doped III-V semiconductor layer 608 . The -V semiconductor layer 618 is such that the high hole mobility transistor 20' is an enhanced semiconductor device.

In some embodiments, the second doped III-V semiconductor layer 618 can comprise an N-type doped III-V semiconductor material, which can include germanium, oxygen, other suitable dopants, or a combination thereof. For example, in the present embodiment, the first III-V semiconductor layer 602 is formed of undoped AlGaN, and the second III-V semiconductor layer 606 is formed of undoped GaN, first The doped III-V semiconductor layer 608 is formed of P-type doped GaN, and the second doped III-V semiconductor layer 618 is formed of N-doped GaN, but the present invention does not limit. In some other embodiments, the second doped III-V semiconductor layer 618 may also include N-type doped AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V families. Material or a combination of the above.

For example, the dopant concentration of the dopant in the second doped III-V semiconductor layer 618 may be 1E15/cm ³ to 1E20/cm ³ .

In some embodiments, undoped may be formed using molecular beam epitaxy, metal chemical vapor deposition, hydride vapor phase epitaxy, other suitable methods, or combinations thereof, prior to the step of forming insulating layer 610. The III-V semiconductor blanket is overlying the first doped III-V semiconductor layer 608, and the dopant is implanted on the undoped III-V semiconductor blanket using an ion implantation process. A doped III-V semiconductor blanket coating is formed in the cladding, and then the doped III-V semiconductor blanket layer is patterned to form a second doped III-V semiconductor layer 618. For example, the above-described patterning process may include a lithography process, an etching process, other suitable processes, or a combination thereof. In some other embodiments, the second doped III-V semiconductor layer 618 can also be formed using in-situ doping.

Since the enhanced high hole mobility transistor 20' also includes a III-V semiconductor layer having a fin structure, it also has a large area of a two-dimensional hole cloud to improve device performance.

The foregoing summary of the various embodiments of the invention may be Those skilled in the art will understand that other processes and structures can be readily designed or modified based on the embodiments of the present invention to achieve the same objectives and/or to achieve the embodiments described herein. The same advantages. Those of ordinary skill in the art should also understand that such equivalent structures are not departing from the spirit and scope of the invention. Various changes, permutations, or modifications may be made to the embodiments of the invention without departing from the spirit and scope of the invention.

In addition, each claim of the disclosure may be an individual embodiment, and the scope of the disclosure includes each of the claims and each embodiment of the disclosure. The combination.

Claims (20)

A semiconductor device comprising: a substrate; a first III-V semiconductor layer disposed on the substrate, wherein the first III-V semiconductor layer comprises a fin structure, and the fin structure a top surface, a first sidewall, and a second sidewall opposite to the first sidewall; a second III-V semiconductor layer disposed on the first III-V semiconductor layer, wherein the first III The -V semiconductor layer and the second III-V semiconductor layer comprise a different material, and the second III-V semiconductor layer covers the top surface, the first sidewall, and the second sidewall of the fin structure Forming a heterojunction along the top surface of the fin structure, the first sidewall and the second sidewall; a gate electrode disposed on the second III-V semiconductor layer; and a A source/drain electrode is disposed on the second III-V semiconductor layer. The semiconductor device of claim 1, wherein the second III-V semiconductor layer is conformally disposed on the first III-V semiconductor layer. The semiconductor device of claim 1, further comprising: a first doped III-V semiconductor layer disposed between the second III-V semiconductor layer and the gate electrode. The semiconductor device of claim 3, wherein the first doped III-V semiconductor layer is conformally disposed on the second III-V semiconductor layer. The semiconductor device of claim 3, wherein the first doped III-V semiconductor layer comprises a P-doped III-V semiconductor. The semiconductor device of claim 5, wherein the first III-V semiconductor layer comprises GaN, the second III-V semiconductor layer comprises AlGaN, and the first doped III-V semiconductor layer comprises P-doped GaN. The semiconductor device of claim 5, wherein the first III-V semiconductor layer comprises AlGaN, the second III-V semiconductor layer comprises GaN, and the first doped III-V semiconductor layer comprises P-doped GaN. The semiconductor device of claim 3, further comprising: a second doped III-V semiconductor layer disposed between the first doped III-V semiconductor layer and the gate electrode. The semiconductor device of claim 8, wherein the first doped III-V semiconductor layer comprises a P-type doped III-V semiconductor, and the second doped III-V semiconductor layer comprises N Type doped III-V semiconductor. The semiconductor device of claim 9, wherein the first III-V semiconductor layer comprises AlGaN, the second III-V semiconductor layer comprises GaN, and the first doped III-V semiconductor layer comprises P-type doped GaN, the second doped III-V semiconductor layer includes N-doped GaN. A method of forming a semiconductor device, comprising: providing a substrate; forming a first III-V semiconductor layer on the substrate, wherein the first III-V semiconductor layer comprises a fin structure, and the fin structure comprises a top surface, a first sidewall and a second sidewall opposite to the first sidewall; forming a second III-V semiconductor layer on the first III-V semiconductor layer, wherein the first III-V semiconductor layer and The second III-V semiconductor layer includes a dissimilar material, and the second III-V semiconductor layer covers the top surface of the fin structure, the first sidewall, and the second sidewall to follow the fin The top surface of the sheet structure, the first sidewall and the second sidewall form a heterojunction; forming a gate electrode on the second III-V semiconductor layer; and forming a source/drain electrode Above the II-V semiconductor layer. The method of forming a semiconductor device according to claim 11, wherein the second III-V semiconductor layer is conformally formed on the first III-V semiconductor layer. The method for forming a semiconductor device according to claim 11, wherein after forming the second III-V semiconductor layer and before forming the gate electrode, further comprising: forming a first doped III-V group A semiconductor layer is over the second III-V semiconductor layer. The method of forming a semiconductor device according to claim 13, wherein the first doped III-V semiconductor layer is conformally formed on the second III-V semiconductor layer. The method of forming a semiconductor device according to claim 13, wherein the first doped III-V semiconductor layer comprises a P-doped III-V semiconductor. A method of forming a semiconductor device according to claim 15, wherein The first III-V semiconductor layer includes GaN, and the second III-V semiconductor layer includes AlGaN, and the first doped III-V semiconductor layer includes P-doped GaN. The method of forming a semiconductor device according to claim 15, wherein the first III-V semiconductor layer comprises AlGaN, and the second III-V semiconductor layer comprises GaN, the first doped III-V group The semiconductor layer includes P-type doped GaN. The method for forming a semiconductor device according to claim 13, wherein after forming the first doped III-V semiconductor layer and before forming the gate electrode, further comprising: forming a second doping III- A group V semiconductor layer is over the first doped III-V semiconductor layer. The method of forming a semiconductor device according to claim 18, wherein the first doped III-V semiconductor layer comprises a P-doped III-V semiconductor, and the second doped III-V semiconductor The layer includes an N-type doped III-V semiconductor. The method of forming a semiconductor device according to claim 19, wherein the first III-V semiconductor layer comprises AlGaN, the second III-V semiconductor layer comprises GaN, and the first doped III-V group The semiconductor layer includes P-type doped GaN, and the second doped III-V semiconductor layer includes N-type doped GaN.