TWI657453B - Memory system and operating method thereof - Google Patents

Abstract

A memory system includes a first flash memory, a second flash memory, and a controller. The first flash memory includes a memory array, and the memory array is divided into a plurality of pages. The controller is coupled to the first flash memory and the second flash memory, and configured to: control the second flash memory to record the specific one before programming the specific page in the first flash memory An address of the page; and after the particular page is programmed, controlling the second flash memory to record a programming state of the particular page.

Description

Memory system and its operation method

The present disclosure generally relates to a memory system and method of operation thereof.

Flash memory has been widely used in various electronic products. Flash memory is a non-volatile memory that retains data after a power outage. However, if the flash memory is suddenly interrupted during data operations (such as programming/erasing operations), it may therefore stay in an incomplete state.

The present disclosure relates to a memory system and method of operation thereof. The memory system includes a first flash memory and a second flash memory. When a page in the first flash memory is to be programmed, the address of the page, such as a physical address, will be recorded first in the second flash memory. In addition, after the page is programmed, the second flash memory also records the corresponding programming state of the page (eg, a programming end flag). Thereafter, by checking the information recorded in the second flash memory, it is possible to recognize, for example, an incomplete page due to a power interruption. An insufficient program handling procedure for handling incomplete pages can only detect incomplete pages Execute. Therefore, the performance, start-up time, and write amplification of the memory system can be improved.

In accordance with an embodiment of the present disclosure, a memory system is provided that includes a first flash memory, a second flash memory, and a controller. The first flash memory includes a memory array that is divided into a plurality of pages. The controller is coupled to the first flash memory and the second flash memory, and configured to: control the second flash memory to record the specific one before programming the specific page in the first flash memory An address of the page; and after the particular page is programmed, controlling the second flash memory to record a programming state of the particular page.

According to still another embodiment of the present disclosure, a method of operating a memory system is provided, wherein the memory system includes a first flash memory, a second flash memory, and a first flash memory and a second flash. The controller of the memory, the first flash memory includes a memory array, and the memory array is divided into a plurality of pages, the operation method includes: controlling a specific page in the first flash memory before programming Controlling the second flash memory to record an address of the particular page; and after the particular page is programmed, the controller controls the second flash memory to record a programmed state of the particular page.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

10‧‧‧ memory system

12‧‧‧Host device

102‧‧‧First flash memory

104‧‧‧Second flash memory

106‧‧‧ Controller

202‧‧‧Memory array

204‧‧‧ column decoder

206‧‧ ‧ buffer

208‧‧‧Control unit

210‧‧‧ line decoder

WL_1~WL_m‧‧‧ character line

BL_1~BL_n‧‧‧ bit line

302, 304, 402, 404, 406, 408, 410, 412, 414, 416, 418, 420, 502, 504, 506, 508, 510, 512 ‧ ‧ steps

P1~P10‧‧‧Page

EJB1~ADD5‧‧‧ physical address

Programming status of STA1~STA5‧‧‧ pages

FIG. 1 is a block diagram of a memory system in accordance with an embodiment of the present disclosure.

FIG. 2 is a block diagram of a first flash memory according to an embodiment of the present disclosure.

FIG. 3 is a flow chart showing a method of operating a memory system in accordance with an embodiment of the present disclosure.

FIG. 4 is a timing diagram of signal operation of the memory system according to an embodiment of the present disclosure.

FIG. 5 is a flow chart showing a power interruption recovery procedure of the memory system according to an embodiment of the present disclosure.

Figure 6 is a diagram showing the state of the page in the first flash memory and the related information recorded in the second flash memory.

FIG. 1 is a block diagram of a memory system 10 in accordance with an embodiment of the present disclosure.

The memory system 10 includes one or more first flash memories 102, one or more second flash memories 104, and a controller 106. For convenience of explanation, only one first flash memory 102 and one second flash memory 104 are exemplified herein.

The first flash memory 102 can be a NAND flash memory. The second flash memory 104 can be a reverse OR gate (NOR) flash memory. In some embodiments, the first flash memory 102 can be replaced with a phase change memory (PCM) or other page-program based non-volatile memory. The second flash memory 104 can be replaced by a magnetoresistive random access memory (MRAM) or any other non-volatile memory that can be byte-addressable.

The controller 106 is coupled to the first flash memory 102 and the second flash memory 104. Controller 106 can analyze and process the requirements and/or instructions from host device 12 and perform the various functions described in this disclosure.

Controller 106 can be implemented in hardware, software, or a combination thereof. For example, the controller 106 can be a microprocessor circuit, a microcontroller, a digital signal processing circuit (DSP) circuit, a programmable logic device (PLD), a state machine, an independent hardware circuit, or any Other suitable control logic is implemented.

FIG. 2 is a block diagram of a first flash memory 102 in accordance with an embodiment of the present disclosure. The first flash memory 102 includes a memory array 202, a column decoder 204, a page buffer 206, a control unit 208, and a row decoder 210.

Memory array 202 can include a plurality of memory cells. Depending on the electrical operation being performed, such memory cells may be grouped into memory blocks or pages. For example, memory cells in memory array 202 can be grouped into a plurality of pages as a basic unit for performing programming operations on NAND flash memory.

Column decoder 204 is coupled to memory array 202 via one or more word lines WL_1 WL WL_m. The column decoder 204 is controlled by the control unit 208, which can decode the address from the controller 106 and select and drive the word lines WL_1 WL WL_m according to the decoding result.

The page buffer 206 is coupled to the memory array 202 via one or more bit lines BL_1 BLBL_n. The write data from the controller 106 can be sequentially loaded into the page buffer 206 via the row decoder 210. The write data is first stored in the page buffer 206 prior to programming a particular page in the memory array 202.

Control unit 208 is coupled to column decoder 204 and row decoder 210. Control unit 208 can perform general memory operations, such as programming, reading, erasing, etc., on memory array 202 in response to control commands from controller 106. In an embodiment, the control unit 208 can be a device controller disposed in the first flash memory 102, which can be implemented in the form of hardware, software, or a combination thereof.

FIG. 3 is a flow chart showing a method of operating a memory system in accordance with an embodiment of the present disclosure. For convenience of explanation, the memory system herein is exemplified by the memory system 10 in Fig. 1.

At step 302, prior to programming a particular page in the first flash memory 102, the controller 106 controls the second flash memory 104 to record the address of the particular page, such as a physical address.

A particular page generally refers to a page in the first flash memory 102 that is selected to be written to the material. The programming operation is initiated by programming instructions provided by controller 106. When the first flash memory 102 receives a programming instruction from the controller 106, the write data is loaded into the page buffer 206. The first flash memory 102 then waits for further instructions from the controller 106 (e.g., a confirmation command). When the acknowledgment command is received, the first flash memory 102 programs the write data of the page buffer 206 into a particular page. At this point, the specific page will be programmed.

In accordance with an embodiment of the present disclosure, before a particular page is programmed, that is, the particular page has not been programmed, the controller 106 controls the second flash memory 104 to record the physical address of the particular page. Therefore, even if the power supply is suddenly interrupted during the programming of the specific page, the specific page whose programming is incomplete can be found from the material recorded by the second flash memory 104.

At step 304, after the particular page is programmed, the controller 106 controls the second flash memory 104 to record the programming state of the particular page.

For example, after the particular page is programmed, the controller 106 will perform a verify operation on the particular page. During the verify operation, a tight threshold voltage setting is used to determine if the particular page was programmed successfully. If the generated error bit count is lower than a predetermined value, the particular page is successfully programmed (ie, by a verify operation), at which time the controller 106 will control the second flash memory 104 to record the particular page. The programming state. Conversely, if the generated error bit count exceeds a predetermined value, the particular page system fails to be programmed and a failed status is reported to controller 106.

In the above manner, if the programming operation performed on a specific page is complete (for example, a power interruption event does not occur during a programming operation), the physical address and the programming state of the specific page are recorded in the second flash memory. In the body 104. On the other hand, if the programming operation performed on a specific page is incomplete, for example, the power supply is suddenly interrupted during the programming operation, the second flash memory 104 may only record the physical address of the specific page, but the physical address is not recorded. The programming state of a particular page. Because of the power interruption event, the programmed state of the particular page will not be recorded in the second flash memory 104. Therefore, if the physical address of a specific page has been recorded in the second flash memory, the controller 106 can check whether the specific page is confirmed by checking whether the programming state of the specific page appears in the second flash memory 104. Completely programmed. If the physical address and the programmed state of the particular page are recorded in the second flash memory 104, the particular page will be treated as a programmed full page that is not subject to a power interruption event; conversely, if the second flash memory There is a physical address for the particular page in 104 without the programming state of the particular page, which will be considered a programmed incomplete page that may be subject to a power interruption event.

In an embodiment, when the second flash memory 104 is set to be disabled (or not activated) by the controller 106, the controller 106 controls the first flash memory 102 to record the data of the second flash memory 104. Data retention information, such as a valve voltage distribution of memory cells in the second flash memory 104.

FIG. 4 is a timing diagram of signal operation of the memory system according to an embodiment of the present disclosure. For convenience of explanation, the memory system herein is exemplified by the memory system 10 in Fig. 1. In addition, the sequence including the states 404, 406, 410, 412, 414, and 416 of the upper half of the figure represents the operations performed on the first flash memory 102, and is depicted in the figure below. The sequence of the half containing states 402, 408, 418, and 420 represents the operations performed on the second flash memory 104.

In state 402, the erase operation of the second flash memory 140 is suspended.

Specifically, if the controller 106 wants to initiate a programming operation on a specific page in the first flash memory 102, the controller 106 first determines whether the second flash memory 104 is operating on a related information suitable for recording the specific page. status. If the result of the determination is no, for example, the second flash memory 104 is performing an erase operation, the controller 106 will suspend the erase operation. If the answer is yes, the controller 106 will transmit a programming command to the first flash memory 102 to initiate a programming operation, as indicated by state 404.

At state 404, controller 106 transmits a programming instruction to first flash memory 102 to request first flash memory 102 to program a particular page.

In an embodiment, when it is determined that the memory space of the second flash memory 104 is insufficient to record the physical address of the specific page and the programming state, the first flash memory is Before transmitting the programming command 102, the controller 106 will wait for the second flash memory 104 to complete the erase operation.

In state 406, when the first flash memory 102 receives a programming instruction from the controller 106, the write data for that particular page will be loaded into the page buffer 206 of the first flash memory 102.

Meanwhile, in state 408, the controller 106 will control the second flash memory 104 to record the physical address of the particular page, that is, the location in which the data is to be written into the first flash memory 102.

In state 410, after the second flash memory 104 has recorded the physical address of the particular page and the write data has been loaded into the page buffer 206, the controller 106 will transmit a confirmation command to the first flash memory 102. So that the first flash memory 102 programs the write data in the page buffer 206 to the particular page in the memory array 202.

Since the second flash memory 104 only needs to log in the physical address information in a few bytes during the state 408, the registration of the physical address message to the second flash memory 104 can be completed during the state 406. . In other words, upon completion of state 406, controller 106 can then send a confirmation command to first flash memory 102 without affecting the programming performance of first flash memory 102.

Next, in state 412, a particular page of memory array 202 in first flash memory 102 is programmed. The first flash memory 102, in response to the received acknowledgment command, programs the write data in the page buffer 206 into a particular page.

At state 414, controller 106 verifies the particular page that was programmed, and then retrieves the programmed state of the particular page at state 416. In an example, the programming state of the particular page can include an indicator that the particular page has been successfully programmed.

Next, at state 418, controller 106 controls second flash memory 104 to record the programmed state of the particular page that has been retrieved.

In the above manner, the second flash memory 104 will record the corresponding programming state of the particular page only after the programming of the particular page ends. For a specific page whose physical address has been recorded in the second flash memory 104, when the system power is turned on, the controller 106 can check whether the programming state of the specific page appears in the second flash memory. In the body 104, to determine whether the particular page is fully programmed. If the programming state of the particular page is present in the second flash memory 104, it indicates that the particular page is normally programmed. Conversely, if the second flash memory 104 only records the physical address of the particular page without recording the corresponding programming state, it indicates that the particular page is not fully programmed. For example, a power outage event occurs during the programming of that particular page.

In state 420, after the second flash memory 104 records the physical address of the particular page and the programming state, the controller 106 performs an erase operation on the second flash memory 104 to cause the second flash memory 104 to There is space to record the physical address of the page to be programmed and the programming state.

In general, for each page selected for programming in the first flash memory 102, the controller 106 will control the second flash memory 104 to record the physical address of the page before the page is programmed, and The page is programmed to record the programming state of the page.

FIG. 5 is a flow chart showing a power interruption recovery procedure of the memory system according to an embodiment of the present disclosure. For convenience of explanation, the memory system herein is exemplified by the memory system 10 in Fig. 1.

At step 502, after the power is turned on, the controller 106 searches for the last recorded physical address in the second flash memory 104 to find the last programmed page in the first flash memory 102.

At step 504, the controller 106 checks if the corresponding programmed state of the last programmed page has been recorded in the second flash memory 104. If not, the program proceeds to step 506. If so, the program proceeds to step 510.

At step 506, when it is determined that the corresponding programmed state of the last programmed page is not recorded in the second flash memory 104, the controller 10 recognizes the last programmed page as a programmed incomplete page, which is, for example, due to a power supply. Caused by an interruption. Next at step 508, the controller 106 performs a programming incomplete processing procedure on the programmed incomplete page for power interruption recovery.

In one embodiment, during programming of the incomplete processing program, the controller 106 first determines whether the programming incomplete page is an error correction code (ECC) pass page or a blank page.

The ECC described herein refers to the page of the ECC verification operation through the page. If the incomplete page is judged to be the ECC pass page, indicating that the power interrupt event may occur at the end or the second half of the programming operation, the data in the incomplete page can still be verified by ECC. On the other hand, if the programming incomplete page is judged to be a blank page, it indicates that the power interruption event may have occurred at the beginning or the first half of the programming operation.

When the programming incomplete page is recognized as an ECC pass page, the controller 106 will perform a backup operation to maintain the material in the page. For example, after determining that the data in the incomplete page is verified by ECC (ie, the programming incomplete page is recognized as an ECC pass page), the controller 106 will establish programming at the new location of the first flash memory 102. A copy of the data for an incomplete page.

On the other hand, after it is judged that the program incomplete page is a blank page in the first flash memory 102, the controller 106 will fill the incomplete page with the dummy data to avoid the incomplete page being programmed. use. This is because the state of the programmed incomplete page that is recognized as a blank page may deviate from the normal erased state due to incomplete programming. Once such a blank page is written to the data via subsequent programming operations, it is likely that an error message will be generated.

In one embodiment, in addition to programming incomplete pages, blank pages that may be subsequently programmed and affected by a power interruption event are also populated with blank data by controller 106.

At step 510, after determining that the programming state corresponding to the last programmed page has been recorded in the second flash memory 104, the controller 106 will recognize the last programmed page as a programmed full page. Since it is not necessary to execute a program under-program for programming a full page, the program can proceed directly to step 512.

At step 512, the controller 106 reconstructs a logical address-to-physical address mapping relationship for the first flash memory 102. For example, the controller 106 saves the mapping of logical addresses to physical addresses in the form of a mapping table. The controller 106 can utilize this mapping table to translate the logical address provided by the host device 12 into the physical address of the first flash memory 102.

FIG. 6 illustrates the state of the page in the first flash memory 102 and the related information recorded in the second flash memory 104.

For ease of understanding, only the first flash memory 102 includes ten pages P1 to P10 as an example. In this example, it is assumed that pages P1 to P10 in the first flash memory 102 are sequentially programmed.

The controller 106 can read the first flash memory 102 and detect that the pages P6~P10 are blank pages (indicated by a rectangle having a diagonal network bottom in the figure), and determine the first blank page based on the programming order. The page P5 before P6 is the last page programmed in the first flash memory 102. The last page programmed can be a programmed full page or a programmed incomplete page that is subject to a power interruption event.

As previously mentioned, a page that has been recorded in the second flash memory 104 for a physical address is a programmed full page if its corresponding programmed state exists in the second flash memory 104. The opposite is a programming incomplete page. As shown in FIG. 6, the physical addresses ADD1 to ADD4 of the pages P1 to P4 and the program states STA1 to STA4 are recorded in the second flash memory 104, respectively. Therefore, pages P1~P4 will be treated as programmed full pages.

For the last programmed page, P5, its physical address ADD5 is finally recorded in the second flash memory 104. The controller 106 can check if the corresponding programming state of the page P5 is recorded in the second flash memory 104. If so, page P5 is a programmed full page; if not, page P5 is a programmed incomplete page in first flash memory 102 that needs to be restored, for example, via the programming incomplete handler described in FIG. .

Based on the above, the memory system proposed by the present disclosure includes a first flash memory and a second flash memory. When a page in the first flash memory is to be programmed, the page The physical location will be recorded first in the second flash memory. In addition, after the page is programmed, the second flash memory also records the corresponding programming state of the page (eg, a programming end flag). Thereafter, by checking the information recorded in the second flash memory, it is possible to recognize, for example, an incomplete page due to a power interruption. An incomplete programming handler that handles programming incomplete pages can only be executed when a programming incomplete page is detected. Therefore, the performance, start-up time, and write amplification of the memory system can be improved.

The description includes many specifics, and should not be construed as limiting the scope of the claimed embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can be implemented in the various embodiments or in any suitable subcombination. Moreover, while the above features are described as working in some combination even initially stated as such, one or more of the required combinations may be removed from the combination in some cases, and the required combination may involve A variation of a combination or sub-combination. Similarly, although the operations are depicted in a particular order in the figures, this should not be construed as requiring that such operations be performed in the particular order or sequence of the order shown, or that all illustrated operations are required to achieve the desired results. Executed.

Only some illustrations and implementations have been disclosed. Variations, modifications, and enhancements of the described examples and implementations, as well as other implementations, can be made based on the disclosure.

Claims (15)

A memory system, comprising: a first flash memory, comprising a memory array, the memory array is divided into a plurality of pages; a second flash memory; and a controller coupled to the first flash The memory and the second flash memory, and configured to: control the second flash memory to record an address of the specific page before programming the specific page in the first flash memory; After the specific page is programmed, the second flash memory is controlled to record a programming state of the specific page; wherein the first flash memory and the second flash memory are respectively two physical memories. The memory system of claim 1, wherein the first flash memory further comprises: a page buffer coupled to the memory array for storing a write data for the specific page; The controller is further configured to control the second flash memory before transmitting the confirmation command to the first flash memory to enable the first flash memory to program the write data of the page buffer to the specific page. The flash memory records the address of the particular page. The memory system of claim 1, wherein the controller is further configured to: Suspending an erasing operation performed by the second flash memory before transmitting a programming command to the first flash memory. The memory system of claim 1, wherein the controller is further configured to: when determining that a memory space of the second flash memory is insufficient to store the address of the specific page and the programming state Waiting for the second flash memory to complete an erase operation before transmitting a programming command to the first flash memory. The memory system of claim 1, wherein the controller is further configured to: find a last programmed page in the first flash memory; and check a corresponding programming state of the last programmed page. Whether it has been recorded in the second flash memory; when it is determined that the corresponding programming state of the last programmed page is not recorded in the second flash memory, the last programmed page is recognized as a programming not A full page; and a programming incomplete handler for the incomplete page of programming. The memory system of claim 5, wherein the programming incomplete processing program comprises: when determining that the programming incomplete page passes an error correction verification operation, the controller is in the first flash memory The new location establishes a copy of the data for the programming incomplete page. The memory system of claim 5, wherein the programming incomplete processing program comprises: When it is determined that the programming incomplete page is a blank page in the first flash memory, the controller fills in a blank data for the incomplete programming page. A method of operating a memory system, wherein the memory system includes a first flash memory, a second flash memory, and a control coupled to the first flash memory and the second flash memory The first flash memory includes a memory array, the memory array is divided into a plurality of pages, and the first flash memory and the second flash memory are respectively two physical memories, and the operation is performed. The method includes, prior to programming a particular page in the first flash memory, the controller controlling the second flash memory to record an address of the particular page; and after the particular page is programmed, The controller controls the second flash memory to record a programming state of the particular page. The method of claim 8, wherein the first flash memory further comprises a page buffer coupled to the memory array and configured to store a write for the particular page. And the operating method further includes: before transmitting the confirmation command to the first flash memory to enable the first flash memory to program the write data of the page buffer to the specific page, the controller Controlling the second flash memory to record the address of the particular page. The operating method of claim 8, further comprising: suspending an erasing operation performed by the second flash memory before transmitting the programming command to the first flash memory. The operating method of claim 8, further comprising: when determining that a memory space of the second flash memory is insufficient to store the address of the specific page and the programming state, the controller is in the pair The first flash memory waits for the second flash memory to complete an erase operation before transmitting a programming command. The operating method of claim 8, further comprising: after the second flash memory records the address of the specific page and the programming state, the controller performs the second flash memory A wipe out operation. The operating method of claim 8, further comprising: the controller searching for a last programmed page in the first flash memory; the controller checking a corresponding programming state of the last programmed page Whether it has been recorded in the second flash memory; when it is determined that the corresponding programming state of the last programmed page is not recorded in the second flash memory, the controller identifies the last programmed page Programming a incomplete page; and the controller performs a programming incomplete handler for the incomplete page. The operating method of claim 13, wherein the programming incomplete processing program comprises: when determining that the programming incomplete page passes an error correction verification operation, the controller is new in the first flash memory The location establishes a copy of the data for the programming incomplete page. The operating method of claim 13, wherein the programming incomplete processing program comprises: after determining that the programming incomplete page is a blank page in the first flash memory, the controller Programming incomplete pages fill in a blank data.