TWI633558B - Operating method of resistive memory storage apparatus - Google Patents

Abstract

A method of operating a resistive memory device, comprising: performing a heating step on a resistive memory device; and performing a setting and resetting cycle operation on the resistive memory device after the heating step to increase reading of the resistive memory component Take the boundary; and determine whether the resistive memory component is verified by reading the boundary.

Description

Method of operating a resistive memory element

The present invention relates to a method of operating a memory device, and more particularly to a method of operating a resistive memory device.

In recent years, resistive memory (such as Resistive Random Access Memory (RRAM)) has developed extremely rapidly and is currently the most attractive structure of future memory. Resistive memory is a low-power, high-speed operation, high-density, and compatible with complementary metal oxide semiconductor process technology, making it ideal for the next generation of non-volatile memory components.

Current resistive memories typically include opposing upper and lower electrodes and a dielectric layer between the upper and lower electrodes. Before the current resistive memory can be repeatedly switched between high and low resistance states to memorize data, the process of channel formation is first required. The process of forming includes applying a bias voltage to the resistive memory, such as a positive bias, to cause current to flow from the upper electrode to the lower electrode, such that oxygen vacancy and oxygen ion are formed in the dielectric layer. The current path changes the resistive memory from a high resistance state (HRS) to a low resistance state (LRS) to form a conductive filament. Generally, in the formed filament, the diameter of the portion adjacent to the upper electrode may be smaller than the diameter of the portion adjacent to the lower electrode. After that, the resistive memory can be reset or set, so that the resistive memory is switched to the high-resistance state and the low-resistance state, respectively, to complete the memory of the data. In addition, when the current resistive memory is reset, a reverse bias having a polarity opposite to that set at the resistive memory is applied to cause current to flow from the lower electrode to the upper electrode. At this time, the oxygen vacancy adjacent to the upper electrode combines with a portion of the oxygen ions to interrupt the current path, causing the filament to be disconnected adjacent to the upper electrode. When the current resistive memory is set, a bias having the same polarity as that of the filament forming process can be applied to the resistive memory to cause current to flow from the upper electrode to the lower electrode. At this time, oxygen ions adjacent to the upper electrode are detached, and oxygen vacancies are newly formed, so that the filament is reformed adjacent to the upper electrode.

However, in the prior art, if the resistive memory is subjected to a heating step, the read boundary is usually lowered, and the logic state of the resistive memory cannot be correctly judged. Therefore, how to increase the read boundary of resistive memory is one of the important topics at present.

The present invention provides a method of operating a resistive memory device that increases the read boundary of a resistive memory device.

The method of operating a resistive memory device of the present invention includes: performing a heating step on the resistive memory device; performing a set and reset cycle operation on the resistive memory device to increase a read boundary of the resistive memory device; Determine if the resistive memory component is verified by reading the boundary. The set and reset cycle operations are performed after the heating step.

In one embodiment, after the step of performing a set and reset cycle operation on the resistive memory element, the method of operating the resistive memory element further comprises: if the resistive memory element is verified by reading the boundary, ending Setting and resetting the loop operation; and repeating the steps of performing the set and reset loop operations on the resistive memory element until the resistive memory element does not pass the read boundary verification, or until the resistive memory element is verified by the read boundary, or Until a preset number of times.

In an embodiment, the method of operating the resistive memory device further includes performing a forming process and an initial resetting process on the resistive memory device. The forming process includes a heating step. The set and reset loop operations are executed after the formation procedure and the initial reset procedure are completed.

In one embodiment, the method of operating the resistive memory device further includes mounting a resistive memory device on the circuit board. The installation step includes a heating step. Set and reset loop operations to program and erase resistive memory components.

The method for operating a resistive memory device of the present invention comprises: performing a refresh operation on the resistive memory device; and determining whether to perform a stylization and erasing cycle on the resistive memory device according to whether the resistive memory device is subjected to a heating step. Operation to increase the read boundary of the resistive memory element; and to determine if the resistive memory element is verified by read boundary. Stylized and erase loop operations are performed after the refresh operation.

In one embodiment, the method for operating the resistive memory device further includes: determining whether the resistive memory device has undergone a heating step; and if the resistive memory device is subjected to the heating step, after the refreshing operation, the resistive memory The component performs stylization and erase cycle operations; and if the resistive memory component is not subjected to a heating step, the method of operating the resistive memory component is terminated.

In one embodiment, the resistive memory device described above includes a first array of unit cells and a second array of unit cells. The method of operating the resistive memory device further includes applying a weak set voltage to the first unit cell array to cause the plurality of memory cells of the first unit cell array to transition from the first resistive state to the second resistive state. The voltage value of the weak set voltage is lower than the voltage value of the normal set voltage. The step of determining whether the resistive memory element has undergone the heating step comprises: determining whether the number of the memory cells in the first unit cell array transitioning from the second resistive state to the first resistive state is greater than a critical value; if the memory unit cell is from The second resistance state is changed to a state in which the first resistance state is greater than a threshold value, determining that the resistive memory device is subjected to the heating step; and if the number of the memory cell transitioning from the second resistance state to the first resistance state is less than or equal to a threshold value It is judged that the resistive memory element has not undergone a heating step.

In an embodiment, after the step of performing the staging and erasing loop operations on the resistive memory device, the operating method of the resistive memory device further comprises: if the resistive memory component is verified by reading the boundary, End stylization and erase loop operations; and if the resistive memory component does not pass the read boundary verification, repeat the steps of stylizing and erasing the loop operation of the resistive memory component until the resistive memory component passes the read boundary Verify, or until a preset number of times.

In an embodiment, the method of operating the resistive memory device further includes performing a power-on operation on the resistive memory device. The step of judging whether or not the resistive memory element has undergone the heating step is performed after the end of the power-on operation.

In an embodiment, the refresh operation is performed after the power up operation ends.

Based on the above, in the operating method of the present invention, after the resistive memory element is subjected to the heating step, the setting and resetting cycle operations or the stylization and erasing cycle operation steps are performed to increase the read boundary of the resistive memory device. .

The above described features and advantages of the invention will be apparent from the following description.

The invention is illustrated by the following examples, but the invention is not limited to the illustrated embodiments. Further combinations are also allowed between the embodiments. The term "coupled" as used throughout the specification (including the scope of the claims) may be used in any direct or indirect connection. For example, if the first device is described as being coupled to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be connected through other devices or some kind of connection means. Connected to the second device indirectly. In addition, the term "signal" may mean at least one current, voltage, charge, temperature, data, electromagnetic wave or any other one or more signals.

FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the invention. 2 is a schematic diagram showing a filament formation process, a reset operation, and a setting operation in a memory cell according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2 , the memory storage device 100 of the embodiment includes a memory control circuit 110 and a resistive memory component 120 . The resistive memory component 120 is coupled to the memory control circuit 110. The resistive memory element 120 includes a plurality of memory cells 122 arranged in an array. In the present embodiment, the memory cell 122 includes an upper electrode 210, a lower electrode 220, and a dielectric layer 230. The upper electrode 210 and the lower electrode 220 are good metal conductors, and the materials of the two may be the same or different. The dielectric layer 230 is disposed between the upper electrode 210 and the lower electrode 220. Dielectric layer 230 includes a dielectric material, including, for example, a transition metal oxide. The memory cell 122 has at least two resistance states. By applying different voltages to the upper electrode 210 and the lower electrode 220 respectively, the resistance state of the memory cell 122 is changed, and the memory cell 122 can provide data storage. Features.

In the present embodiment, the memory cell 122 has, for example, a transistor-resistor (1T1R) structure or a two-diode two-resistor (2T2R) structure, and its implementation can be sufficiently obtained by the general knowledge in the art. Instructions, suggestions and implementation instructions. The present invention does not limit the structure of the memory cell 122.

In this embodiment, the memory control circuit 110 is configured to form a memory cell 122. During this process, the electrodes at both ends of the memory cell 122 are continuously applied with a bias voltage V1 (i.e., a voltage is formed) to generate an applied electric field to the dielectric layer 230. In the present embodiment, a positive voltage having a value of V1 volt is applied to the upper electrode 210, and a voltage of 0 volt is applied to the lower electrode 220. In addition, the addition of an electric field separates the oxygen atoms 222 into oxygen ions 212 and oxygen vacancies 232. The oxygen vacancy 232 forms a filament in the dielectric layer 230 as a current transfer path. When the applied electric field exceeds the critical value, the dielectric layer 230 will undergo a dielectric collapse phenomenon, thereby transitioning from a high resistance state to a low resistance state. This type of collapse is not permanent and its resistance can still change.

The memory cell 122 that forms the program has a low resistance state. At the time of the reset operation, the upper electrode 210 of the memory cell 122 is applied with a voltage of 0 volts, and the lower electrode 220 is applied with a positive voltage of a value of V2 volts. This voltage difference is a reset voltage, such as -V2 volts. The reset cell memory cell 122 changes its state from a low resistance state to a high resistance state. Next, at the time of the setting operation, the upper electrode 210 of the memory cell 122 is applied with a positive voltage of V3 volts, and the lower electrode 220 is applied with a voltage of 0 volts. This voltage difference is a set voltage, such as +V3 volts. The memory cell 122 of the set operation changes its state from a high resistance state to a low resistance state. In the present embodiment, the magnitude and polarity of the reset voltage and the set voltage are for illustrative purposes only, and are not intended to limit the present invention. In the present embodiment, the forming procedure, the resetting operation, and the setting operation illustrated in FIG. 2 are for illustrative purposes only, and are not intended to limit the present invention.

FIG. 3 illustrates a method of operating a resistive memory device in accordance with an embodiment of the present invention. Referring to FIG. 1 to FIG. 3, in step S100, the memory control circuit 110 of the present embodiment performs a forming process and an initial resetting process on the resistive memory device 120. Thereafter, in step S110, the memory control circuit 110 performs a set and reset cycle operation on the resistive memory device 120 to increase the read boundary of the resistive memory device 120. That is, the read boundary of the resistive memory element 120 after the step S110 is performed is larger than the read boundary of the resistive memory element 120 in which the step S110 is not performed. In step S120, the memory control circuit 110 determines whether the resistive memory element 120 has passed the read boundary verification. The reading boundary verification includes setting a first current threshold and a second current threshold that is less than the first current threshold, and comparing the current flowing through the resistive memory element 120 with the first current threshold and the second current threshold. When the current of the resistive memory element 120 is greater than the first current threshold or less than the second current threshold, it is determined that the resistive memory element 120 is verified by reading the boundary. When the current of the resistive memory element 120 is between the first current threshold and the second current threshold, it is determined that the resistive memory element 120 has not passed the read boundary verification.

If the resistive memory element 120 does not pass the read boundary verification, the memory control circuit 110 performs step S110 again to repeat the steps of performing the set and reset cycle operations on the resistive memory element 120 until the resistive memory element 120 Verify by reading the boundary. In an embodiment, the memory control circuit 110 can also be set a preset number of times to repeatedly perform the step S110 on the resistive memory element 120 until the preset number of times is reached. On the other hand, if the resistive memory element 120 is verified by the read boundary, the memory control circuit 110 ends the setting of the step S110 and the reset loop operation.

In the present embodiment, the set and reset cycle operations include at least one set operation and at least one reset operation, and embodiments thereof may be sufficiently taught, suggested, and implemented by the general knowledge in the art.

4 illustrates a method of operating a resistive memory device in accordance with another embodiment of the present invention. Referring to FIG. 1, FIG. 2 and FIG. 4, in step S200, the memory control circuit 110 of the present embodiment performs a heating step on the resistive memory device 120. In step S210, the memory control circuit 110 performs a set and reset cycle operation on the resistive memory element 120 to increase the read boundary of the resistive memory element 120. That is, the read boundary of the resistive memory element 120 after the step S210 is performed is larger than the read boundary of the resistive memory element 120 in which the step S210 is not performed. In this embodiment, the setting and resetting cycle operation includes at least one reset operation and at least one setting operation, and the implementation manner thereof can obtain sufficient teaching, suggestion and implementation by the general knowledge in the technical field or the content disclosed in FIG. Description. In the present embodiment, the setting and reset cycle operation of step S210 is performed after the heating step of step S200.

In step S220, the memory control circuit 110 determines whether the resistive memory element 120 has passed the read boundary verification. If the resistive memory element 120 does not pass the read boundary verification, the memory control circuit 110 performs step S210 again to repeatedly perform the setting and reset cycle operations on the resistive memory element 120 until the resistive memory element 120 passes the read. Take the boundary verification. In an embodiment, the memory control circuit 110 can also be set to a preset number of times to repeatedly perform the step S210 on the resistive memory element 120 until the preset number of times is reached. On the other hand, if the resistive memory element 120 is verified by the read boundary, the memory control circuit 110 ends the setting of the step S210 and the reset cycle operation operation.

In an embodiment, the heating step of step S200 may be generated when the memory control circuit 110 performs a forming process on the resistive memory element 120. Alternatively, in an embodiment, the heating step of step S200 may occur when the resistive memory element 120 is mounted on a circuit board. In this embodiment, the mounting step includes a heating step, and the set and reset cycle operations are used to program and erase the resistive memory element 120.

FIG. 5 illustrates a method of operating a resistive memory device in accordance with another embodiment of the present invention. Referring to FIG. 1, FIG. 2 and FIG. 5, in step S300, the memory control circuit 110 of the present embodiment performs a refresh operation on the resistive memory device 120. In step S310, the memory control circuit 110 determines whether to perform a stylization and erase cycle operation on the resistive memory device 120 according to whether the resistive memory device 120 has undergone a heating step to increase the resistive memory device 120. Read boundary. That is, the read boundary of the resistive memory element 120 after the execution of the stylization and erase cycle operations is large compared to the read boundary of the resistive memory element 120 in which the stylization and erase cycle operations are not performed. In the present embodiment, the implementation of the stylization and erase cycle operations and the refresh operation can be sufficiently taught, suggested, and implemented by the general knowledge in the art.

In one embodiment, the resistive memory component 120 of FIG. 2 includes, for example, a temperature sensor for detecting temperature, and when the memory control circuit 110 determines that the measured temperature is greater than a predetermined value, determining the resistive The memory element 120 is subjected to a heating step.

In one embodiment, the resistive memory component 120 of FIG. 2 includes, for example, different arrays of cell cells for detecting temperature and storing data, respectively. For example, the resistive memory component 120 includes, for example, a first array of cell cells for detecting temperature, and a second array of cell cells for storing data. In an embodiment, the number of unit cells of the first unit cell array is smaller than the unit cell of the second unit cell array.

FIG. 6 illustrates a method of operating a resistive memory device in accordance with another embodiment of the present invention. In this embodiment, the resistive memory device 120 further includes a first cell array for detecting temperature and a second cell array for storing data. Referring to FIG. 1 , FIG. 2 and FIG. 6 , in step S400 , the memory control circuit 110 of the embodiment applies a weak set voltage to the first unit cell array to make a plurality of memories of the first unit cell array. The bulk cell transitions from a first resistive state (eg, a high resistance state) to a second resistive state (eg, a low resistance state). Next, a power up operation is performed on the resistive memory element 120. In the present embodiment, the voltage value of the weak set voltage is less than the voltage value of the normal set voltage, for example, less than the voltage value V3 of FIG. The data written according to the weak set voltage is susceptible to high temperature effects and bit reversal occurs, for example, from a second resistive state (eg, a low resistance state) to a first resistive state (eg, a high resistance state). Next, in step S410, the memory control circuit 110 determines whether the resistive memory element 120 has undergone a heating step. If the resistive memory element 120 has not undergone a heating step, the memory control circuit 110 ends the method of operating the resistive memory element 120.

If it is determined that the resistive memory element 120 has undergone the heating step, the memory control circuit 110 performs a refresh operation on the resistive memory element 120 (step S420). Next, in step S430, the memory control circuit 110 performs a program and erase cycle operation on the resistive memory device 120 to increase the read boundary of the resistive memory device 120.

In step S440, the memory control circuit 110 of the present embodiment determines whether the resistive memory element 120 has passed the read boundary verification. If the resistive memory element 120 does not pass the read boundary verification, the memory control circuit 110 performs step S430 again to repeatedly perform the stylization and erase cycle operations on the resistive memory element 120 until the resistive memory element 120 passes. Read boundary verification. In an embodiment, the memory control circuit 110 can also be set a predetermined number of times to repeatedly perform the step S430 on the resistive memory device 120 until the preset number of times is reached. On the other hand, if the resistive memory element 120 is verified by the read boundary, the memory control circuit 110 performs step S450.

In step S450, the memory control circuit 110 of the present embodiment applies a weak set voltage to the first cell array again, so that the plurality of memory cells of the first cell array are from the first resistance state (for example, a high resistance state). Transitioning to a second resistance state (eg, a low resistance state) causes the first cell array to again have a temperature sensing function. Next, the memory control circuit 110 ends the method of operating the resistive memory element 120.

FIG. 7 is a flow chart showing a method of determining whether a resistive memory device has undergone a heating step according to an embodiment of the invention. Referring to FIG. 6 and FIG. 7, in the embodiment, step S410 includes steps S412, S414, and S416, for example. In step S412, the memory control circuit 110 determines whether the number of memory cells in the first unit cell array transitions from the second resistance state to the first resistance state is greater than a threshold value. If the number of changes of the memory cell from the second resistance state to the first resistance state is greater than the threshold value, in step S414, the memory control circuit 110 determines that the resistive memory device 120 has undergone the heating step. If the number of changes of the memory cell from the second resistance state to the first resistance state is less than or equal to the threshold value, in step S416, the memory control circuit 110 determines that the resistive memory device 120 has not undergone the heating step.

In summary, in the exemplary embodiment of the present invention, after the resistive memory element is subjected to the heating step, the operation method includes setting and resetting the cyclic operation or the stylization and erasing cycle operation steps to increase the resistive memory. The read boundary of the body element. In an exemplary embodiment, the resistive memory component has a temperature detecting function, and the memory control circuit can determine whether to perform stylization and erase cycle operations on the resistive memory component to increase the resistance memory component. Read the boundary.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ memory storage device

110‧‧‧Memory Control Circuit

120‧‧‧Resistive memory components

122‧‧‧ memory cell

210‧‧‧Upper electrode

212‧‧‧Oxygen ions

220‧‧‧ lower electrode

222‧‧‧Oxygen atom

230‧‧‧ dielectric layer

232‧‧‧Oxygen vacancies

V1‧‧‧ forming voltage

V2‧‧‧Reset voltage

V3‧‧‧Set voltage

HRS‧‧‧high resistance state

LRS‧‧‧Low resistance state

S100, S110, S120, S200, S210, S220, S300, S310, S400, S410, S412, S414, S416, S420, S430, S440, S450‧‧‧ method steps

FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the invention. 2 is a schematic diagram showing a filament formation process, a reset operation, and a setting operation in a memory cell according to an embodiment of the invention. FIG. 3 illustrates a method of operating a resistive memory device in accordance with an embodiment of the present invention. 4 illustrates a method of operating a resistive memory device in accordance with another embodiment of the present invention. FIG. 5 illustrates a method of operating a resistive memory device in accordance with another embodiment of the present invention. FIG. 6 illustrates a method of operating a resistive memory device in accordance with another embodiment of the present invention. FIG. 7 is a flow chart showing a method of determining whether a resistive memory device has undergone a heating step according to an embodiment of the invention.

Claims (9)

A method of operating a resistive memory device, comprising: performing a heating step on the resistive memory device, wherein after the heating step, a read boundary of the resistive memory device is reduced; The body element performs a set and reset cycle operation to increase the reduced read boundary of the resistive memory element; and determine whether the resistive memory element is verified by a read boundary, wherein the setting and resetting The cycle operation is performed after this heating step. The method of operating a resistive memory device according to claim 1, wherein the method of operating the resistive memory device is performed after the step of performing the setting and resetting cycle operation on the resistive memory device. The method includes: if the resistive memory component is verified by the read boundary, ending the setting and resetting cycle operation; and if the resistive memory component does not pass the read boundary verification, repeating execution of the resistive memory component The step of setting and resetting the loop operation until the resistive memory element is verified by the read boundary, or up to a predetermined number of times. The method for operating a resistive memory device according to claim 1, further comprising: mounting the resistive memory component on a circuit board, wherein the mounting step comprises the heating step, wherein the setting and resetting The loop operation is used to program and erase the resistive memory component. A method for operating a resistive memory device, comprising: performing a refresh operation on the resistive memory device; determining whether to execute a program on the resistive memory device according to whether the resistive memory device has undergone a heating step And erasing a loop operation to increase a read boundary of the resistive memory element, wherein the read boundary of the resistive memory element is lowered after the heating step; and determining the resistive memory element Whether to perform a read boundary verification, wherein the stylization and erase loop operations are performed after the refresh operation. The method for operating a resistive memory device according to claim 4, further comprising: determining whether the resistive memory device has undergone the heating step; if the resistive memory device passes the heating step, the refreshing After the operation, the staging and erasing cycle operations are performed on the resistive memory device; and if the resistive memory device does not undergo the heating step, the method of operating the resistive memory device is terminated. The method of operating a resistive memory device according to claim 5, wherein the resistive memory device comprises a first cell array and a second cell array, and the resistive memory device operates The method further includes: applying a weak set voltage to the first unit cell array to cause the plurality of memory cells of the first unit cell array to transition from a first resistance state to a second resistance state, wherein the weak setting The voltage value of the voltage is less than the voltage value of a normal set voltage. The step of determining whether the resistive memory element has undergone the heating step comprises: determining whether the number of the memory cells in the first unit cell array changes from the second resistance state to the first resistance state is greater than one a threshold value; if the number of the memory cells from the second resistance state to the first resistance state is greater than the threshold value, determining that the resistive memory device passes the heating step; and if the memory cells are The number of transitions from the second resistance state to the first resistance state is less than or equal to the threshold value, and it is determined that the resistive memory element has not undergone the heating step. The method of operating a resistive memory device according to claim 5, after the step of performing the stylization and erase cycle operations on the resistive memory device, the method of operating the resistive memory device The method further includes: if the resistive memory component is verified by the read boundary, ending the stylization and erase cycle operation; and repeating the resistive memory if the resistive memory component does not pass the read boundary verification The component performs the step of stylizing and erasing the loop operation until the resistive memory component is verified by the read boundary, or up to a predetermined number of times. The method for operating a resistive memory device according to claim 5, further comprising: A power-on operation is performed on the resistive memory element, wherein the step of determining whether the resistive memory element has passed the heating step is performed after the power-on operation ends. The method of operating a resistive memory device according to claim 8 wherein the refresh operation is performed after the end of the power-on operation.