TWI628531B - Clock control circuit and controller - Google Patents

Abstract

A clock control circuit includes: a clock generation unit that receives a control signal, and when the control signal has a high logic level, the clock generation unit starts and generates a clock signal; and a controller includes a digit Unit and a clock control unit. The digital unit receives the clock signal and is configured to generate a first digit signal, a second digit signal, and a third digit signal. When receiving the clock signal, the digit unit operates in an initialization state and a One of the initialization completion states, and when the initialization state operated by the digital unit ends, the first and second digit signals each have the high logic level, and the clock control unit receives a reset signal And the first to third digit signals, and the control signal is generated accordingly.

Description

Clock control circuit and controller

The invention relates to a control circuit and a controller, in particular to a clock control circuit and a controller.

A conventional mixed-signal integrated circuit includes a digital unit and an analog unit. The digital unit needs to receive a clock signal generated by a crystal oscillator in the analog unit to perform initialization and related digital operations. The crystal oscillator can be controlled by a control signal from the digital unit (or can be preset to be in a simultaneous state) and generate the clock signal to the digital unit.

In the prior art, in order to enable the digital unit to enter the initialization state in a reset phase (that is, when the conventional mixed signal integrated circuit receives a power signal), the method (1) can be utilized: The unit presets to turn on and output the control signal with a high logic level (corresponding to the crystal oscillator starting), and a processor executes a software to determine whether the initialization and related digital work required by the digital unit is performed. After the execution is completed, and after the execution is completed, the control signal is converted from the high logic level to a low logic level (corresponding to the crystal oscillator not starting); or, by using the method (2): the crystal oscillator is not subject to the digit The unit is controlled and preset to remain in the starting state. However, the prior method (1) reduces the simplicity of the conventional mixed signal integrated circuit application, and the method (2) causes the conventional mixed signal integrated circuit to have higher power consumption.

Accordingly, it is an object of the present invention to provide a clock control circuit that overcomes the shortcomings of the prior art.

Thus, the clock control circuit of the present invention includes a clock generation unit and a controller.

The clock generation unit receives a control signal, and when the control signal has a high logic level, the clock generation unit can start and generate a clock signal in response to the received control signal.

The controller includes a digital unit and a clock control unit.

The digital unit is electrically connected to the clock generating unit to receive the clock signal, and is configured to generate a first digit signal indicating whether the initialization of the digit unit is completed, and a second digit indicating whether the digitizing operation of the digit unit is completed. a signal and a third digit signal, when the clock signal is received, the digit unit operates in one of an initialization state and an initialization state, and when the initialization state operated by the digit unit ends, The first and second digit signals each have the high logic level.

The clock control unit is electrically connected to the clock generating unit and the digital unit, and receives a reset signal and the first to third digit signals from the digital unit, and according to the reset signal and the first The third digit signal generates the control signal and outputs the control signal to the clock generation unit.

Another object of the present invention is to provide a controller that overcomes the shortcomings of the prior art.

The controller is adapted to generate a control signal to control a clock generating unit. When the control signal has a high logic level, the clock generating unit is controlled to start and generate a clock signal, and the controller includes a digital bit. Unit and a clock control unit.

The digital unit is configured to receive the clock signal, and is configured to generate a first digital signal indicating whether initialization of the digital unit is completed, a second digital signal indicating whether digital operation of the digital unit is completed, and a third digit a signal, when the clock signal is received, the digit unit operates in one of an initialization state and an initialization state, and when the initialization state operated by the digit unit ends, the first and the first The two digit signals each have the high logic level.

The clock control unit is electrically connected to the digital unit, receives a reset signal and the first to third digital signals from the digital unit, and generates the first and third digital signals according to the reset signal and the first to third digital signals. The control signal is output to the clock generation unit.

The effect of the present invention is that the clock control unit can automatically start the clock generation unit and generate the clock signal to the digital unit for initialization, so that the clock control circuit of the embodiment does not need to be known. The crystal oscillator is preset to be in the starting state or the digital unit is preset to be turned on as in the prior art. In this embodiment, the clock control circuit can reduce power consumption and improve the simplicity of the circuit application.

Referring to FIG. 1, an embodiment of a clock control circuit of the present invention includes a clock generation unit 1 and a controller 2. In this embodiment, the clock control circuit is a mixed-signal integrated circuit.

The clock generation unit 1 receives a control signal Cs, and when the control signal Cs has a high logic level (ie, a logic level 1), the clock generation unit 1 can respond to the received The control signal Cs is activated to generate a clock signal clk. In the present embodiment, the clock generating unit 1 is, for example, a crystal oscillator.

The controller 2 includes a digital unit 21 and a clock control unit 22.

The digital unit 21 is electrically connected to the clock generating unit 1 to receive the clock signal clk, and is used to generate a first digital signal D1 indicating whether the initialization of the digital unit 21 is completed, and a digital operation indicating the digital unit 21 (That is, the related operation after the digital unit 21 is initialized and the clock signal clk is required to be executed, for example, preliminary automatic detection) whether the second digital signal D2 and the third digital signal D3 are completed. When the clock signal clk is received, the digit unit 21 operates in one of an initialization state and an initialization state, and when the initialization state operated by the digit unit 21 ends, the first The second digit signals D1, D2 each have the high logic level (ie, the digit unit 21 performs initialization and associated digital operations in accordance with the clock signal clk). Before the digitizing unit 21 is not in the initial state, the first and second digit signals D1, D2 each have the low logic level.

In this embodiment, the digital unit 21 includes a register 211 that stores and outputs the third digit signal D3. The digital unit 21 is also controlled by an external control signal Co from an external microprocessor (not shown) to adjust the level of the third digital signal D3. It should be noted that, in this embodiment, based on the power saving consideration, the level of the third digit signal D3 is preset to have a low logic level (ie, a logic 〝0〞 level). In other embodiments, the register 211 can be replaced by the external microprocessor, and the external microprocessor adjusts the level of the third digit signal D3.

The clock control unit 22 is electrically connected to the clock generation unit 1 and the digital unit 21, and receives a reset signal reset and the first to third digit signals D1, D2, and D3 from the digit unit 21, and according to The reset signal reset and the first to third digit signals D1, D2, and D3 generate the control signal Cs, and the control signal Cs is output to the clock generation unit 1. In the present embodiment, the clock control unit 22 includes first to third logic gates 221, 222, 223.

The first logic gate 221 has an output terminal and is electrically connected to the digitizing unit 21 to receive a first input end and a second input end of the first and second digit signals D1 and D2, respectively. The first logic gate 221 generates a first output signal V1 at the output end thereof according to the first and second digit signals D1 and D2. In this embodiment, the first logic gate 221 is a reverse gate.

The second logic gate 222 has a first input end electrically connected to the output end of the first logic gate 221 to receive the first output signal V1, and a register 211 electrically connected to the digital unit 21 to receive the a second input of the third digital signal D3, and an output. The second logic gate 222 generates a second output signal V2 at the output end according to the first output signal V1 and the third digit signal D3. In this embodiment, the second logic gate 222 is an OR gate.

The third logic gate 223 has a first input terminal for receiving the reset signal reset, a second input terminal electrically connected to the output end of the second logic gate 222 to receive the second output signal V2, and an output. end. The third logic gate 223 generates the control signal Cs at the output end thereof according to the reset signal reset and the second output signal V2. In this embodiment, the third logic gate 223 is a gate.

2, the operation timing diagram of the embodiment, the parameter reset is the reset signal, the parameters D1, D2, D3 are the first to third digit signals respectively, the parameter Cs is the control signal, and the parameter clk is the Clock signal, parameter t is time.

Referring to Figures 1 and 2, the operation of the clock control circuit of this embodiment will be described below.

At time point t0:

The clock control circuit receives a power signal (not shown), and the reset signal reset has the high logic level. It can be seen from FIG. 1 that the level of the control signal Cs is determined by the level of the second output signal V2, and the third digit signal D3 is preset to have the low logic level, so that the second output signal V2 The level depends on the level of the first output signal V1, and the level of the first output signal V1 depends on the levels of the first and second digit signals D1, D2. The clock control circuit just receives the power signal at time t0 (ie, corresponding to the reset signal reset has the high logic level) and the digital unit 21 is not initialized, therefore, the first and second The digital signals D1 and D2 each have the low logic level at the time point t0, such that the first and second output signals V1 and V2 each have the high logic level, and the control signal Cs also has the high logic. The timing is such that the clock generation unit 1 starts and generates the clock signal clk to the digital unit 21 for initialization and associated digital operation in response to the received control signal Cs.

At time point t0~t1:

The digital unit 21 receives the clock signal clk and starts initialization (ie, the digital unit 21 operates in the initialization state), the reset signal reset continues to have the high logic level, and the third digital signal D3 continues to have The low logic level, the first digital signal D1 is converted to the high logic level by the low logic level when the initialization of the digital unit 21 is completed, and the second digital signal D2 continues to have the low logic level (ie, The digital operation required to be performed after the initialization of the digital unit 21 is not completed. Therefore, the level of the control signal Cs depends on the level of the first output signal V1 (the principle point t0), and the first output The level of the signal V1 depends on the levels of the first and second digit signals D1, D2, such that the level of the control signal Cs continues to be at the high logic level. Briefly, between time points t0 and t1, as long as at least one of the first and second digit signals D1, D2 has the low logic level, the level of the control signal Cs is the high logic. Level. It should be noted that, in the present embodiment, the state at which the digit unit 21 performs initialization and the time point t0 to t1 of the associated digital operation is defined as the initialization state.

At time point t1:

The first digital signal D1 continues to have the high logic level, and the digital unit 21 completes the digital operation that needs to be performed after the initialization, so that the second digital signal D2 is converted from the low logic level to the high logic level. The first output signal V1 has the low logic level, and the third digital signal D3 continues to have the low logic level, so that the second output signal V2 has the low logic level, and the reset signal reset continues. Having the high logic level, the control signal Cs is converted to the low logic level by the high logic level, and the clock generation unit 1 is responsive to the received control signal Cs having the low logic level. The clock signal clk is not generated and stopped.

After time point t1:

The initialization state of the digital unit 21 is ended, the reset signal reset continues to have the high logic level, and the first and second digit signals D1, D2 each continue to have the high logic level. The level of the control signal Cs is related to the level of the third digit signal D3. For example, when the third digit signal D3 continues to have the low logic level (time point t1~t2), the control signal Cs has the low logic level (corresponding to the clock generation unit 1 not starting and stopping) The clock signal clk) is generated. When the third digit signal D3 is adjusted to have the high logic level (after time point t2), the control signal Cs is also converted to have the high logic level. At this time, the clock generation unit 1 starts again. And generating the clock signal clk to the digit unit 21, so that the digit unit 21 operates in the initialized state according to the clock signal clk (for example, the digit unit 21 performs automatic detection in the circuit again according to the clock signal clk. Features).

It should be noted that when the reset signal reset has the low logic level, the control signal Cs has the low logic level, so that the clock generation unit 1 responds to the received control signal Cs without start.

In summary, since the clock control circuit receives the power signal (corresponding to the reset signal reset having the high logic level), the clock control unit 22 can be based on the first and second The digital signal D1, D2 generates the control signal Cs having the high logic level to activate the clock generation unit 1, so that the clock generation unit 1 generates the clock signal clk to the digital unit 21 for initialization, and After the initialization of the digitizing unit 21, the clock control unit 22 can automatically disable the clock generating unit 1 so that the clock control circuit of the embodiment does not need to oscillate the crystal as in the conventional mixed signal integrated circuit. The preset is always in the starting state, and the clock control circuit of the embodiment can reduce the power consumption. In addition, in the embodiment, the clock control circuit does not need to preset the digital unit to be turned on and output a control signal having a high logic level as in the conventional mixed signal integrated circuit, and then execute a processor by a processor. The software determines whether the digital unit is initialized to convert the control signal from the high logic level to a low logic level. In this embodiment, the clock control circuit can improve the simplicity of the circuit application.

However, the above is only the embodiment of the present invention, and the scope of the invention is not limited thereto, and all the equivalent equivalent changes and modifications according to the scope of the patent application and the patent specification of the present invention are still The scope of the invention is covered.

1‧‧‧ clock generation unit
2‧‧‧ Controller
21‧‧‧Digital Unit
211‧‧‧ register
22‧‧‧clock control unit
221‧‧‧First Logic Gate
222‧‧‧Second logic gate
223‧‧‧third logic gate
Cs‧‧‧ control signal
Co‧‧‧ external control signal
Clk‧‧‧ clock signal
D1‧‧‧ first digit signal
D2‧‧‧ second digit signal
D3‧‧‧ third digit signal
Reset‧‧‧Reset signal
V1‧‧‧ first output signal
V2‧‧‧ second output signal
t·‧‧‧Time
T0‧‧‧ time point
T1‧‧‧ time
T2‧‧‧ time

Other features and advantages of the present invention will be apparent from the embodiments of the present invention, wherein: Figure 1 is a circuit block diagram illustrating one embodiment of the clock control circuit of the present invention; and Figure 2 is a timing diagram The figure illustrates the operation of this embodiment.

Claims (10)

A clock control circuit includes: a clock generation unit that receives a control signal, and when the control signal has a high logic level, the clock generation unit can be activated and generated in response to the received control signal a clock signal; and a controller, comprising: a digital unit, electrically connected to the clock generating unit to receive the clock signal, and configured to generate a first digit signal indicating an initialization of the digit unit, an indication The second digit signal and the third digit signal of whether the digital unit of the digital unit is completed, when the clock signal is received, the digit unit operates in one of an initialization state and an initialization state, and when At the end of the initialization state operated by the digital unit, the first and second digital signals each have the high logic level, and a clock control unit electrically connects the clock generating unit and the digital unit to receive a weight And a signal from the first to third digits of the digital unit, and based on the reset signal and the first to third digit signals The control signal is generated and output to the clock generation unit. The clock control circuit of claim 1, wherein: when the reset signal has the high logic level, the third digit signal has a low logic level, and the first and second digit signals When at least one of the low logic levels has the low logic level, the level of the control signal is the high logic level and the digital unit operates in the initialization state; and when the initialization state operated by the digital unit ends and the reset When the signal has the high logic level, the level of the control signal is related to the level of the third digital signal. The clock control circuit of claim 2, wherein: when each of the reset signal and the first to third digit signals has the high logic level, the level of the control signal is The high logic level and the digital unit operate in the initialized state. The clock control circuit of claim 1, wherein the clock control unit comprises: a first logic gate having an output terminal and electrically connecting the digit unit to receive the first and second digit signals, respectively a first input end and a second input end, the first logic gate generates a first output signal at the output end according to the first and second digit signals; a second logic gate has a Electrically connecting the output end of the first logic gate to receive the first input end of the first output signal, electrically connecting the digital unit to receive the second input end of the third digital signal, and an output end, the first The second logic gate generates a second output signal at the output end according to the first output signal and the third digit signal; and a third logic gate having a first input end for receiving the reset signal, Electrically connecting the output end of the second logic gate to receive the second input end of the second output signal, and an output end, the third logic gate is in the output according to the reset signal and the second output signal At the end, the control signal is generated. The clock control circuit of claim 4, wherein the first logic gate is a reverse gate, the second logic gate is a gate, and the third logic gate is a gate. The clock control circuit of claim 1, wherein the digit unit comprises a register for storing and outputting the third digit signal, the digit unit being further controlled by an external control signal to adjust the third digit The level of the signal. The clock control circuit of claim 1, wherein the clock generation unit is a crystal oscillator. A controller is configured to generate a control signal to control a clock generation unit. When the control signal has a high logic level, the clock generation unit is controlled to start and generate a clock signal. The controller includes: a digital unit for receiving the clock signal, and for generating a first digit signal indicating whether the initialization of the digit unit is completed, a second digit signal indicating whether the digitizing operation of the digit unit is completed, and a third a digit signal, when the clock signal is received, the digit unit operates in one of an initialization state and an initialization state, and when the initialization state operated by the digit unit ends, the first The second digital signals each have the high logic level; and a clock control unit electrically connected to the digital unit, receiving a reset signal and the first to third digital signals from the digital unit, and according to the reset The signal and the first to third digit signals generate the control signal, and the control signal is output to the clock generation unit. The controller of claim 8, wherein: when the reset signal has the high logic level, the third digit signal has a low logic level, and at least one of the first and second digit signals When the low logic level is present, the level of the control signal is the high logic level and the digit unit operates in the initialization state; when the initialization state operated by the digit unit ends and the reset signal has the When the logic level is high, the level of the control signal is related to the level of the third digit signal; and when the reset signal and each of the first to third digit signals have the high logic level The level of the control signal is the high logic level and the digital unit operates in the initialized state. The controller of claim 8, wherein the clock control unit comprises: a first logic gate having an output, and electrically connecting the digit unit to receive one of the first and second digit signals, respectively a first input end and a second input end, the first logic gate generates a first output signal at the output end according to the first and second digit signals; and a second logic gate having an electrical connection The output end of the first logic gate is configured to receive the first input end of the first output signal, the second input end electrically connected to the digital unit to receive the third digit signal, and an output end, the second logic The gate generates a second output signal at the output end according to the first output signal and the third digit signal; and a third logic gate having a first input terminal for receiving the reset signal, and an electrical connection The output end of the second logic gate receives the second input end of the second output signal, and an output end, the third logic gate is at the output end according to the reset signal and the second output signal This control signal is generated.