TWI627715B - Substrate structure - Google Patents

Abstract

A substrate structure includes a substrate body having a plurality of insulating layers and a circuit combination coupled to the substrate body and having a passive circuit, wherein at least one of the forming materials of the insulating layer is a high-dielectric constant material, so that the circuit is assembled. The capacitor circuit is formed on the insulating layer of the high-dielectric-constant material to maintain the signal quality and reduce the overall circuit area of the circuit combination.

Description

Substrate structure

The present invention relates to a substrate for a semiconductor package, and more particularly to a substrate structure having a passive circuit.

The traditional materials used for packaging substrates are materials with low dielectric constant (that is, Dk value is between 2.5 and 4) and low dielectric loss (low Df). Cross talk and parasitic capacitance to improve signal quality and suppress interference between lines.

Furthermore, with the development of packaging technology, it is common to place passive RF components (such as filters, power dividers, balanced-to-unbalanced converters, impedance matching circuits, etc.) in system-level packages. The RF component can be a discrete component, or it can be integrated into a package substrate.

In the technology of integrated passive radio frequency components, integrated passive radio frequency components are usually composed of equivalent inductors, capacitors, and transmission lines. As shown in FIG. 1A, the substrate structure 1 of a package substrate includes a substrate body 10 and a circuit assembly 11. The substrate body 10 includes a core layer 10b and dielectric layers 10a, 10c disposed on the upper and lower sides of the core layer 10b, respectively. The circuit combination 11 is coupled to the core layer 10b and the dielectric layers 10a and 10c. The circuit combination 11 includes passive circuits 11a (such as As shown in FIG. 1B, it includes a capacitor circuit C and an inductor circuit L), a plurality of circuit layers 11b, and a plurality of conductive blind holes 11c, and the conductive blind holes 11c are provided in the core layer 10b and the dielectric layers 10a. 10c.

In the aforementioned substrate structure 1, a material with a low dielectric constant (low Dk) is mainly used as the substrate body 10, that is, the dielectric coefficient of the core layer 10b and the dielectric layers 10a, 10c is about 2.5 to 4.

However, if the product requires a larger capacitance value, the area of the capacitor line C can only be increased without increasing the number of layers of the circuit combination 11.

However, increasing the area of the capacitor line C will make the area of the dielectric layer 10a occupied by the passive line 11a larger, so that the wiring space of the dielectric layer 10a becomes smaller, that is, the line layer 11b takes up the dielectric layer. The area of 10a becomes smaller, and even the electrical function is reduced.

Therefore, how to overcome the problems in the conventional technology has become an urgent issue.

In view of the lack of the above-mentioned conventional technologies, the present invention provides a substrate structure including a substrate body including a plurality of insulating layers stacked on each other, wherein at least one of the materials of the insulating layer is a high dielectric constant material, and at least one The material of the insulating layer is a low-dielectric-constant material; and the circuit combination includes a passive circuit and is coupled to the substrate body.

In the aforementioned substrate structure, the dielectric constant of the high dielectric constant material is greater than or equal to 6, and the dielectric constant of the low dielectric constant material is less than 6.

In the aforementioned substrate structure, the passive circuit includes a capacitor circuit, which is coupled to the insulating layer of the material with high dielectric constant.

In the aforementioned substrate structure, the passive circuit includes an inductive circuit, which is coupled to the insulating layer of the material with a low dielectric constant.

In the aforementioned substrate structure, the passive circuit includes a resistance circuit, which is coupled to the insulating layer of the material having a low dielectric constant or the material having a high dielectric constant.

In the aforementioned substrate structure, the circuit assembly further includes a circuit layer, which is bonded to the insulating layer of the material having a low dielectric constant.

In the aforementioned substrate structure, the middle position of the plurality of stacked insulating layers is a core layer.

In the aforementioned substrate structure, the plurality of insulating layers stacked on each other are laid out in an asymmetrical manner according to a dielectric constant.

In the aforementioned substrate structure, the plurality of insulating layers stacked on each other are laid out symmetrically in accordance with a dielectric constant.

In the aforementioned substrate structure, the passive line includes at least one of an inductive line, a resistive line, or a capacitive line.

In the aforementioned substrate structure, the thickness of the insulating layer of the high dielectric constant material is smaller than the thickness of other insulating layers.

It can be known from the above that the substrate structure of the present invention mainly comprises changing at least one insulating layer in the substrate body to a material having a high dielectric constant, so that the inductance circuit or the circuit layer is located on the insulating layer having a low dielectric constant material. However, passive lines that require a large amount of capacitive coupling are formed on the insulating layer of a material with a high dielectric constant, so that not only the original signal quality can be maintained, but also the overall line area of the line combination can be effectively reduced.

1,2,3,3 ’, 3”, 4,4 ’, 4”, 5,5 ’, 5”, 6,6’‧‧‧ substrate structure

10,20,30,30 ’, 30”, 40,40 ’, 40”, 50,50 ’, 50”, 60,60’‧‧‧‧Substrate body

10a, 10c‧‧‧Dielectric layer

10b‧‧‧Core layer

11,21‧‧‧ route combination

11a, 21a‧‧‧ Passive line

11b, 21b‧‧‧ Line layer

11c, 21c ‧ ‧ conductive blind hole

20a, 20b‧‧‧ Insulation

30a, 30a ’, 30a”, 30b, 30b ’, 30c‧‧‧‧Insulation

40a, 40a ’, 40b, 40b’, 40b ”, 40c‧‧‧Insulation

50a, 50a ’, 50b, 50b’, 50b ”, 50c, 50c’‧‧‧Insulation

60a, 60a ’, 60b, 60c‧‧‧Insulation

C‧‧‧capacitor line

h, t, r‧‧‧thickness

L‧‧‧ Inductive line

FIG. 1A is a schematic partial cross-sectional view of a conventional package substrate; FIG. 1B is a schematic top perspective view of a passive circuit of the package substrate of FIG. 1A.

Figure 2 is a schematic partial cross-sectional view of the first embodiment of the substrate structure of the present invention; Figures 3A to 3C are schematic partial cross-sectional views of the second embodiment of the substrate structure of the present invention; Figures 4A to 4C are Partial cross-sectional schematic diagram of the third embodiment of the substrate structure of the invention; Figures 5A to 5C are schematic partial cross-sectional diagrams of the fourth embodiment of the substrate structure of the invention; and Figures 6A to 6B are schematic diagrams of the substrate structure of the invention A schematic partial sectional view of the fifth embodiment.

The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. The limited conditions are not technically significant. Any modification of the structure, change of the proportional relationship, or adjustment of the size shall still fall within the scope of this invention without affecting the effects and goals that the invention can produce. The technical content disclosed by the invention can be covered. At the same time, the references in this manual The terms "between", "down", "up" and "one" are only for the convenience of description, and are not used to limit the scope of the present invention. The relative relationship is changed or adjusted without substantial changes. Under the technical content, it should be regarded as the scope in which the present invention can be implemented.

FIG. 2 is a schematic partial cross-sectional view of the first embodiment of the substrate structure 2 of the present invention.

The substrate structure 2 includes a substrate body 20 and a circuit assembly 21.

The substrate body 20 includes a plurality of (two layers in this embodiment) insulating layers 20a, 20b, and one of the insulating layers 20a includes a high-dielectric constant material having a dielectric constant greater than or equal to 6, The other insulating layer 20b includes a low-dielectric-constant material having a dielectric constant less than 6.

In this embodiment, the insulating layer of the high-dielectric constant material is shown in the drawing in the form of a dot distribution, and the insulating layer of the low-dielectric constant material is shown in the drawing in the form of the blank distribution. Be stated beforehand.

In this embodiment, the insulating layers 20a and 20b are dielectric layers, and the material thereof is prepreg or other known materials, and the thicknesses t of the insulating layers 20a and 20b are substantially equal.

The circuit combination 21 is coupled to the insulating layers 20a, 20b of the substrate body 20. For example, a part of the circuit combination 21 is disposed between the insulating layers 20a, 20b.

In this embodiment, the line combination 21 has at least one passive line 21a, a plurality of line layers 21b, and a plurality of conductive blind holes 21c electrically connected to each other. The passive line 21a includes an inductance line L and a resistance line. (The figure is omitted) or the capacitor line C, and the conductive blind holes 21c are disposed in the insulating layers 20a and 20b. For example, the inductance line L has a spiral coil shape (as shown in FIG. 1B), and the number of coils can be designed according to requirements.

Furthermore, the value (C) of the capacitive coupling of the capacitive line C is related to the dielectric constant (Dk = εr) of the material, the area (A) of the coupling pole piece of the passive line 21a, and the thickness d of the dielectric material, The relationship is as follows: C = ε r A / d

It can be known from the above formula that in order to maintain the capacitive coupling amount of a capacitor line, as long as the dielectric constant (Dk) of the dielectric material is increased or the material thickness d is decreased, the area A can be reduced.

Therefore, in the substrate structure 2 of this embodiment, one of the insulating layers 20a of the substrate body 20 includes a high-dielectric constant material having a dielectric constant greater than or equal to 6, and the other insulating layers 20b adopt a low dielectric constant. Materials to keep the inductive line L or the electrical circuit generally connected to the chip to be formed on the insulating layer 20b with a low dielectric constant (low Dk), and the capacitive line C that requires a large amount of capacitive coupling is formed on a high dielectric constant ( high Dk) on the insulating layer 20a can not only maintain the original signal quality, but also effectively reduce the overall circuit area of the capacitor circuit C, and it will not affect the wiring space of the circuit layer 21b in the same insulating layer 20a, or even increase the The wiring space of the wiring layer 21b in the same insulating layer 20a.

Specifically, if Dk is increased from the original 3.6 to 7.8, the overall circuit area of the circuit combination 21 can be reduced to 80% of the original total area, where the original total area is the insulation layer of the substrate body. The overall circuit area of the circuit combination for low dielectric constant (low Dk) materials.

In addition, the resistance line can be selected on an insulating layer having a high dielectric constant or a low dielectric constant.

3A to 3C are schematic partial cross-sectional views of the second embodiment of the substrate structures 3a, 3b, and 3c of the present invention. The difference between this embodiment and the first embodiment lies in the number of layers of the insulating layer, and the other structures are substantially the same. Therefore, the following detailed descriptions are different, and the same points are not repeated, and are hereby described.

As shown in FIG. 3A, the substrate body 30 includes three layers of insulating layers 30a, 30b, and 30c, and the intermediate insulating layer 30b is a core layer, and the insulating layers 30a and 30c located above and below the core layer are Is a dielectric layer.

In this embodiment, the insulating layer 30a on the upper side includes a high-dielectric-constant material having a dielectric constant greater than or equal to 6, and the other insulating layers 30b, 30c include a low-dielectric-constant material having a dielectric constant less than 6. .

Furthermore, the thickness h of the core layer (ie, the intermediate insulating layer 30b) is greater than the thickness t of the dielectric layers (ie, the other insulating layers 30a, 30c).

As shown in FIG. 3B, the substrate body 30 'is composed of three insulating layers 30a, 30b', 30c, and the insulating layers 30a, 30b ', 30c are dielectric layers.

In this embodiment, the thicknesses t of the insulating layers 30a, 30b ', 30c are substantially equal, and the insulating layer 30a on the upper side includes a high-dielectric constant material with a dielectric constant greater than or equal to 6, and the other insulating layers 30b ', 30c series contains a low dielectric constant material with a dielectric constant less than 6.

As shown in FIG. 3C, the substrate body 30 "is composed of five layers of insulating layers 30a, 30a ', 30a", 30b', 30c, and the insulating layers 30a, 30a ', 30a ", 30b', 30c are Is a dielectric layer.

In this embodiment, the insulating layers 30a, 30a ', 30a ", 30b', 30c The thickness t is approximately the same, and the insulating layer 30a of the upper second layer contains a high dielectric constant material having a dielectric constant greater than or equal to 6, while the other insulating layers 30a ', 30a ", 30b', 30c contain There is a low-dielectric-constant material having a dielectric constant less than 6, and the insulating layer 30a is sandwiched between the two insulating layers 30a ', 30a ".

As shown in Figures 3A to 3C, the insulating layers 30a, 30a ', 30a ", 30b, 30b', and 30c are laid out in an unbalanced manner according to the dielectric coefficient, that is, above the intermediate insulating layers 30b, 30b ' The levels of the dielectric coefficients of the insulating layers 30a, 30a ', 30a ", 30c on the lower sides are not equal, that is, they are not symmetrically distributed, and a circuit combination 21 is arranged on the insulating layers.

4A to 4C are schematic partial cross-sectional views of the third embodiment of the substrate structures 4a, 4b, and 4c of the present invention. The difference between this embodiment and the second embodiment lies in the lamination layout of the insulating layers, and other structures are substantially the same. Therefore, the following detailed description of the differences will not be repeated, and it is hereby described.

As shown in FIG. 4A, the substrate body 40 includes three layers of insulating layers 40a, 40b, and 40c, and the intermediate insulating layer 40b is a core layer, and the insulating layers 40a and 40c located above and below the core layer are Is a dielectric layer.

In this embodiment, the upper and lower sides of the insulating layer 40a, 40c include a high-dielectric constant material having a dielectric constant greater than or equal to 6, and the middle of the insulating layer 40b includes a low dielectric constant of a dielectric constant less than 6. The electric coefficient material makes these insulating layers 40a, 40b, and 40c be stacked in a balanced manner according to the dielectric constant, that is, the high and low levels of the dielectric coefficients of the insulating layers 40a and 40c on the upper and lower sides of the intermediate insulating layer 40b are shown. Symmetrical distribution.

It should be understood that although the insulating layers 40a and 40c on the upper and lower sides each include a high dielectric constant material having a dielectric constant greater than or equal to 6, the dielectric constants of the two may be the same or different.

As shown in FIG. 4B, the substrate body 40 'is composed of three insulating layers 40a, 40b', and 40c, and the insulating layers 40a, 40b ', and 40c are dielectric layers.

In this embodiment, the insulating layers 40a and 40c on the upper and lower sides include a high-dielectric constant material having a dielectric constant greater than or equal to 6, and the insulating layer 40b 'on the middle side includes a low dielectric constant less than 6. Dielectric constant material.

As shown in FIG. 4C, the substrate body 40 "includes five layers of insulating layers 40a ', 40b', 40b", and 40c, and the insulating layers 40a ', 40b', 40b ", and 40c are dielectric layers. .

In this embodiment, the insulating layer 40b "in the middle includes a high-dielectric-constant material with a dielectric constant greater than or equal to 6, and the other insulating layers 40a ', 40b', and 40c include a dielectric with a dielectric constant less than 6. Low dielectric constant material.

It should be understood that although the insulating layers 40a ', 40b', and 40c on the upper and lower sides each include a low-dielectric constant material having a dielectric constant less than 6, the dielectric constants of the layers may be the same or different.

Therefore, as shown in FIGS. 4A to 4C, the insulating layers 40a, 40a ', 40b, 40b', 40b ", 40c are laid out in a balanced manner according to the dielectric constant, that is, the intermediate insulating layers 40b, 40b ', 40b. The dielectric layers of the upper and lower insulating layers 40a, 40a ', 40b', and 40c are symmetrically distributed, and a circuit set 21 is arranged on the insulating layers.

Figures 5A to 5C are the fourth of the substrate structures 5a, 5b, and 5c of the present invention. A schematic partial cross-sectional view of the embodiment. The difference between this embodiment and the third embodiment lies in the change of the balanced lamination layout, and other structures are substantially the same, so the following detailed description of the differences will not be repeated, and it is hereby described.

As shown in FIG. 5A, the substrate body 50 includes three layers of insulating layers 50a, 50b, and 50c, and the intermediate insulating layer 50b is a core layer, and the insulating layers 50a and 50c located above and below the core layer are Is a dielectric layer.

In this embodiment, the insulating layer 50b in the middle contains a high-dielectric-constant material having a dielectric constant greater than or equal to 6, and the other insulating layers 50a, 50c include a low-dielectric-constant material having a dielectric constant smaller than 6. The insulating layers 50a, 50b, and 50c are laid out in a balanced manner according to the dielectric constant.

It should be understood that although the insulating layers 50a and 50c on the upper and lower sides each include a low-dielectric-constant material with a dielectric constant less than 6, the dielectric constants of the two may be the same or different.

As shown in FIG. 5B, the substrate body 50 'is composed of three insulating layers 50a, 50b', 50c, and the insulating layers 50a, 50b ', 50c are dielectric layers.

In this embodiment, the insulating layer 50b ′ in the middle contains a high-dielectric-constant material with a dielectric constant greater than or equal to 6, and the insulating layers 50a and 50c on the upper and lower sides contain a low-dielectric constant less than 6. Dielectric constant material.

As shown in FIG. 5C, the substrate body 50 "includes seven layers of insulating layers 50a, 50a ', 50b", 50c, 50c', and the insulating layers 50a, 50a ', 50b ", 50c, 50c' are Is a dielectric layer.

In this embodiment, the upper second insulating layer 50a 'and the lower second insulating layer 50c' include a high dielectric constant material having a dielectric constant greater than or equal to 6, and other insulating layers 50a, "50b", 50c include A low dielectric constant material with a dielectric constant less than 6.

It should be understood that the levels of the dielectric coefficients of the insulating layers 50a, 50a ', 50c, 50c' on the upper and lower sides are symmetrically distributed, but the dielectric coefficients of the layers on both sides may be the same or different.

Therefore, as shown in Figures 5A to 5C, the insulating layers 50a, 50a ', 50b, 50b', 50b ", 50c, 50c 'are laid out in a balanced manner according to the dielectric constant, that is, the intermediate insulating layers 50b, 50b The insulation layers 50a, 50a ', 50c, and 50c' on the upper and lower sides of the ', 50b' are symmetrically distributed in the high and low levels, and a circuit combination 21 is arranged on the insulation layers.

6A to 6B are schematic views of a fifth embodiment of the substrate structures 6a and 6b of the present invention. The difference between this embodiment and the first embodiment lies in the number of layers of the insulating layer, and the other structures are substantially the same. Therefore, the following detailed descriptions are different, and the same points are not repeated, and are hereby described.

As shown in FIG. 6A, the substrate body 60 is composed of three insulating layers 60a, 60b, and 60c, and the intermediate insulating layer 60b is a core layer, and the insulating layers 60a, 60c are located above and below the core layer. Is a dielectric layer.

In this embodiment, the insulating layer 60a on the upper side includes a high-dielectric-constant material having a dielectric constant greater than or equal to 6, and the other insulating layers 60b, 60c include a low-dielectric-constant material having a dielectric constant less than 6. .

Furthermore, the thickness h of the core layer (ie, the intermediate insulating layer 60b) is greater than the thickness t of the dielectric layers (ie, the other insulating layers 60a, 60c). Alternatively, as shown in FIG. 6B, the thickness r of the insulating layer 60a 'containing the high dielectric constant material is smaller than the thicknesses t, h of the other insulating layers 60b, 60c (i.e., r <t < h).

It can be known from the above formula that, in order to maintain the capacitive coupling amount of a circuit, as long as the Dk of the dielectric material is increased or the thickness of the dielectric material is decreased, the effect of reducing the circuit area can be achieved. Therefore, in the substrate structure 6 'shown in FIG. 6B, one of the insulating layers 60a' of the substrate body 60 'includes a high dielectric constant material having a dielectric constant greater than or equal to 6, and the insulating layer 60a' The thickness r is smaller than the thicknesses t and h of the other insulating layers 60b and 60c, so that the capacitor circuit C is formed on the insulating layer 60a ', which can not only maintain the original signal quality, but also effectively reduce the entirety of the capacitor circuit C. The circuit area will not affect the wiring space of the wiring layer 21b in the same insulating layer 60a ', and may even increase the wiring space of the wiring layer 21b in the same insulating layer 60a'.

Specifically, if Dk is increased from the original 3.6 to 7.8, and the thickness of the insulation layer is reduced, the overall circuit area of the circuit combination 21 can be reduced to 70% of the original total area, where the original total area is the The overall circuit area of the circuit combination when the insulation layers of the substrate body are all low Dk.

In summary, the substrate structure of the present invention is to change a part of the insulating layer in the substrate body to a high-dielectric-constant material, and the remaining insulating layer to maintain a low-dielectric-constant material, and the inductance circuit or the circuit layer should be located at the low-level On the insulating layer of the dielectric constant material, passive circuits that require a large amount of capacitive coupling are formed on the insulating layer of the high dielectric constant material, so not only can it maintain the original signal quality, but it can also effectively reduce the overall size of the circuit combination. Circuit area, thereby reducing costs.

Furthermore, reducing the thickness of the insulating layer of the high-dielectric constant material can further reduce the overall circuit area of the circuit combination.

The above embodiments are used to exemplify the principle of the present invention and its effects, but not to limit the present invention. Anyone skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

Claims (10)

A substrate structure includes a substrate body including a plurality of insulating layers stacked on each other, wherein at least one material of the insulating layer is a high dielectric constant material, and at least one of the insulating layer is a low dielectric constant material. Among them, the thickness of the insulating layer of the material with high dielectric constant is smaller than the thickness of other insulating layers; and the circuit combination includes passive lines and is coupled to the substrate body. The substrate structure according to item 1 of the scope of patent application, wherein the dielectric constant of the high dielectric constant material is greater than or equal to 6, and the dielectric constant of the low dielectric constant material is less than 6. The substrate structure according to item 1 of the scope of the patent application, wherein the passive circuit comprises a capacitor circuit which is coupled to the insulating layer of a material with a high dielectric constant. The substrate structure according to item 1 of the scope of the patent application, wherein the passive circuit comprises an inductive circuit, which is coupled to the insulating layer of a material with a low dielectric constant. The substrate structure according to item 1 of the scope of the patent application, wherein the passive circuit comprises a resistance circuit which is bonded to the insulating layer of a material with a low dielectric constant or a material with a high dielectric constant. The substrate structure according to item 1 of the scope of the patent application, wherein the circuit combination includes a circuit layer, which is bonded to the insulating layer of a material with a low dielectric constant. The substrate structure according to item 1 of the scope of patent application, wherein the middle position of the plurality of insulating layers stacked on each other is a core layer. The substrate structure according to item 1 of the scope of the patent application, wherein the plurality of insulating layers stacked on each other are laid out in an asymmetrical manner according to a dielectric coefficient. The substrate structure according to item 1 of the scope of the patent application, wherein the plurality of insulating layers stacked on each other are symmetrically stacked according to the dielectric constant. The substrate structure according to item 1 of the scope of patent application, wherein the passive circuit includes at least one of an inductive circuit, a resistive circuit or a capacitive circuit.