TWI623116B - Light-Emitting Device - Google Patents
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Abstract
一種發光元件,包含:一支持基板,包含一第一表面以及相對於第一表面之一第二表面;一覆晶發光二極體,接合於第一表面,包含一第一接合墊、一第二接合墊以及一第三接合墊;一導電通道及一導熱通道,相互電性絕緣,位於支持基板中由第一表面延伸至第二表面;以及一導電墊及一導熱墊,位於第二表面,分別與導電通道及導熱通道連接;其中第一接合墊與第二接合墊其中之一連接導電通道,第三接合墊連接導熱通道。A light-emitting element comprising: a support substrate comprising a first surface and a second surface opposite to the first surface; a flip-chip light emitting diode bonded to the first surface, comprising a first bonding pad, a first a bonding pad and a third bonding pad; a conductive path and a heat conducting channel electrically insulated from each other, extending from the first surface to the second surface in the supporting substrate; and a conductive pad and a thermal pad on the second surface And connecting to the conductive channel and the heat conducting channel respectively; wherein one of the first bonding pad and the second bonding pad is connected to the conductive channel, and the third bonding pad is connected to the heat conducting channel.
Description
本發明係關於一種發光元件,更詳言之,係關於一種覆晶型的發光二極體元件。The present invention relates to a light-emitting element, and more particularly to a flip-chip type light-emitting diode element.
發光二極體(Light-Emitting Diode, LED)為固態半導體發光元件,其優點為功耗低,產生的熱能低,工作壽命長,體積小,反應速度快和具有良好的光電特性,例如穩定的發光波長。因此發光二極體被廣泛應用於家用電器,設備指示燈,及光電產品等。Light-Emitting Diode (LED) is a solid-state semiconductor light-emitting device, which has the advantages of low power consumption, low heat energy, long working life, small volume, fast response speed and good photoelectric characteristics, such as stable The wavelength of the light. Therefore, the light-emitting diodes are widely used in household appliances, equipment indicator lights, and optoelectronic products.
一種發光元件,包含:一支持基板,包含一第一表面以及相對於第一表面之一第二表面;一覆晶發光二極體,接合於第一表面,包含一第一接合墊、一第二接合墊以及一第三接合墊;一導電通道及一導熱通道,相互電性絕緣,位於支持基板中由第一表面延伸至第二表面;以及一導電墊及一導熱墊,位於第二表面,分別與導電通道及導熱通道連接;其中第一接合墊與第二接合墊其中之一連接導電通道,第三接合墊連接導熱通道。A light-emitting element comprising: a support substrate comprising a first surface and a second surface opposite to the first surface; a flip-chip light emitting diode bonded to the first surface, comprising a first bonding pad, a first a bonding pad and a third bonding pad; a conductive path and a heat conducting channel electrically insulated from each other, extending from the first surface to the second surface in the supporting substrate; and a conductive pad and a thermal pad on the second surface And connecting to the conductive channel and the heat conducting channel respectively; wherein one of the first bonding pad and the second bonding pad is connected to the conductive channel, and the third bonding pad is connected to the heat conducting channel.
一種發光元件,包含:一支持基板,包含一第一表面以及相對於第一表面之一第二表面;一覆晶發光二極體,接合於第一表面,包含一第一接合墊、一第二接合墊以及一第三接合墊;一導熱通道,位於支持基板中,由第一表面延伸至第二表面;以及一導熱墊,位於第二表面,與導熱通道連接;其中第三接合墊與第一接合墊及第二接合墊之間皆為電性絕緣,且第三接合墊連接導熱通道。A light-emitting element comprising: a support substrate comprising a first surface and a second surface opposite to the first surface; a flip-chip light emitting diode bonded to the first surface, comprising a first bonding pad, a first a bonding pad and a third bonding pad; a heat conducting channel extending from the first surface to the second surface in the supporting substrate; and a thermal pad on the second surface connected to the heat conducting channel; wherein the third bonding pad is The first bonding pad and the second bonding pad are electrically insulated, and the third bonding pad is connected to the heat conduction channel.
本申請案之實施例會被詳細地描述,並且繪製於圖式中,相同或類似的部分會以相同的號碼在各圖式以及說明出現。The embodiments of the present application will be described in detail, and in the drawings, the same or the like
第1A圖為依據本申請案一實施例中所揭示之一發光二極體10之正面上視圖。第1B圖為依據本申請案之一實施例中所揭示之一發光元件1之截面圖。如第1B圖所示,發光元件1包含如第1A圖所示之發光二極體10以正面朝下之覆晶方式接合於一支持基板100之第一表面101,即發光二極體10之正面面對支持基板100的第一表面101,發光二極體10為一覆晶發光二極體。其中第1B圖所繪示的發光二極體10截面即為沿第1A圖中A-A’線段之截面。FIG. 1A is a front elevational view of a light emitting diode 10 according to an embodiment of the present application. 1B is a cross-sectional view of a light-emitting element 1 disclosed in accordance with an embodiment of the present application. As shown in FIG. 1B, the light-emitting element 1 includes the light-emitting diode 10 as shown in FIG. 1A and is flip-chip bonded to the first surface 101 of a support substrate 100, that is, the light-emitting diode 10 The front surface faces the first surface 101 of the support substrate 100, and the light-emitting diode 10 is a flip-chip light-emitting diode. The cross section of the light emitting diode 10 shown in Fig. 1B is a section along the line A-A' in Fig. 1A.
發光二極體10具有一半導體疊層20,包含一第一半導體層201、一第二半導體層202,以及一活性層203位於第一半導體層201與第二半導體層202之間。第一半導體層201與第二半導體202層具有不同之導電性、電性、極性或摻雜物以分別提供電洞與電子。極性可為n型或p型,使得電子與電洞可於活性層中複合以產生光線。舉例而言,第一半導體層201可為n型半導體層,第二半導體層202可為p型半導體層。藉由改變半導體疊層20中一層或多層的組成以調整發光二極體10所發出光線的波長。半導體疊層20之材料包含Ⅲ-Ⅴ族半導體材料,例如Alx Iny Ga(1-x-y) N或Alx Iny Ga(1-x-y) P,其中0≦x,y≦1;(x+y)≦1。依據活性層之材料,當半導體疊層材料為AlInGaP系列材料時,可發出波長介於610 nm及650 nm之間的紅光,波長介於530 nm及570 nm之間的綠光,當半導體疊層20材料為InGaN系列材料時,可發出波長介於450 nm及490 nm之間的藍光,或是當半導體疊層20材料為AlGaN、AlGaInN系列材料時,可發出波長介於400 nm及250 nm之間的紫外光。活性層203可為單異質結構(single heterostructure, SH ),雙異質結構(double heterostructure, DH ),雙側雙異質結構( double-side double heterostructure, DDH ),多層量子井結構(multi-quantum well, MQW)。活性層材料可為中性、p型或n型電性的半導體。如第1B圖所示,於本實施例中,發光二極體10在相對於支持基板100之第一半導體層201表面可具有粗化結構,可增加光的散射並増進發光效率。於另一實施例中,在相對於支持基板100之發光二極體10表面可具有一成長基板(圖未示)。The light emitting diode 10 has a semiconductor layer 20 including a first semiconductor layer 201 and a second semiconductor layer 202, and an active layer 203 is disposed between the first semiconductor layer 201 and the second semiconductor layer 202. The first semiconductor layer 201 and the second semiconductor 202 layer have different electrical, electrical, polar or dopants to provide holes and electrons, respectively. The polarity can be either n-type or p-type such that electrons and holes can be combined in the active layer to produce light. For example, the first semiconductor layer 201 may be an n-type semiconductor layer, and the second semiconductor layer 202 may be a p-type semiconductor layer. The wavelength of the light emitted by the light-emitting diode 10 is adjusted by changing the composition of one or more layers in the semiconductor laminate 20. The material of the semiconductor stack 20 comprises a III-V semiconductor material, such as Al x In y Ga (1-xy) N or Al x In y Ga (1-xy) P, where 0 ≦ x, y ≦ 1; (x +y)≦1. According to the material of the active layer, when the semiconductor laminate is AlInGaP series material, red light with a wavelength between 610 nm and 650 nm and green light with a wavelength between 530 nm and 570 nm can be emitted as a semiconductor stack. When the layer 20 material is InGaN series material, it can emit blue light with wavelength between 450 nm and 490 nm, or when the semiconductor laminate 20 material is AlGaN or AlGaInN series materials, it can emit wavelengths between 400 nm and 250 nm. Between the ultraviolet light. The active layer 203 may be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well structure. MQW). The active layer material can be a neutral, p-type or n-type electrical semiconductor. As shown in FIG. 1B, in the present embodiment, the light-emitting diode 10 can have a roughened structure on the surface of the first semiconductor layer 201 with respect to the support substrate 100, which can increase the scattering of light and the luminous efficiency. In another embodiment, a surface of the light-emitting diode 10 relative to the support substrate 100 may have a growth substrate (not shown).
在半導體疊層20中,部分區域之第二半導體層202及活性層203被移除,以暴露出第一半導體層201及第二半導體層202及活性層203之側壁,形成複數個暴露區。其中,暴露區包含位於半導體疊層20內部的複數個第一暴露區30a,以及位於半導體疊層10週圍邊緣的第二暴露區30b。於本實施例中,除部分區域之第二半導體層202及活性層203被移除外,還更進一步移除部分第一半導體層201,其中,第一半導體層201、第二半導體層202及活性層203之側壁構成複數個第一暴露區30a及第二暴露區30b之側壁;第一半導體層201次露出的表面構成第一暴露區30a及第二暴露區30b之底面;複數個第一暴露區30a可以是複數個孔洞或條狀溝槽,於本實施例中,複數個第一暴露區30a是複數個孔洞,其中,孔洞的配置、數量及大小可依電流分佈的需求而有不同的設計。一電流分散層18位於第二半導體層202之表面,且與第二半導體層202電性接觸,電流分散層18可以是金屬或是透明導電材料,其中金屬可選自具有透光性的薄金屬層,透明導電材料包含銦錫氧化物(ITO)、氧化鋁鋅(AZO)、氧化鎵鋅(GZO)、或銦鋅氧化物(IZO)等材料。一反射結構16藉由蒸鍍或沉積等方式形成於電流分散層18上,反射結構16可由一反射層(圖未示)及/或一阻障層(圖未示)所組成,其中反射層位於電流分散層18及阻障層(圖未示)之間。於本申請案實施例中,於發光二極體10上視圖,反射層的外緣可設置於電流分散層18的外緣之內側、外側、或者與電流分散層18的外緣重合對齊,阻障層的外緣可設置於反射層的外緣之內側、外側、或者設置成與反射層的外緣重合對齊。於本申請案之另一實施例中,可省略電流分散層18,以反射結構16直接形成於第二半導體層202上。In the semiconductor stack 20, a portion of the second semiconductor layer 202 and the active layer 203 are removed to expose sidewalls of the first semiconductor layer 201 and the second semiconductor layer 202 and the active layer 203 to form a plurality of exposed regions. The exposed region includes a plurality of first exposed regions 30a located inside the semiconductor laminate 20, and a second exposed region 30b located at an edge of the semiconductor laminate 10. In this embodiment, in addition to the removal of the second semiconductor layer 202 and the active layer 203 of the partial region, a portion of the first semiconductor layer 201 is further removed, wherein the first semiconductor layer 201, the second semiconductor layer 202, and The sidewalls of the active layer 203 form a plurality of sidewalls of the first exposed region 30a and the second exposed region 30b; the exposed surface of the first semiconductor layer 201 constitutes a bottom surface of the first exposed region 30a and the second exposed region 30b; The exposed area 30a may be a plurality of holes or strip-shaped grooves. In this embodiment, the plurality of first exposed areas 30a are a plurality of holes, wherein the arrangement, the number and the size of the holes may be different according to the current distribution requirements. the design of. A current dispersion layer 18 is located on the surface of the second semiconductor layer 202 and is in electrical contact with the second semiconductor layer 202. The current dispersion layer 18 may be a metal or a transparent conductive material, wherein the metal may be selected from a thin metal having light transmissivity. The transparent conductive material comprises a material such as indium tin oxide (ITO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), or indium zinc oxide (IZO). A reflective structure 16 is formed on the current dispersion layer 18 by evaporation or deposition. The reflective structure 16 may be composed of a reflective layer (not shown) and/or a barrier layer (not shown), wherein the reflective layer Located between the current dispersion layer 18 and the barrier layer (not shown). In the embodiment of the present application, in the upper view of the light emitting diode 10, the outer edge of the reflective layer may be disposed on the inner side or the outer side of the outer edge of the current dispersion layer 18, or coincide with the outer edge of the current dispersion layer 18, and is blocked. The outer edge of the barrier layer may be disposed on the inner side, the outer side of the outer edge of the reflective layer, or disposed to coincide with the outer edge of the reflective layer. In another embodiment of the present application, the current spreading layer 18 may be omitted, and the reflective structure 16 is directly formed on the second semiconductor layer 202.
反射層可為一或多層之結構,多層之結構例如為一布拉格反射(DBR)結構。反射層之材料包含反射率較高的金屬材料,例如銀(Ag)、鋁(Al)、或銠(Rh)等金屬或上述材料之合金。在此所述具有較高的反射率係指對於發光二極體10所發出光線的波長具有80%以上的反射率。於本申請案之一實施例中,阻障層包覆反射層以避免反射層表面氧化而使反射層之反射率劣化。阻障層之材料包含金屬材料,例如鈦(Ti)、鎢(W)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、鉑(Pt)等金屬或上述材料之合金。阻障層可為一或多層之結構,多層結構例如為鈦(Ti)/鋁(Al),及/或鈦(Ti)/ 鎢(W)。The reflective layer can be one or more layers of structure, such as a Bragg reflection (DBR) structure. The material of the reflective layer contains a metal material having a high reflectance, such as a metal such as silver (Ag), aluminum (Al), or rhodium (Rh) or an alloy of the above materials. The higher reflectance as used herein means a reflectance of 80% or more for the wavelength of the light emitted from the light-emitting diode 10. In an embodiment of the present application, the barrier layer covers the reflective layer to prevent oxidation of the surface of the reflective layer to deteriorate the reflectivity of the reflective layer. The material of the barrier layer comprises a metal material such as a metal such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) or the like. alloy. The barrier layer may be one or more layers, such as titanium (Ti) / aluminum (Al), and / or titanium (Ti) / tungsten (W).
一第一絕緣層40覆蓋半導體疊層20之表面、複數第一暴露區30a之側壁及第二暴露區30b之側壁,具有一第一群組的第一絕緣層開口401以裸露出第一暴露區30a內的第一半導體層201,以及一第二群組的第一絕緣層開口402以裸露出反射結構16。第1B圖中以一點鏈線圈出之局部放大圖表示第二群組的第一絕緣層開口402附近之結構。第一群組及第二群組的第一絕緣層開口401及402形狀包含圓形、橢圓形、矩形、多邊形、環形或是任意形狀。於本實施例中,第一絕緣層40可為單層或多層之構造。當第一絕緣層40為單層膜時,第一絕緣層40可保護半導體疊層20之側壁以避免活性層203被後續製程所破壞,以及避免元件操作時發生短路。當第一絕緣層40為多層膜時,第一絕緣層40可包含兩種以上具有不同折射率的之材料交替堆疊,以形成一布拉格反射鏡(DBR)結構,選擇性地反射特定波長之光。於一實施例中,第一絕緣層40係為非導電材料所形成,包含有機材料,例如Su8、苯并環丁烯(BCB)、過氟環丁烷(PFCB)、環氧樹脂(Epoxy)、丙烯酸樹脂(Acrylic Resin)、環烯烴聚合物(COC)、聚甲基丙烯酸甲酯(PMMA)、聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚醚醯亞胺(Polyetherimide)、氟碳聚合物(Fluorocarbon Polymer),或是無機材料,例如矽膠(Silicone)、玻璃(Glass),或是介電材料,例如氧化鋁(Al2 O3 )、氮化矽(SiNx )、氧化矽(SiOx )、氧化鈦(TiOx ),或氟化鎂(MgFx )等。A first insulating layer 40 covers the surface of the semiconductor stack 20, the sidewalls of the plurality of first exposed regions 30a and the sidewalls of the second exposed regions 30b, and has a first group of first insulating layer openings 401 to expose the first exposure A first semiconductor layer 201 within region 30a, and a second group of first insulating layer openings 402 to expose reflective structure 16. The partially enlarged view of the one-dot chain coil in Fig. 1B shows the structure in the vicinity of the first insulating layer opening 402 of the second group. The shapes of the first insulating layer openings 401 and 402 of the first group and the second group include a circle, an ellipse, a rectangle, a polygon, a ring, or an arbitrary shape. In the embodiment, the first insulating layer 40 may be a single layer or a plurality of layers. When the first insulating layer 40 is a single layer film, the first insulating layer 40 can protect the sidewalls of the semiconductor stack 20 to prevent the active layer 203 from being damaged by subsequent processes, and to avoid short circuits when the components are operated. When the first insulating layer 40 is a multilayer film, the first insulating layer 40 may comprise two or more materials having different refractive indices alternately stacked to form a Bragg mirror (DBR) structure to selectively reflect light of a specific wavelength. . In one embodiment, the first insulating layer 40 is formed of a non-conductive material, and includes an organic material such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), and epoxy resin (Epoxy). Acrylic Resin, cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyether quinone (Polyetherimide), Fluorocarbon Polymer, or inorganic materials such as Silicone, Glass, or dielectric materials such as alumina (Al 2 O 3 ), tantalum nitride (SiN) x ), cerium oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ).
一接觸層50位於第一絕緣層40上,且填入第一群組的第一絕緣層開口401以接觸第一暴露區30a內的第一半導體層201,並透過第一絕緣層40與第二半導體層202電性絕緣。接觸層50具有接觸層開口501對應位於第二群組的第一絕緣層開口402處。於本申請案之一實施例中,接觸層50可包覆第二暴露區30b側壁上的第一絕緣層40,並延伸至接觸第二暴露區30b由第一半導體層201表面構成的底面,如此一來,接觸層50與第一半導體層201之接觸區域除了複數個第一暴露區30a的底面區域外,更包含圍繞複數第一暴露區30a的第二暴露區30b的底面區域,如此可增進電流散佈並得到較低的順向電壓。於本申請案另一實施例中,發光二極體不具有第一暴露區30a,只有半導體疊層10週圍邊緣的第二暴露區30b。接觸層50僅藉由第二暴露區30b與第一半導體層201接觸。接觸層50可為一或多層之結構,為了降低與第一半導體層201相接觸的電阻,接觸層50之材料包含金屬材料,例如鉻(Cr)、鈦(Ti)、鎢(W)、金(Au)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、鉑(Pt)等金屬或上述材料之合金。於本申請案之一實施例中,接觸層50之材料優選地包含具有高反射率之金屬,例如鋁(Al)、鉑(Pt)。於本申請案之一實施例中,接觸層50為多層之結構,與第一半導體層201相接觸側的材料優選地包含鉻(Cr)或鈦(Ti)以增加其與第一半導體層201的接合強度。A contact layer 50 is located on the first insulating layer 40, and fills the first group of first insulating layer openings 401 to contact the first semiconductor layer 201 in the first exposed region 30a, and transmits through the first insulating layer 40 and The second semiconductor layer 202 is electrically insulated. The contact layer 50 has a contact layer opening 501 corresponding to the first insulating layer opening 402 of the second group. In an embodiment of the present application, the contact layer 50 may cover the first insulating layer 40 on the sidewall of the second exposed region 30b and extend to contact the bottom surface of the second exposed region 30b formed by the surface of the first semiconductor layer 201. In this way, the contact area of the contact layer 50 and the first semiconductor layer 201 includes the bottom surface area of the second exposed area 30b surrounding the plurality of first exposed areas 30a, in addition to the bottom surface area of the plurality of first exposed areas 30a. Increase current spreading and get a lower forward voltage. In another embodiment of the present application, the light emitting diode does not have the first exposed region 30a, only the second exposed region 30b of the peripheral edge of the semiconductor laminate 10. The contact layer 50 is in contact with the first semiconductor layer 201 only by the second exposed region 30b. The contact layer 50 may be one or more layers. In order to reduce the electrical resistance in contact with the first semiconductor layer 201, the material of the contact layer 50 comprises a metal material such as chromium (Cr), titanium (Ti), tungsten (W), gold. A metal such as (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), or platinum (Pt) or an alloy of the above materials. In one embodiment of the present application, the material of the contact layer 50 preferably comprises a metal having high reflectivity, such as aluminum (Al), platinum (Pt). In one embodiment of the present application, the contact layer 50 is a multi-layered structure, and the material on the side in contact with the first semiconductor layer 201 preferably contains chromium (Cr) or titanium (Ti) to increase it and the first semiconductor layer 201. Joint strength.
一第二絕緣層60形成於接觸層50上,具有第一群組的第二絕緣層開口601以暴露接觸層50,以及在對應第二群組的第一絕緣層開口402與接觸層開口501的位置上具有一第二群組的第二絕緣層開口602,以暴露反射結構16,其中位於第二半導體層202上的接觸層50夾置於第一絕緣層40及第二絕緣層60之間,第一群組的第二絕緣層開口601與第一群組的第一絕緣層開口401開口可錯開,互不重疊。如此一來,從第一群組的第二絕緣層開口601注入的電流,可先在接觸層50擴散開來,再經由第一群組的第一絕緣層開口401注入到第一半導體層201內。同樣地,第一群組及第二群組的第二絕緣層開口601及602形狀包含圓形、橢圓形、矩形、多邊形、環形或是任意形狀。於本實施例中,第二絕緣層60可為單層或多層之構造。當第二絕緣層60為單層膜時,第二絕緣層60可保護半導體疊層20之側壁以避免被後續製程所破壞以及避免電性短路發生。當第二絕緣層60為多層膜時,第二絕緣層60可包含兩種以上具有不同折射率的之材料交替堆疊,以形成一布拉格反射鏡(DBR)結構,選擇性地反射特定波長之光。第二絕緣層60係為非導電材料所形成,包含有機材料,例如Su8、苯并環丁烯(BCB)、過氟環丁烷(PFCB)、環氧樹脂(Epoxy)、丙烯酸樹脂(Acrylic Resin)、環烯烴聚合物(COC)、聚甲基丙烯酸甲酯(PMMA)、聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚醚醯亞胺(Polyetherimide)、氟碳聚合物(Fluorocarbon Polymer),或是無機材料,例如矽膠(Silicone)、玻璃(Glass),或是介電材料,例如氧化鋁(Al2 O3 )、氮化矽(SiNx )、氧化矽(SiOx )、氧化鈦(TiOx ),或氟化鎂(MgFx )等。A second insulating layer 60 is formed on the contact layer 50, having a first group of second insulating layer openings 601 to expose the contact layer 50, and corresponding to the second group of first insulating layer openings 402 and contact layer openings 501. a second insulating layer opening 602 having a second group to expose the reflective structure 16, wherein the contact layer 50 on the second semiconductor layer 202 is sandwiched between the first insulating layer 40 and the second insulating layer 60 The second insulating layer opening 601 of the first group and the opening of the first insulating layer opening 401 of the first group may be staggered without overlapping each other. In this way, the current injected from the second insulating layer opening 601 of the first group may be diffused first in the contact layer 50 and then injected into the first semiconductor layer 201 via the first insulating layer opening 401 of the first group. Inside. Similarly, the shapes of the second insulating layer openings 601 and 602 of the first group and the second group include a circle, an ellipse, a rectangle, a polygon, a ring, or an arbitrary shape. In the embodiment, the second insulating layer 60 may be a single layer or a multilayer structure. When the second insulating layer 60 is a single layer film, the second insulating layer 60 can protect the sidewalls of the semiconductor stack 20 from being damaged by subsequent processes and avoiding electrical shorts. When the second insulating layer 60 is a multilayer film, the second insulating layer 60 may comprise two or more materials having different refractive indices alternately stacked to form a Bragg mirror (DBR) structure to selectively reflect light of a specific wavelength. . The second insulating layer 60 is formed of a non-conductive material, and includes an organic material such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), and acrylic resin (Acrylic Resin). ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon Fluorocarbon Polymer, or an inorganic material such as Silicone, Glass, or a dielectric material such as alumina (Al 2 O 3 ), tantalum nitride (SiN x ), or antimony oxide ( SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ).
發光二極體10具有一第一接合墊110a、一第二接合墊110b以及一第三接合墊110c分別設置於第二絕緣層60上,在空間上彼此相互分離。於本申請案實施例中,第三接合墊110c位於第一接合墊110a與第二接合墊110b之間。第三接合墊110c與第一接合墊110a之間,以及第三接合墊110c與第二接合墊110b之間具有一間距。第一接合墊110a填入第二絕緣層60的第一群組的第二絕緣層開口601與接觸層50相連接,進而與第一半導體層201電性連接。第二接合墊110b填入第二絕緣層60的第二群組的第二絕緣層開口602與反射結構16相連接,因此第二接合墊110b進而與第二半導體層202電性連接。第三接合墊110c與第一接合墊110a及第二接合墊110b之間皆為電性絕緣。第一接合墊110a、第二接合墊110b與第三接合墊110c可具有相同材料或不同材料,例如,第一接合墊110a、第二接合墊110b與第三接合墊110c之材料可選自金(Au)、銅(Cu)、鉻(Cr)、鎳(Ni)、鈷(Co)、鐵(Fe)、鈦(Ti)、鎢(W)、鋯(Zr)、鉬(Mo)、鉭(Ta)、鋁(Al)、銀(Ag)、鉑(Pt)、鈀(Pd)、銠(Rh)、銥(Ir)、釕(Ru)、鋨(Os)或上述材料的單層、合金或多層膜。The light-emitting diode 10 has a first bonding pad 110a, a second bonding pad 110b, and a third bonding pad 110c respectively disposed on the second insulating layer 60, which are spatially separated from each other. In the embodiment of the present application, the third bonding pad 110c is located between the first bonding pad 110a and the second bonding pad 110b. There is a gap between the third bonding pad 110c and the first bonding pad 110a, and between the third bonding pad 110c and the second bonding pad 110b. The second insulating layer opening 601 of the first group of the first bonding pads 110a filled in the second insulating layer 60 is connected to the contact layer 50, and is electrically connected to the first semiconductor layer 201. The second bonding pad 110b of the second bonding pad 110b is filled in the second insulating layer 60 of the second insulating layer 60, and the second bonding pad 110b is electrically connected to the second semiconductor layer 202. The third bonding pad 110c is electrically insulated from the first bonding pad 110a and the second bonding pad 110b. The first bonding pad 110a, the second bonding pad 110b, and the third bonding pad 110c may have the same material or different materials. For example, the materials of the first bonding pad 110a, the second bonding pad 110b, and the third bonding pad 110c may be selected from gold. (Au), copper (Cu), chromium (Cr), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os) or a single layer of the above materials, Alloy or multilayer film.
支持基板100具有一第一表面101與一相對於第一表面101之第二表面102,第一表面101與發光二極體10接合,一絕緣黏結材料80位於支持基板100與發光二極體10之間。在本實施例中,支持基板100為非導電材料,包含但不限於氮化鋁(AlN)、鑽石、藍寶石(sapphire)、玻璃、陶瓷以及高分子複合材料(polymer matrix composite, PMC)等。第一表面101設置有一第一接觸墊120a、一第二接觸墊120b、以及一第三接觸墊130,分別位於相對於發光二極體10之第一接合墊110a、第三接合墊110c與第二接合墊110b的位置上。於一實施例中,第一接觸墊120a、第二接觸墊120b與第三接觸墊130之表面可分別具有複數個金屬凸塊32,複數個金屬凸塊32穿過其間的絕緣黏結材料80,與其對應的接合墊接觸並達成接合。於本申請案之一實施例中,第一接合墊110a、第三接合墊110c與第二接合墊110b之表面可分別具有複數個金屬凸塊,與複數個金屬凸塊32同樣具有穿過其間的絕緣黏結材料80,與其對應的接觸墊接觸並達成接合。此外,絕緣黏結材料80亦設置於相鄰的接合墊110a-110c之間,與相鄰的第一接觸墊120a、第二接觸墊120b與第三接觸墊130之間,如此一來,可確保各接合墊110a-110c之間與第一接觸墊120a、第二接觸墊120b與第三接觸墊130之間的絕緣性,防止發光二極體10發生短路。絕緣黏結材料80包含有機材料,例如Su8、苯并環丁烯(BCB)、過氟環丁烷(PFCB)、環氧樹脂(Epoxy)、丙烯酸樹脂(Acrylic Resin)、環烯烴聚合物(COC)、聚甲基丙烯酸甲酯(PMMA)、聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚醚醯亞胺(Polyetherimide)、氟碳聚合物(Fluorocarbon Polymer),或是無機材料,例如矽膠(Silicone)、玻璃(Glass),或是介電材料,例如氧化鋁(Al2O3)、氮化矽(SiNx)、氧化矽(SiOx)、氧化鈦(TiOx),或氟化鎂(MgFx)等。第三接觸墊130具有一第一區域130a直接接觸發光二極體10之第二接合墊110b,亦即,於上視圖中,第三接觸墊130之第一區域130a位於發光二極體10之投影面積內,用以與發光二極體10接合;此外,第三接觸墊130具有一第二區域130b,由第一區域130a延伸至發光二極體10之投影面積外,第二區域130b在後續製程中可用於對外接合之打線區域,將打線點(圖未示)設置於第二區域130b上。在此不限於以打線方式對外接合方式,其他習知的對外接合方式也可作為本申請案一實施方式,例如以黃光顯影製程佈導線對外連接。The support substrate 100 has a first surface 101 and a second surface 102 opposite to the first surface 101. The first surface 101 is bonded to the LED assembly 10. An insulating bonding material 80 is disposed on the support substrate 100 and the LED assembly 10. between. In the present embodiment, the support substrate 100 is a non-conductive material, including but not limited to aluminum nitride (AlN), diamond, sapphire, glass, ceramic, and polymer matrix composite (PMC). The first surface 101 is provided with a first contact pad 120a, a second contact pad 120b, and a third contact pad 130 respectively located on the first bonding pad 110a and the third bonding pad 110c and the first electrode relative to the LED body 10. The position of the two bonding pads 110b. In one embodiment, the surfaces of the first contact pad 120a, the second contact pad 120b, and the third contact pad 130 may respectively have a plurality of metal bumps 32, and the plurality of metal bumps 32 pass through the insulating bonding material 80 therebetween. Contact with the corresponding bonding pad and achieve bonding. In one embodiment of the present application, the surfaces of the first bonding pad 110a, the third bonding pad 110c, and the second bonding pad 110b may respectively have a plurality of metal bumps, and have a plurality of metal bumps 32 therethrough. The insulating bonding material 80 contacts and contacts the corresponding contact pads. In addition, the insulating bonding material 80 is also disposed between the adjacent bonding pads 110a-110c, and between the adjacent first contact pads 120a, the second contact pads 120b and the third contact pads 130, thereby ensuring The insulation between the bonding pads 110a-110c and the first contact pads 120a, the second contact pads 120b and the third contact pads 130 prevents the light-emitting diodes 10 from being short-circuited. The insulating bonding material 80 comprises an organic material such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC). , polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer (Fluorocarbon Polymer), or Inorganic materials such as Silicone, Glass, or dielectric materials such as alumina (Al2O3), tantalum nitride (SiNx), yttrium oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx) and so on. The third contact pad 130 has a first region 130a directly contacting the second bonding pad 110b of the LED body 10. That is, in the upper view, the first region 130a of the third contact pad 130 is located in the LED body 10. The third contact pad 130 has a second region 130b extending from the first region 130a to the projected area of the light-emitting diode 10, and the second region 130b is in the projected area. In the subsequent process, the wire bonding area can be used for external bonding, and a wire bonding point (not shown) is disposed on the second region 130b. The present invention is not limited to the external bonding method by wire bonding, and other conventional external bonding methods can also be used as an embodiment of the present application, for example, the yellow light developing process wiring is externally connected.
在第一接觸墊120a與第二接觸墊120b下方的支持基板100中,各具有貫穿於支持基板100的一第一群組通孔36a以及一第二群組通孔36b,第一群組通孔36a及第二群組通孔36b由第一表面101延伸至第二表面102。第一群組通孔36a內填充導電材料,第二群組通孔36b內填充導熱材料,也可以是絕緣導熱材料,因此第一群組通孔36a與第二群組通孔36b分別形成導電通導與導熱通道。第一群組通孔36a與第二群組通孔36b之形狀,由上視觀之可為圓形、矩形、環形或其他形狀。第一群組通孔36a與第二群組通孔36b的數量可為單個或多個,其配置與分佈可依第一接合墊110a、第三接合墊 110c之設置以及導熱與導電之目的而有不同設計。Each of the support substrate 100 under the first contact pad 120a and the second contact pad 120b has a first group through hole 36a and a second group through hole 36b extending through the support substrate 100. The aperture 36a and the second group of vias 36b extend from the first surface 101 to the second surface 102. The first group of through holes 36a are filled with a conductive material, and the second group of through holes 36b are filled with a heat conductive material, which may also be an insulating and heat conductive material, so that the first group of through holes 36a and the second group of through holes 36b respectively form a conductive Conduction and heat conduction channels. The shape of the first group of through holes 36a and the second group of through holes 36b may be circular, rectangular, circular or other shapes as viewed from above. The number of the first group of through holes 36a and the second group of through holes 36b may be single or multiple, and the configuration and distribution may be according to the arrangement of the first bonding pads 110a, the third bonding pads 110c, and the purpose of heat conduction and conduction. There are different designs.
第二表面102設有一導電墊200以及一導熱墊300,分別對應連接第一群組通孔36a與第二群組通孔36b。導電墊200藉由第一群組通孔36a、第一接觸墊120a以及第一接合墊110a與發光二極體10之第一半導體層201達成電性連接。如此一來,發光二極體10的第一半導體層201與第二半導體層202可分別透過導電墊200與第三接觸墊130跟外部電源或電子元件電性連接。發光二極體10所產生的熱,可藉由第三接合墊110c、第二接觸墊120b、第二群組通孔36b以及導熱墊300傳導至發光元件1外部,增加發光元件1之散熱效果。如第1C圖所示,於本申請案另一實施例中,支持基板100之第二表面102可接合於一散熱基板66,散熱基板66可包含金屬材料,其與支持基板100之接合面上具有一第三絕緣層62、一金屬層64a設置於第三絕緣層62上,以及另一金屬層64b直接設置於散熱基板66上。導電墊200與金屬層64a接合,導熱墊300與金屬層64b接合。於另一實施例中,金屬層64b可替換為導熱膠材。於另一實施例中,於打線製程時可將第一打線點56a形成於金屬層64a上,第二打線點56b設置於第三接觸墊130上。The second surface 102 is provided with a conductive pad 200 and a thermal pad 300 respectively connected to the first group through hole 36a and the second group through hole 36b. The conductive pad 200 is electrically connected to the first semiconductor layer 201 of the light emitting diode 10 by the first group via hole 36a, the first contact pad 120a, and the first bonding pad 110a. As a result, the first semiconductor layer 201 and the second semiconductor layer 202 of the LED 10 can be electrically connected to the external power source or the electronic component through the conductive pad 200 and the third contact pad 130, respectively. The heat generated by the LEDs 10 can be conducted to the outside of the light-emitting element 1 by the third bonding pads 110c, the second contact pads 120b, the second group vias 36b, and the thermal pad 300, thereby increasing the heat dissipation effect of the light-emitting elements 1. . As shown in FIG. 1C , in another embodiment of the present application, the second surface 102 of the support substrate 100 can be bonded to a heat dissipation substrate 66 , and the heat dissipation substrate 66 can include a metal material on the interface surface of the support substrate 100 . A third insulating layer 62, a metal layer 64a are disposed on the third insulating layer 62, and another metal layer 64b is disposed directly on the heat dissipation substrate 66. The conductive pad 200 is bonded to the metal layer 64a, and the thermal pad 300 is bonded to the metal layer 64b. In another embodiment, the metal layer 64b can be replaced with a thermally conductive adhesive. In another embodiment, the first wire bonding point 56a may be formed on the metal layer 64a during the wire bonding process, and the second wire bonding point 56b may be disposed on the third contact pad 130.
第2圖為依據本申請案之發光元件2之一實施例截面圖。如第2圖所示,發光元件2包含發光二極體10以覆晶方式接合於一支持基板100之第一表面101。本實施例中發光二極體10與支持基板100之結構與前述實施例第1B圖相同,因此不再贅述。而本實施例與前述實施例差異在於發光二極體10與支持基板100之接合方式,如第2圖所示,第一接觸墊120a與發光二極體10之第二接合墊110b接合,第二接觸墊120b與發光二極體10之第三接合墊110c接合,第三接觸墊130與發光二極體10之第一接合墊110a接合。導電墊200藉由第一群組通孔36a、第一接觸墊120a以及第二接合墊110b與發光二極體10之第二半導體層202達成電性連接;第三接觸墊130經由第一接合墊110a與第一半導體層201電性連接。如此一來,發光二極體10的第一半導體層201與第二半導體層202可分別透過第三接觸墊130與導電墊200跟外部電源或電子元件連接。發光二極體10所產生的熱,可藉由第三接合墊110c、第二接觸墊120b、第二群組通孔36b以及導熱墊300傳遞至發光元件2外部,增加發光元件2之散熱效果。同樣地,於本申請案另一實施例中,發光元件2的導電墊200與導熱墊300可接合於一散熱基板(圖未示)。Fig. 2 is a cross-sectional view showing an embodiment of a light-emitting element 2 according to the present application. As shown in FIG. 2, the light-emitting element 2 includes the light-emitting diode 10 bonded to the first surface 101 of a support substrate 100 in a flip-chip manner. The structure of the light-emitting diode 10 and the support substrate 100 in this embodiment is the same as that of the first embodiment, and therefore will not be described again. The difference between this embodiment and the foregoing embodiment is the manner in which the LEDs 10 and the support substrate 100 are bonded. As shown in FIG. 2, the first contact pads 120a are bonded to the second bonding pads 110b of the LEDs 10. The two contact pads 120b are bonded to the third bonding pads 110c of the LEDs 10, and the third contact pads 130 are bonded to the first bonding pads 110a of the LEDs 10. The conductive pad 200 is electrically connected to the second semiconductor layer 202 of the LED 10 by the first group via 36a, the first contact pad 120a and the second bonding pad 110b; the third contact pad 130 is connected via the first bonding The pad 110a is electrically connected to the first semiconductor layer 201. As a result, the first semiconductor layer 201 and the second semiconductor layer 202 of the LED 10 can be connected to the external power source or electronic component through the third contact pad 130 and the conductive pad 200, respectively. The heat generated by the LEDs 10 can be transmitted to the outside of the light-emitting element 2 through the third bonding pads 110c, the second contact pads 120b, the second group vias 36b, and the thermal pad 300, thereby increasing the heat dissipation effect of the light-emitting elements 2. . Similarly, in another embodiment of the present application, the conductive pad 200 of the light-emitting element 2 and the thermal pad 300 can be bonded to a heat-dissipating substrate (not shown).
由第1B圖的發光元件1與第2圖的發光元件2可知,第一接合墊110a與第二接合墊110b其中之一可經由第一接觸墊120a連接至支持基板100的第一群組通孔30a(即導電通道),第三接合墊110c經由第二接觸墊120b連接至支持基板100的第二群組通孔30b(即導熱通道),第一接合墊110a與第二接合墊110b其中另一與支持基板100的第三接觸墊130接合。因為第三接合墊110c與第一半導體層201和第二半導體層202皆為電性絕緣,第一半導體層201和第二半導體層202分別藉由導電墊200與第三接觸墊130與外部電源或外部電子元件作連接,導熱墊300與導電墊200之間,以及導熱墊300與第三接觸墊130之間皆為電性絕緣,所以在導熱墊300與散熱基板66的接合面無須額外設置絕緣結構,使散熱途徑更為直接,更可簡化散熱基板之電路設計。此外,由於第三接觸墊130設置於第一表面101上,第二表面102上除了導電墊200的設置面積以外,有更多的面積可以將導熱墊300形成於其上方,以增加散熱面積。It can be seen from the light-emitting element 1 of FIG. 1B and the light-emitting element 2 of FIG. 2 that one of the first bonding pad 110a and the second bonding pad 110b can be connected to the first group of the supporting substrate 100 via the first contact pad 120a. The hole 30a (ie, the conductive path), the third bonding pad 110c is connected to the second group through hole 30b (ie, the heat conduction channel) of the support substrate 100 via the second contact pad 120b, the first bonding pad 110a and the second bonding pad 110b The other is joined to the third contact pad 130 of the support substrate 100. Because the third bonding pad 110c is electrically insulated from the first semiconductor layer 201 and the second semiconductor layer 202, the first semiconductor layer 201 and the second semiconductor layer 202 are respectively connected to the external power supply by the conductive pad 200 and the third contact pad 130. Or the external electronic component is connected, the thermal pad 300 and the conductive pad 200, and the thermal pad 300 and the third contact pad 130 are electrically insulated, so no additional arrangement is needed on the bonding surface of the thermal pad 300 and the heat dissipation substrate 66. The insulating structure makes the heat dissipation path more direct and simplifies the circuit design of the heat dissipation substrate. In addition, since the third contact pad 130 is disposed on the first surface 101, in addition to the disposed area of the conductive pad 200 on the second surface 102, there is more area on which the thermal pad 300 can be formed to increase the heat dissipation area.
於上述實施例中,第一接合墊110a、第二接合墊110b以及第三接合墊110c為多邊形或矩形,然而,各接合墊之面積、形狀與配置並不限於此。例如,各接合墊亦可具有弧狀。於本申請案一實施例中,導熱墊300之面積可大於導電墊200之面積;於本申請案另一實施例中,導熱墊300之面積可大於第二接觸墊120b與第三接觸墊130之面積和;於本申請案另一實施例中,於上視圖中,導熱墊300的投影面積重疊於第二接觸墊120b的投影面積及/或第三接觸墊130的投影面積。In the above embodiment, the first bonding pad 110a, the second bonding pad 110b, and the third bonding pad 110c are polygonal or rectangular. However, the area, shape, and arrangement of the bonding pads are not limited thereto. For example, each of the bonding pads may also have an arc shape. In an embodiment of the present application, the area of the thermal pad 300 may be larger than the area of the conductive pad 200. In another embodiment of the present application, the area of the thermal pad 300 may be larger than the second contact pad 120b and the third contact pad 130. In another embodiment of the present application, in a top view, the projected area of the thermal pad 300 overlaps the projected area of the second contact pad 120b and/or the projected area of the third contact pad 130.
第3A圖為依據本申請案之發光元件3之一實施例截面圖。如第3A圖所示,發光元件3包含發光二極體10以覆晶方式接合於一支持基板100’之第一表面101,支持基板100’可為非導電材料。本實施例中發光二極體10之結構與前述實施例相同,因此不再贅述。而本實施例與前述實施例差異在於,支持基板100’之第一表面101上設置有一第一接觸墊140a、一第二接觸墊140b、以及一第三接觸墊120。第一接觸墊140a與第一接合墊110a接合,第二接觸墊140b與第二接合墊110b接合,第三接觸墊120與第三接合墊110c接合。第三接觸墊120下方的支持基板100’中具有通孔36’,通孔36’內填充有導熱材料,與支持基板100’第二表面102之一導熱墊300相連接。與前述實施例第1B圖類似,第一接觸墊140a與第二接觸墊140b具有一區域位於發光二極體10之投影範圍外,此區域在後續製程中可用於打線,例如將打線點(圖未示)設置在此區域上,發光二極體10的第一半導體層201與第二半導體層202可分別透過第一接觸墊140a與第二接觸墊140b跟外部電源或電子元件連接。如此一來,在支持基板100’之第二表面102上不需要另外設置導電墊,導熱墊300 可覆蓋整個第二表面102,增加散熱面積。Fig. 3A is a cross-sectional view showing an embodiment of a light-emitting element 3 according to the present application. As shown in Fig. 3A, the light-emitting element 3 includes a light-emitting diode 10 bonded to the first surface 101 of a support substrate 100' in a flip-chip manner, and the support substrate 100' may be a non-conductive material. The structure of the light-emitting diode 10 in this embodiment is the same as that of the foregoing embodiment, and therefore will not be described again. The difference between the embodiment and the foregoing embodiment is that the first surface 101 of the support substrate 100' is provided with a first contact pad 140a, a second contact pad 140b, and a third contact pad 120. The first contact pad 140a is bonded to the first bonding pad 110a, the second contact pad 140b is bonded to the second bonding pad 110b, and the third contact pad 120 is bonded to the third bonding pad 110c. The support substrate 100' under the third contact pad 120 has a through hole 36' which is filled with a heat conductive material and is connected to the thermal pad 300 of the second surface 102 of the support substrate 100'. Similar to the first embodiment, the first contact pad 140a and the second contact pad 140b have an area outside the projection range of the light-emitting diode 10, and this area can be used for wire bonding in a subsequent process, for example, a wire-bonding point (Fig. The first semiconductor layer 201 and the second semiconductor layer 202 of the LED 10 can be connected to an external power source or electronic component through the first contact pad 140a and the second contact pad 140b, respectively. As a result, no additional conductive pads are required on the second surface 102 of the support substrate 100', and the thermal pad 300 can cover the entire second surface 102 to increase the heat dissipation area.
於本申請案另一實施例中,可將第3A圖發光元件3接合於散熱基板66上,如第3B圖所示。散熱基板66可包含金屬材料,其與支持基板100’之接合面上具有金屬層64直接設置於散熱基板66上,導熱墊300與金屬層64接合。於另一實施例中,金屬層64b可替換為導熱膠材。於另一實施例中,於打線製程時可將第一打線點56a形成於第一接觸墊140a上,第二打線點形成於第二接觸墊140b上。如前面實施例所述,第三接合墊110c與第一及第二接合墊110a及110b皆為電性絕緣,因此導熱墊300與發光二極體10亦為電性絕緣。當發光元件3接合於散熱基板66時,兩者之間的接合面無需設置其他絕緣結構,可藉由金屬層64(或導熱膠材)直接將發光元件3所產生的熱直接傳遞至散熱基板66。此外,散熱基板66表面無需設置其他電路連接結構,因此無需考量發光元件3與散熱基板66在接合時兩者之間的對位精準,可簡化散熱基板66之結構並簡化製程。In another embodiment of the present application, the light-emitting element 3 of FIG. 3A can be bonded to the heat dissipation substrate 66 as shown in FIG. 3B. The heat dissipation substrate 66 may include a metal material having a metal layer 64 disposed directly on the heat dissipation substrate 66 on the bonding surface of the support substrate 100', and the thermal pad 300 is bonded to the metal layer 64. In another embodiment, the metal layer 64b can be replaced with a thermally conductive adhesive. In another embodiment, the first wire bonding point 56a may be formed on the first contact pad 140a during the wire bonding process, and the second wire bonding point is formed on the second contact pad 140b. As described in the previous embodiment, the third bonding pad 110c and the first and second bonding pads 110a and 110b are electrically insulated, and thus the thermal pad 300 and the LED 10 are also electrically insulated. When the light-emitting element 3 is bonded to the heat-dissipating substrate 66, the bonding surface between the two does not need to be provided with another insulating structure, and the heat generated by the light-emitting element 3 can be directly transmitted to the heat-dissipating substrate by the metal layer 64 (or the thermal conductive adhesive). 66. In addition, the surface of the heat dissipation substrate 66 does not need to be provided with other circuit connection structures. Therefore, it is not necessary to consider the alignment accuracy between the light-emitting element 3 and the heat dissipation substrate 66 when bonding, and the structure of the heat dissipation substrate 66 can be simplified and the process can be simplified.
惟上述實施例僅為例示性說明本申請案之原理及其功效,而非用於限制本申請案。任何本申請案所屬技術領域中具有通常知識者均可在不違背本申請案之技術原理及精神的情況下,對上述實施例進行修改及變化。因此本申請案之權利保護範圍如後述之申請專利範圍所列。However, the above embodiments are merely illustrative of the principles and effects of the present application, and are not intended to limit the present application. Modifications and variations of the above-described embodiments can be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present application is as set forth in the scope of the patent application described below.
1、2、3‧‧‧發光元件1, 2, 3‧‧‧Lighting elements
10‧‧‧發光二極體10‧‧‧Lighting diode
100、100’‧‧‧支持基板100,100'‧‧‧Support substrate
101‧‧‧第一表面101‧‧‧ first surface
102‧‧‧第二表面102‧‧‧ second surface
110a‧‧‧第一接合墊110a‧‧‧First joint pad
110b‧‧‧第二接合墊110b‧‧‧Second joint pad
110c‧‧‧第三接合墊110c‧‧‧ third joint pad
120a、140a‧‧‧第一接觸墊120a, 140a‧‧‧ first contact pads
120b、140b‧‧‧第二接觸墊120b, 140b‧‧‧second contact pad
120、130‧‧‧第三接觸墊120, 130‧‧‧ third contact pad
130a‧‧‧第一區域130a‧‧‧First area
130b‧‧‧第二區域130b‧‧‧Second area
20‧‧‧半導體疊層20‧‧‧Semiconductor laminate
201‧‧‧第一半導體層201‧‧‧First semiconductor layer
202‧‧‧第二半導體層202‧‧‧Second semiconductor layer
203‧‧‧活性層203‧‧‧Active layer
16‧‧‧反射結構16‧‧‧Reflective structure
18‧‧‧電流分散層18‧‧‧current dispersion layer
30a‧‧‧第一暴露區30a‧‧‧First exposed area
30b‧‧‧第二暴露區30b‧‧‧Second exposed area
32‧‧‧金屬凸塊32‧‧‧Metal bumps
36’‧‧‧通孔36’‧‧‧through hole
36a‧‧‧第一群組通孔36a‧‧‧First group of through holes
36b‧‧‧第二群組通孔36b‧‧‧Second group of through holes
40‧‧‧第一絕緣層40‧‧‧First insulation
401‧‧‧第一群組的第一絕緣層開口401‧‧‧First insulation opening of the first group
402‧‧‧第二群組的第一絕緣層開口402‧‧‧Second insulation opening of the second group
50‧‧‧接觸層50‧‧‧Contact layer
501‧‧‧接觸層開口501‧‧‧Contact opening
60‧‧‧第二絕緣層60‧‧‧Second insulation
601‧‧‧第一群組的第二絕緣層開口601‧‧‧Second insulation opening of the first group
602‧‧‧第二群組的第二絕緣層開口602‧‧‧Second insulation opening of the second group
200‧‧‧導電墊200‧‧‧Electrical mat
300、300’‧‧‧導熱墊300, 300'‧‧‧ Thermal pad
56a、56b‧‧‧第一打線點、第二打線點56a, 56b‧‧‧ first line and second line
62‧‧‧第三絕緣層62‧‧‧The third insulation layer
64、64a、64b‧‧‧金屬層64, 64a, 64b‧‧‧ metal layer
第1A圖為本申請案一實施例之發光二極體上視圖。FIG. 1A is a top view of a light emitting diode according to an embodiment of the present application.
第1B圖為本申請案一實施例之發光元件截面圖。Fig. 1B is a cross-sectional view showing a light-emitting element of an embodiment of the present application.
第1C圖為本申請案另一實施例之發光元件截面圖。Fig. 1C is a cross-sectional view showing a light-emitting element of another embodiment of the present application.
第2圖為為本申請案另一實施例之發光元件截面圖。Fig. 2 is a cross-sectional view showing a light-emitting element of another embodiment of the present application.
第3A圖為為本申請案另一實施例之發光元件截面圖。Fig. 3A is a cross-sectional view showing a light-emitting element of another embodiment of the present application.
第3B圖為為本申請案另一實施例之發光元件截面圖。Fig. 3B is a cross-sectional view showing a light-emitting element of another embodiment of the present application.
Claims (10)
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TW201537782A (en) * | 2014-03-27 | 2015-10-01 | Seoul Viosys Co Ltd | Light-emitting diode and light-emitting device |
TW201541569A (en) * | 2014-04-16 | 2015-11-01 | Viking Tech Corp | Electronic package structure and ceramic substrate thereof |
TWM517424U (en) * | 2014-07-18 | 2016-02-11 | 首爾偉傲世有限公司 | Light-emitting diode, light-emitting device |
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TW201537782A (en) * | 2014-03-27 | 2015-10-01 | Seoul Viosys Co Ltd | Light-emitting diode and light-emitting device |
TW201541569A (en) * | 2014-04-16 | 2015-11-01 | Viking Tech Corp | Electronic package structure and ceramic substrate thereof |
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