TWI618253B - Microelectronic structure and method of forming same - Google Patents

Abstract

The invention discloses a microelectronic structure and a method for forming the same. The method for forming a microelectronic structure includes forming a graphene layer in situ on a substrate. The graphene layer includes at least one graphene structure and has an energy gap greater than 300 meV to form a first insulating layer to make graphene. A first insulating layer is formed between the layer and the substrate, a second insulating layer is formed on the graphene layer, and a first electrode, a second electrode, and a third electrode are formed on the second insulating layer, so that the first The electrode and the second electrode directly contact both ends of the graphene layer, and the third electrode and the graphene layer are separated by a second insulating layer. The thus obtained microelectronic structure can be improved by applying a high energy gap graphene material.

Description

Microelectronic structure and its forming method

The invention relates to the field of microelectronics manufacturing, in particular to a microelectronic structure and a method for forming the same.

At present, in the field of microelectronics manufacturing, more and more attention is paid to the application of graphene, with a view to applying graphene with low resistivity and light and thin structure to it, which will help improve the electronic movement speed and miniaturization of microelectronic components. In the prior art, the use of graphene to make microelectronic components has developed rapidly, and several models have been proposed. First, please refer to the structure diagram shown in FIG. 1. The metal oxide half field effect transistor (MOSFET) 1 is a graphene layer 140 fabricated on a silicon substrate 120 as a channel layer connected between a source 160 and a drain 150. The silicon dioxide layer 130 serves as an insulating layer, and the back gate 110 controls the electron flow in the channel layer. Although such a metal-oxide half field-effect transistor can be made through current manufacturing processes, it has excessive parasitic capacitance and cannot be integrated with other components, so it cannot meet the needs of industrial manufacturing.

Please also refer to FIG. 2 and FIG. 3, wherein the metal-oxide-semiconductor field-effect transistor 2 of FIG. 2 is doped with a rear surface of a silicon substrate 220 covered with silicon dioxide 230 to form a rear gate 210. The front surface is chemically stripped ( chemical exfoliation method) or a graphene layer 240 is formed on nickel, copper and other metals. The metal-oxide half field effect transistor 3 of FIG. 3 is a graphene layer 330 formed on a silicon carbide substrate 310 by an epitaxial growth technique. And oxidize to form a silicon dioxide layer 320. Then, make the upper gate The edge layer and the upper gate 270, and whether the source electrodes 260, 350 and the drain electrodes 250, 340 are conductive are controlled by the upper gate 270, 360. However, due to the insufficient energy gap of the graphene layers 240 and 330 in the metal-oxide half-field-effect transistors 2 and 3 in the form of an upper gate, the channel cannot be cut off after the channel is turned on, and the important function of the metal-oxide half-field-effect transistors is lost.

Therefore, there is a great need for the development and application of microelectronic structures in which graphene exhibits good element functions and meets the needs of industrial production.

The object of the present invention is to provide a novel microelectronic structure and a method for forming the same, which apply the superior superconducting properties of graphene to the microelectronic structure and improve the electronic characteristics of the microelectronic structure.

According to one aspect of the present invention, a microelectronic structure is provided, including: a substrate on which a graphene layer, a first electrode, a second electrode, and a third electrode are formed, wherein the first electrode and the second electrode The graphene layer is directly in contact with both ends of the graphene layer, a first insulating layer is spaced between the graphene layer and the substrate, a second insulating layer is spaced between the third electrode and the graphene layer, and the graphene layer has a Energy gap.

According to another aspect of the present invention, a method for forming a microelectronic structure is provided. The method includes: forming a graphene layer in-situ on a substrate. The graphene layer includes at least one graphene structure and has a size greater than An energy gap of 300meV; forming a first insulating layer so that the graphene layer and the substrate are separated by the first insulating layer; forming a second insulating layer on the graphene layer; and forming a first on the second insulating layer The electrode, a second electrode and a third electrode make the first electrode and the second electrode directly contact both ends of the graphene layer, and the third electrode and the graphene layer are separated by a second insulating layer.

The present invention may be selectively changed, and examples are not limited here: the substrate may selectively use any substrate, such as a microelectronic substrate; the graphene layer may optionally include any number of layers of graphene, and here one layer is used as For example, the first insulating layer and the second insulating layer may be formed by selectively using an oxide of a substrate material or a high-dielectric film. Preferably, the first insulating layer may be oxidized by passing oxygen through a graphene layer. The second insulating layer is a high-dielectric thin film; the first electrode, the second electrode, and the third electrode may optionally be metal electrodes. For example, if the formed microelectronic structure is a double-gate field-effect transistor, the first electrode, the second electrode, and the third electrode may be a source electrode, a drain electrode, and a first gate electrode, respectively, and the substrate may be Second gate.

Second, the method for forming a microelectronic structure provided by the present invention may further include a cleaning step before the graphene layer is formed in situ, and the cleaning step cleans a surface of the substrate on which the graphene layer is to be formed in situ. For example, the cleaning step can be achieved by using ozone cleaning or a SiCoNi pre-cleaning treatment, and there is no limitation here.

Compared with the prior art, the present invention provides a novel microelectronic structure and a method for forming the same by applying a graphene material therein and increasing the energy gap of the graphene material, thereby greatly improving the electronic characteristics of the microelectronic structure. During the manufacturing process, an appropriate cleaning process is selectively added to produce a graphene layer with the same size and shape, so as to meet the needs of mass production of microelectronic structures.

1‧‧‧ Metal Oxide Half Field Effect Transistor

110‧‧‧ rear gate

120‧‧‧ Silicon substrate 120

130‧‧‧ Silicon dioxide layer

140‧‧‧graphene layer 140

150‧‧‧ Drain

160‧‧‧Source 160

2‧‧‧ Metal Oxide Half Field Effect Transistor

210‧‧‧ rear gate

220‧‧‧Silicon wafer 220

230‧‧‧ Silicon dioxide

240‧‧‧graphene layer

250‧‧‧ Drain

260‧‧‧Source

270‧‧‧ Upper gate

3‧‧‧ Metal Oxide Half Field Effect Transistor

310‧‧‧ SiC substrate

320‧‧‧ Silicon dioxide layer

330‧‧‧graphene layer

340‧‧‧Drain

350‧‧‧Source

360‧‧‧ Upper gate

4‧‧‧Microelectronic Structure

410‧‧‧ substrate

420‧‧‧first insulating layer

430‧‧‧graphene layer

440‧‧‧Second electrode

450‧‧‧first electrode

460‧‧‧Second insulation layer

470‧‧‧Third electrode

S100, S200, S300, S400, S500 ‧‧‧ steps

The accompanying drawings of the present invention are described as follows: FIGS. 1 to 3 are schematic structural diagrams of microelectronic structures in the prior art; FIG. 4 is a structural schematic diagram of microelectronic structures according to an embodiment of the present invention; Another structural schematic diagram of the microelectronic structure of the embodiment; FIG. 6 to FIG. 9 are structural diagrams of the microelectronic structure during the formation process according to an embodiment of the present invention Intent; FIG. 10 is a flowchart of a method for forming a microelectronic structure according to an embodiment of the present invention.

The microelectronic structure of the present invention and the method for forming the same will be described in more detail with reference to the schematic diagrams, which show the preferred embodiments of the present invention. It should be understood that those skilled in the art can modify the invention described herein while still realizing the invention. Beneficial effects. Therefore, the following description should be understood as widely known to those skilled in the art, and not as a limitation on the present invention.

The invention is described in more detail by way of example in the following paragraphs with reference to the drawings. The advantages and features of the invention will be apparent from the following description and claims. It should be noted that the drawings are in a very simplified form and all use inaccurate proportions, which are only used to facilitate and clearly assist the description of the embodiments of the present invention.

The core idea of the present invention is to provide a microelectronic structure and a method for forming the same. The method includes: forming a graphene layer in-situ on a substrate, the graphene layer including at least one graphene structure and having an energy gap greater than 300 meV; forming a first insulating layer to make graphene A first insulating layer is spaced between the layer and the substrate; a second insulating layer is formed on the graphene layer; and a first electrode, a second electrode, and a third electrode are formed on the second insulating layer, so that the first The electrode and the second electrode directly contact both ends of the graphene layer, and the third electrode and the graphene layer are separated by a second insulating layer. Therefore, the application of graphene material in the microelectronic structure improves the electronic characteristics of the device.

Next, please refer to FIG. 4 and FIG. 5 for a detailed description of the microelectronic structure of the present invention and a method for forming the same. The microelectronic structure shown here is based on a double-gate field effect transistor as an example. However, the present invention is not limited to the specific structure shown in FIG. 4 or FIG. 5. FIG. 10 is a flowchart of a method for forming a microelectronic structure according to the present invention; and FIGS. 5 to 9 are schematic diagrams of the structure of a microelectronic structure according to the present invention during the formation process.

Please refer to FIG. 4 in combination with FIG. 10. The method for forming the microelectronic structure 4 includes: first, before step S200, a graphene layer 430 is formed in situ on a substrate 410, and then a cleaning step is selectively performed. S100, a surface of the graphene layer 430 is formed in situ on the cleaning substrate 410. Preferably, in the present invention, the cleaning step S100 is performed by ozone cleaning, SiCoNi pre-cleaning treatment, or the like. Next, in step S200, as shown in FIG. 6, a graphene layer 430 is formed in-situ on the substrate 410. The graphene layer 430 includes at least one graphene structure and has an energy gap greater than 300 meV. The substrate 410 used here is exemplified by a silicon substrate, and the graphene layer 430 is exemplified by a large-area extended graphene structure formed by in-situ polymerization, which may include one or more graphene structures. The layer 430 and the substrate 410 are not limited to a film layer including other materials. Since the cleaning step S100 has been performed before the graphene layer 430 is formed, it is helpful to control the uniformity of the shape and the boundary of the graphene layer 430 to produce a graphene layer of a size and shape that meets requirements.

After this step, in step S300, as shown in FIG. 7, a first insulating layer 420 is formed by oxidation, so that the graphene layer 430 and the substrate 410 are separated by the first insulating layer 420. In this example, the first insulating layer 420 is formed by making the structure shown in FIG. 6 into an environment containing oxygen, passing oxygen through the graphene layer 430, and oxidizing the substrate 410. In this example, oxygen oxidizes the silicon substrate 410 to silicon dioxide to form a first insulating layer 420.

Next, as shown in FIG. 8, step S400 is performed to form a second insulating layer 460 on the graphene layer 430. Specifically, the second insulating layer 460 may be any high-dielectric film formed by any film forming technology. Such as hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), alumina (Al ₂ O ₃ ), titanium dioxide (TiO ₂ ) and tantalum pentoxide (Ta ₂ O ₅ ), and hafnium dioxide is preferred Here, a hafnium dioxide formed by an atomic layer deposition (ALD) process is used as an example.

Then, referring to FIG. 9, step S500 is performed to form a first electrode 450, a second electrode 440, and a third electrode 470 on the second insulating layer 460, so that the first electrode 450 and the second electrode 440 directly contact the graphite. At both ends of the olefin layer 430, the third electrode 470 and the graphene layer 430 are separated by a second insulating layer 460. Specifically, before this step, the second insulating layer 460 may be patterned. For example, the pattern of the second insulating layer 460 is defined by lithography and etching steps, and then the first electrode 450, the second electrode 440, and the first electrode Three electrodes 470. There can be various variations in the method of making the first electrode 450, the second electrode 440, and the third electrode 470, such as forming a metal layer by metal sputtering, atomic layer deposition, or other thin film forming methods, such as aluminum, copper, nickel, titanium, Tungsten, silver, gold, etc., and cover the area other than the place to be etched through a photoresist, and the process is completed by wet etching to remove the first electrode 450, the second electrode 440, and the third electrode 470. Or by grinding. Since the microelectronic structure 4 in this example is a double-gate field-effect transistor, the first electrode 450 is used as a source, the second electrode 440 is used as a drain, and the third electrode 470 is used as a first gate. As the upper gate, the substrate 410 is used as the second gate, such as the rear gate. Therefore, the microelectronic structure 4 has the upper gate and the back gate to control the conduction of the channels therein. The presence of the upper gate can greatly reduce the parasitic capacitance, so that the microelectronic structure 4 can operate effectively.

Please continue to refer to FIG. 9. Through the above steps, the present invention obtains a microelectronic structure 4 including a substrate 410 on which a graphene layer 430, a first electrode 450, a second electrode 440, and a third electrode 470 are formed. The first electrode 450 and the second electrode 440 directly contact both ends of the graphene layer 430. The graphene layer 430 and the substrate 410 are separated by a first insulating layer 420. The third electrode 470 The second insulating layer 460 is spaced from the graphene layer 430, and the graphene layer 430 has an energy gap greater than 300 meV.

The microelectronic structure obtained by the above process, because of increasing the energy gap of the graphene material, greatly improves the electronic characteristics of the microelectronic structure, and through appropriate cleaning processes in the manufacturing process, a graphene layer with the same size and shape is produced. Meet the needs of mass production of microelectronic structures.

Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. In this way, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

S100, S200, S300, S400, S500 ‧‧‧ steps

Claims (10)

A microelectronic structure includes a substrate on which a graphene layer, a first electrode, a second electrode, and a third electrode are formed, wherein the first electrode and the second electrode directly contact the graphene layer. At both ends, the graphene layer and the substrate are separated by a first insulating layer, the third electrode and the graphene layer are separated by a second insulating layer, and the graphene layer has an energy greater than 300 meV. Gap. The microelectronic structure according to item 1 of the patent application scope, wherein the graphene layer includes at least one graphene structure. The microelectronic structure according to item 1 of the scope of patent application, wherein the first electrode, the second electrode, and the third electrode are all metal electrodes. The microelectronic structure according to item 1 of the patent application scope, wherein the first insulating layer is an oxide of the substrate and the second insulating layer is a high-dielectric film. The microelectronic structure according to item 1 of the patent application scope, wherein the microelectronic structure is a double-gate field effect transistor, and the first electrode, the second electrode, and the third electrode are a source electrode and a drain electrode, respectively. And the first gate, and the substrate is the second gate. A method for forming a microelectronic structure includes: forming a graphene layer in-situ on a substrate, the graphene layer including at least one graphene structure, and having an energy gap greater than 300 meV; oxidizing to form a first An insulating layer that separates the graphene layer and the substrate with the first insulating layer; forming a second insulating layer on the graphene layer; and forming a first electrode on the second insulating layer, a A second electrode and a third electrode so that the The first electrode and the second electrode directly contact both ends of the graphene layer, and the third electrode and the graphene layer are separated by the second insulating layer. The method for forming a microelectronic structure according to item 6 of the patent application scope, further comprising a cleaning step before forming the graphene layer in situ, the cleaning step cleans a substrate on the substrate that is intended to form the graphene layer in situ. surface. The method for forming a microelectronic structure according to item 7 of the scope of patent application, wherein the cleaning step is cleaning using ozone. The method for forming a microelectronic structure according to item 7 of the scope of the patent application, wherein the cleaning step is a SiCoNi pre-cleaning process. The method for forming a microelectronic structure according to item 6 of the scope of the patent application, wherein the first insulating layer is formed by passing oxygen through a graphene layer to oxidize the substrate.