TWI607453B - Memory structure and method for manufacturing the same - Google Patents

Description

Memory structure and manufacturing method thereof

The present disclosure relates to a memory structure and a method of fabricating the same, and more particularly to a memory structure including a three-dimensional (3D) array of memory cells and a method of fabricating the same.

It is advantageous that the wires of the semiconductor device have low resistance. For example, in a memory device, the resistance of the common source line is preferably as low as possible to avoid an additional IR drop that would result in a change in the threshold voltage of the memory cell. In a memory structure including a two-dimensional (2D) array of memory cells, this can be easily achieved by increasing the width of each of the shared source lines. However, in a memory structure including a 3D array of memory cells, in order to achieve a high-density array, the space that can be supplied to each of the shared source lines is limited. Therefore, in such a memory structure, it is difficult to provide a low-resistance wire by simply adjusting the geometrical size.

In the present disclosure, a memory structure with reduced IR drop and a method of fabricating the same are provided.

According to some embodiments, such a memory structure includes a 3D array of a plurality of memory cells, a plurality of first wires, a plurality of second wires, an upper metal plate, and at least one strapping structure. The 3D array includes at least one dummy area disposed therein. The first wire is disposed on the 3D array. The second wire is disposed on the first wire. The second wire and the first wire extend in different directions. The upper metal plate is disposed on the second wire. At least one lap structure is used for the first wire and correspondingly disposed on at least one dummy region of the 3D array. Each of the at least one overlapping structure includes a connection structure and a jumper wire. The connection structure is set on the dummy area. The connecting structure connects the first wire. The jumper wire is disposed on the connection structure and coupled to the connection structure. The jumper wire is coupled to the upper metal plate. The patch cord and the second conductor extend in the same direction.

According to some embodiments, such a manufacturing method includes the following steps. First, a 3D array of a plurality of memory cells is formed. The 3D array includes at least one dummy area disposed therein. Forming a plurality of first wires on the 3D array and correspondingly forming at least one connection structure for the at least one overlapping structure of the first wires on at least one dummy region of the 3D array. Forming a plurality of second wires on the first wires, and forming at least one jump wire of the at least one overlapping structure on the at least one connecting structure. The jumper cable is coupled to the connection structure. The second wire and the first wire extend in different directions, and the patch wire and the second wire extend in the same direction. An upper metal plate is formed on the second wire and the jumper wire. The jumper wire is coupled to the upper metal plate.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

A memory structure according to an embodiment includes a 3D array of a plurality of memory cells, a plurality of first wires, a plurality of second wires, an upper metal plate, and at least one overlapping structure. The 3D array includes at least one dummy area disposed therein. The first wire is disposed on the 3D array. The second wire is disposed on the first wire. The second wire and the first wire extend in different directions. The upper metal plate is disposed on the second wire. At least one lap structure is used for the first wire and correspondingly disposed on at least one dummy region of the 3D array. Each of the at least one overlapping structure includes a connection structure and a jumper wire. The connection structure is set on the dummy area. The jumper wire is disposed on the connection structure and coupled to the connection structure. The jumper wire is coupled to the upper metal plate. The patch cord and the second conductor extend in the same direction.

Now, various details of an exemplary memory structure according to an embodiment will be described in conjunction with FIGS. 1A-1B through 5A-5C. For convenience of description, the 3D array of memory cells in the memory structure is depicted as having a single gate vertical channel (SGVC) structure. Further, each of the series of memory cells is depicted as being arranged in a U shape. According to some embodiments, the memory cell is a NAND flash memory cell. However, the memory structure according to an embodiment may include any other kind of suitable 3D memory array. It should be noted that some elements may be omitted from the drawings, and the elements in the drawings may not reflect their true size and shape.

1A-1B illustrates a 3D array 100 of memory cells, and a plurality of first conductors 302 and a connection structure 202 of a lap joint structure 200 disposed thereon, wherein FIG. 1A is a perspective view, in which Some dielectric materials have been removed for purposes of clarity, while Figure 1B is a top view.

According to some embodiments, as shown in the figure, the 3D array 100 has an SGVC structure and a series configured in a U shape. More specifically, the plurality of stacks 102 are disposed on a substrate (not shown). Each stack 102 includes alternating rows of conductive strips 104 and insulating strips 106, wherein the conductive strips 104 may be formed of polysilicon, metal telluride or metal, and the insulating strips 106 may be formed of oxide. According to some embodiments, the uppermost conductive strips 104(T) of adjacent two stacks 102 may serve as ground select lines and tandem select lines, respectively. In some embodiments, the lowermost conductive strip 104 (B) acts as an inversion gate. Other conductive strips 104 can be word lines. A memory layer 108 is conformally disposed on the surface of the stack 102 and the substrate exposed from the trenches between the stacks 102. The memory layer 108 may be an ONO (oxide-nitride-oxide) layer, or a BE-SONOS (energy band engineered bismuth-oxide-nitride oxide-germanium) layer or the like. In each of the grooves, a plurality of channel layers 110 are disposed thereon along the memory layer 108 and separated from each other. The channel layer 110 may be a thin layer formed of polysilicon, which may serve as a local bit line. In this way, the memory cells can be defined at the intersection of the channel layer 110 and the conductive strips 104, thereby constructing the 3D array 100 of memory cells. A dielectric material 112, such as an oxide, is filled into the remaining space, and an air gap 114 can be formed in the dielectric material 112.

The 3D array 100 includes at least one dummy region 116 disposed therein. The at least one dummy region 116 divides the 3D array 100 into a plurality of sub-array regions 118. The at least one dummy region 116 is preferably configured such that the 3D array 100 is equally divided into sub-array regions 118. According to some embodiments, each sub-array region 118 may include 200 to 20,000 rows in a memory cell (here, "n rows in memory cells" and "n-channel memory cells" are synonymous), and adjacent dummy regions 118 may include 2 to 16 rows in the memory cell. The memory cells in the dummy region 116 may be substantially identical to the memory cells in the sub-array region 118, but become "dummy" simply because the lap structures disposed thereon cause them to lose the function of the memory cells.

The first wire 302 is disposed on the 3D array 100. The first wire 302 can extend in the X direction. In some embodiments, as shown in FIG. 1A, the auxiliary conductor 304 can be used as a source terminal directly under the first conductor 302 to improve resistance performance. Plug 306 can be used to couple channel layer 110 to first lead 302. According to some embodiments, the first wire 302 may be a common source line. In such an example, they can be coupled to the source side of the memory cell. According to some embodiments, the first wire 302 has a piece of resistance R _{fc of} about 1 Ω/□ to 10 Ω/□.

The connection structure 202 of the lap structure 200 is disposed on the dummy area 116 of the 3D array 100. According to some embodiments, the connection structure 202 connects the first wire 302. More specifically, as shown in FIG. 1B, the connection structure 202 can include a plurality of connection portions 204 that connect adjacent two first wires 302, respectively. The connection structure 202 preferably physically and electrically connects the first wire 302. Since the dummy region 116 below the connection structure 202 can include 2 to 16 rows in the memory cell, the connection structure 202 can have a width W1 that substantially spans the 2 to 16 rows in the memory cell. The connection structure 202 can be coupled to the channel layer 110 of the memory cell by the plug 306 and the contact via 308, wherein the plug 306 can be formed of polysilicon and the contact via 308 can be formed of metal. The contact vias 308 can be disposed in the same layer as the auxiliary leads 304 and serve as the 汲 extreme. According to some embodiments, the source and drain terminals are disposed on the dummy region 116, and one source terminal and the corresponding one terminal are coupled to each other, for example, by a corresponding first wire 302 and a connecting portion 204.

The connection structure 202 and the first wire 302 are preferably disposed in the same layer. The connection structure 202 and the first wire 302 are preferably formed of the same material by the same process.

2A-2B illustrate elements disposed in a layer higher than the structure shown in FIGS. 1A-1B, wherein FIG. 2A is a perspective view and FIG. 2B is a top view. The lap structure 200 can further include a plurality of first jumper vias 206, and the connection structure 202 is coupled to a jumper wire 208 of the lap structure 200 (shown in FIGS. 3A-3B). In addition, the vias 310 that couple the memory cells to the second leads 312 (shown in FIGS. 3A-3B) above can be formed of the same material in the same process as the first jumper vias 206.

3A-3B illustrate a plurality of second wires 312 and a jumper wire 208 of the lap joint 200 disposed in a layer higher than the structure shown in FIGS. 2A-2B, wherein FIG. 3A is a perspective view And Figure 3B is the top view.

The second wire 312 is disposed on the first wire 302. The second wire 312 and the first wire 302 extend in different directions. In some embodiments, the direction in which the second wire 312 and the first wire 302 extend is substantially perpendicular to each other. The second wire 312 can extend in the Y direction. According to some embodiments, the second wire 312 may be a global bit line. In such an example, they can be coupled to the drain side of the memory cell. According to some embodiments, the second wire 312 has a piece of resistance R _{sc of} about 1 Ω/□ to 10 Ω/□.

The patch cord 208 of the lap structure 200 is disposed on the connection structure 202 and coupled to the connection structure 202. The jumper 208 can be coupled to the connection structure 202 by the first jumper via 206. The patch cord 208 is coupled to an upper metal plate 314 (shown in Figures 5A-5B). Jumper wire 208 and second wire 312 extend in the same direction. According to some embodiments, the ratio of the number of second wires 312 and the total number of patch cords 208 is in a range between 200:1 and 20000:1, such as 512:1, 1024:1 or 2048:1, and the like. Moreover, similar to connection structure 202, patch cord 208 can have a width W2 that substantially spans the 2 to 16 rows in the memory cell. From another perspective, the jumper wires 208 of the lap structure 200 can have a width W2 that is substantially equal to 2 to 16 times the pitch P of the second wires 312 since the second wires respectively correspond to the memory cells of one row.

Jumper wire 208 and second wire 312 are preferably disposed in the same layer. The jumper wire 208 and the second wire 312 are preferably formed of the same material by the same process.

A dummy region 116 including two rows of memory cells, and a lap structure 200 correspondingly spanning the two rows of memory cells are illustrated in FIGS. 1A-1B to 3A-3B. 3C and 3D illustrate alternative embodiments. In Fig. 3C, the dummy region 116' includes three rows of memory cells, and the connection structure 202' of the lap structure 200' and the patch cord 208' correspondingly span the memory cells of the three rows. In the 3D diagram, the dummy region 116" includes four rows of memory cells, and the connection structure 202" of the lap structure 200" and the patch cord 208" correspondingly span the memory cells of the four rows.

4A to 4B are diagrams showing elements disposed in a layer higher than that shown in Figs. 3A to 3B, wherein Fig. 4A is a perspective view and Fig. 4B is a top view. The lap structure 200 can further include a plurality of second jumper vias 210 for coupling the patch cord 208. In some embodiments, the second jumper via 210 couples the patch cord 208 to the upper metal plate 314 (eg, the example of FIG. 5A). In some embodiments, the second jumper via 210 couples the patch cord 208 to some of the third wires 316 (eg, the example of FIG. 5C).

5A-5B illustrate an upper metal plate 314 disposed on the second wire 312, wherein FIG. 5A is a perspective view showing a path of current, and FIG. 5B is a top view. According to some embodiments, the upper metal plate 314 has a piece of resistance R _{tm of} about 0.01 Ω/□ to 0.1 Ω/□. The sheet resistance R _{tm of the} upper metal plate 314 and the sheet resistance R _{fc of the} first wire 302 preferably substantially satisfy the equation: R _tm < 0.1 ́R _fc . The sheet resistances R _tm and R _{fc more} preferably substantially satisfy the equation: R _tm ≤ 0.01 ́R _fc . As a result, the sheet resistance R _{tm of the} upper metal plate 314 can be neglected compared to the sheet resistance R _{fc of the} first wire 302. This means that resistance is no longer a critical issue. By introducing the lap structure 200 that directs the current in the first wire 302 to the upper metal plate 314, the loading of the first wire 302 can be greatly reduced. Thereby reducing the effect of the IR drop on the threshold voltage.

In some embodiments, other components may be disposed between the second wire 312 and the upper metal plate 314. For example, as shown in FIG. 5C, the memory structure may further include a plurality of third wires 316 disposed on the second wires 312. The upper metal plate 314 is disposed on the third wire 316. The third wire 316 and the second wire 312 extend in different directions. According to some embodiments, the third wire 316 may extend in the same direction as the first wire 302. In the example of forming the third wire 316, the second jumper via 210 can couple the patch wire 208 to a plurality of portions of the third wire 316 (eg, certain strips of third wire 316). The lap structure 200 can further include a plurality of third jumper vias 212 that couple the portions of the third wires 316 to the upper metal plate 314.

Reference is now made to Fig. 6, which is a flow diagram of a method of fabricating a memory structure in accordance with an embodiment. In step S41, a 3D array of a plurality of memory cells is formed. The 3D array includes at least one dummy area disposed therein. In step S42, a plurality of first wires are formed on the 3D array, and correspondingly at least one connection structure for at least one overlapping structure of the first wires is formed on at least one dummy region of the 3D array. In step S43, a plurality of second wires are formed on the first wire, and at least one jumper wire forming the at least one overlapping structure is formed on the at least one connecting structure. The jumper cable is coupled to the connection structure. The second wire and the first wire extend in different directions, and the patch wire and the second wire extend in the same direction. In step S44, an upper metal plate is formed on the second wire and the jumper wire. The jumper wire is coupled to the upper metal plate. Other steps may be performed as needed, such as the step of forming a first jumper via and the like.

7A-7B to 10A-10B illustrate an exemplary process for forming a second wire and a patch cord, wherein the 7A, 8A, 9A, and 10A are cross-sectional views, and the 7B, 8B, and 9B, The top view corresponding to the 10B map. In this exemplary process, a self-aligned double patterning technique is used. As shown in Figures 7A-7B, on a lower structure 402, a plurality of layers 404, 406, and 408 can be formed in sequence. Layer 404 may be formed of tantalum nitride, layer 406 may be formed of an oxide, and layer 408 may be a hard mask layer formed of amorphous germanium. A plurality of positioning structures 410 are formed on layer 408. The positioning structure 410 can be formed from an APF film. As shown in Figures 7A-7B, the positioning structure 410 is separated from one another by two spacings S1 and S2, wherein the spacing S1 is designed for the formation of a generally second wire 312, and the spacing S2 is designed for patch cord 208. Formation. For example, in the example where the dummy region 116 includes two rows of memory cells, the interval S2 may be 1.5 times the pitch P of the second wire 312. For a dummy region 116 including three rows of memory cells, the interval S2 may be 2.5P. For a dummy region 116 comprising four rows of memory cells, the interval S2 may be 3.5P. Next, a spacer 412 is formed on the sidewall of the positioning structure 410, and the positioning structure is removed 410 as shown in FIGS. 8A-8B. In some embodiments, a mask 414 for the peripheral region of the memory structure can be provided later. By the next step, the pattern of spacers 412 is transferred to the underlying layer and a layer of dielectric 416 is formed, as shown in Figures 9A-9B. A conductive material is filled into the trench between the layer dielectrics 416 to form a second wire 312 and jumper 208, as shown in Figures 10A-10B.

It will be appreciated that the process for fabricating a memory structure in accordance with an embodiment and the typical process for fabricating a memory structure are compatible. More specifically, it is only necessary to adjust the process of forming a few layers, such as the process of the first wire 302, the second wire 312, and the second jumper via 210. Therefore, the adjustments made will not lead to unacceptable cost increases and manufacturing time.

Referring now to Figs. 11A to 11C, the reduction in IR drop is explained in conjunction with the memory structure for comparison shown in Fig. 11A and the memory structure according to the embodiment shown in Figs. 11B and 11C.

As shown in FIG. 11A, word line pad regions 504 may be respectively disposed on both sides of the primary array region 502. Such a word line pad region 504 can also provide a first wire bonding function. However, one word line pad region 504 requires a space of about 5 microns to 10 microns. For the memory structure, the additional set word line pad area 504 is space-consuming. Hereinafter, the current and resistance across the sub-array region 502 shown in FIG. 11A are defined as I and R, respectively.

In the example of Fig. 11B, a lap structure 506 is provided to divide the sub-array region 502 shown in Fig. 11A into two sub-array regions 502. The space required for the lap structure 506 can be as small as about 0.1 microns, which is much lower than the space required for one word line pad region 504. The overhead of such a lap structure 506 is negligible. Since the first wire as the common source line is used to collect the series current, the current in the first wire is proportional to the number of memory cells between the two structures having the overlapping function. Therefore, by introducing a lap structure 506 as shown in Fig. 11B, the current in the first wire is reduced to I/2. In addition, the resistance is proportional to the length of the passage and thus also to the number of memory cell rows between the two structures having overlapping functions. Therefore, by introducing a lap structure 506 as shown in Fig. 11B, the resistance is reduced to R/2. This means that the load of the first wire can be reduced to 1/4 compared to the example of Fig. 11A.

Similarly, in the example of FIG. 11C, the three overlapping structures 506 divide the sub-array region 502 shown in FIG. 11A into four sub-array regions 502 such that the load of the first wire is compared to the example of FIG. 11A. Can be reduced to 1/16.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧3D array
102‧‧‧Stacking
104, 104 (B), 104 (T) ‧ ‧ conductive strips
106‧‧‧Insulated strips
108‧‧‧ memory layer
110‧‧‧Channel layer
112‧‧‧Dielectric materials
114‧‧‧ Air gap
116, 116', 116" ‧ ‧ 虚 虚
118‧‧‧ array area
200, 200', 200" ‧ ‧ lap joint structure
202, 202', 202" ‧‧‧ connection structure
204‧‧‧Connected section
206‧‧‧First jumper
208, 208', 208" ‧ ‧ jumper
210‧‧‧Second jumper
212‧‧‧The third jumper
302‧‧‧First wire
304‧‧‧Auxiliary wire
306‧‧‧ Plug
308‧‧‧Contact vias
310‧‧‧ Guide hole
312‧‧‧second wire
314‧‧‧Upper metal plate
316‧‧‧ Third wire
402‧‧‧ below structure
404‧‧ layer
406‧‧ ‧
408‧‧ ‧
410‧‧‧ Positioning structure
412‧‧‧ spacers
414‧‧‧ mask
416‧‧‧Intermediary
502‧‧‧ array area
504‧‧‧ character line pad area
506‧‧‧ lap structure
P‧‧‧ pitch
S1‧‧ interval
S2‧‧ ‧ interval
S41‧‧‧ steps
S42‧‧‧Steps
S43‧‧‧Steps
S44‧‧‧ steps
W1‧‧‧Width
W2‧‧‧Width

FIGS. 1A-1B to 5A-5C illustrate details of a memory structure according to an embodiment. Figure 6 is a flow chart of a method of fabricating a memory structure in accordance with an embodiment. 7A-7B to 10A-10B illustrate an exemplary process for fabricating a patch cord and a second wire of a memory structure in accordance with an embodiment. 11A to 11C are diagrams showing an exemplary configuration of a memory structure for comparison and a lap joint structure of a memory structure according to the embodiment.

502‧‧‧ array area

504‧‧‧ character line pad area

506‧‧‧ lap structure

Claims (10)

A memory structure comprising: a 3D array of a plurality of memory cells, the 3D array comprising at least one dummy region disposed therein; a plurality of first wires disposed on the 3D array; and a plurality of second wires disposed at The first wires, wherein the second wires and the first wires extend in different directions; an upper metal plate disposed on the second wires; and at least one overlapping structure for The first wires are correspondingly disposed on the at least one dummy region of the 3D array, and each of the at least one overlapping structure comprises: a connection structure disposed on the dummy region; and a jump wire connection And connecting the connection structure to the connection structure, the jumper is coupled to the upper metal plate, wherein the jumper wire and the second wires extend in the same direction. The memory structure of claim 1, wherein the connection structure of each of the at least one overlapping structure connects the first wires. The memory structure of claim 2, wherein each of the at least one overlapping structure further comprises: a plurality of first jumper vias, the connection structure being coupled to the jumper; and a plurality of The second jumper is connected to the upper metal plate. The memory structure of claim 2, further comprising: a plurality of third wires disposed on the second wires, wherein the upper metal plate is disposed on the third wires, and wherein the The third wire and the second wire extend in different directions; and each of the at least one overlapping structure further comprises: a plurality of first jumper vias, the connection structure being coupled to the jump Wiring; a plurality of second jumper vias, the jumper is coupled to the plurality of portions of the third wires; and a plurality of third jumper vias, the portions of the third wires being coupled To the upper metal plate. The memory structure of claim 1, wherein a piece of resistance R _{tm of} the upper metal plate and a piece of resistance R _{fc of the} first wires substantially satisfy an equation: R _tm ≤ 0.01 ́R _fc . The memory structure of claim 1, wherein the connection structure of each of the at least one overlapping structure and the first wires are disposed in the same layer, and each of the at least one overlapping structure The jumper wire and the second wires are disposed on the same layer. The memory structure of claim 1, wherein the number of the second wires and the total number of the jumpers of the at least one overlapping structure are between 200:1 and 20000:1. Within the scope. The memory structure of claim 1, wherein each of the at least one dummy regions of the 3D array comprises 2 to 16 rows of the memory cells, and each of the at least one overlapping structure The connection structure and the patch cord have a width spanning the 2 to 16 rows of the memory cells, and wherein the jumper wires of each of the at least one overlap structure have a pitch substantially equal to the second wires A width of 2 to 16 times. The memory structure of claim 1, further comprising: a plurality of auxiliary wires directly formed under the first wires, the auxiliary wires being a plurality of source terminals; and a plurality of contact holes, setting And a plurality of channel layers for coupling the connection structures to the memory cells, the contact holes being a plurality of channel terminals; wherein the source terminals and the plurality of channel electrodes Extremely disposed on the at least one dummy region of the 3D array, and one of the source terminals and a corresponding one of the germanium terminals are coupled to each other. A method of fabricating a memory structure, comprising: forming a 3D array of a plurality of memory cells, the 3D array comprising at least one dummy region disposed therein; forming a plurality of first wires on the 3D array, and correspondingly forming At least one connection structure of the at least one overlapping structure of the first wires is on the at least one dummy region of the 3D array; forming a plurality of second wires on the first wires, and forming the at least one overlap At least one jumper of the structure is connected to the at least one connection structure, wherein the at least one jumper is coupled to the at least one connection structure, and wherein the second wires and the first wires extend in different directions, The at least one jumper wire and the second wires extend in the same direction; and an upper metal plate is formed on the second wires and the at least one jumper wire, wherein the at least one jumper wire is coupled to the upper portion Metal plate.