TWI606391B - Floating-point divider and method for operating floating-point divider - Google Patents

Description

Floating point divider and floating point divider operation method

This case is about floating-point dividers.

Floating-point dividers require multiple iterations of quotient calculations. However, in the face of large radix design requirements, the quotient calculated by the floating-point divider per round has a considerable number of bits, and the logic circuit design is rather cumbersome.

In this case, a floating-point divider is proposed. The short-order quotient quotient obtained by multiple look-up tables is combined in one round operation, and the combined quotient value of the long-order quantity is output, wherein each round of operations includes prediction of the next round of operations. Part of the resulting combined quotient value.

A floating point divider according to an embodiment of the present invention includes a wheel part remainder generator, a part remainder simulator, a first quotient table, and a first multiplexer. The wheel partial remainder generator generates a second partial remainder based on a first partial remainder, a divisor, and a first quotient. The partial remainder simulator generates a plurality of third partial remainder candidates according to the second partial remainder, the divisor and the plurality of second quotient value to be tested. The first quotient value table is queried to supply a remainder corresponding to the second part and a second quotient of the divisor. The first quotient value table is further queried, and supplies a third part remainder candidate corresponding to the third part and a plurality of third quotient candidate of the divisor. The first multiplexer from the third quotient Select to select the output corresponding to the second quotient as a third quotient. The third quotient value is used as a partial bit of the combined quotient value of the next round of operation, or as a partial bit of the combined quotient value of the current round but is more used to predict the content required for the next round of operations.

A floating point divider operating method according to an embodiment of the present invention, for operating a floating point divider including a first quotient value table, comprising: according to a first partial remainder, a divisor, and a first quotient Generating a second partial remainder; generating a plurality of third partial remainder candidates according to the second partial remainder, the divisor, and the plurality of second quotient values to be measured; querying the first quotient value table, the supply corresponding to a second partial remainder and a second quotient of the divisor; querying the first quotient value table, supplying a third partial remainder candidate corresponding to the third remainder candidate and the divisor; and providing a first plurality The tool selects the output corresponding to the second quotient from among the third quotient candidates as a third quotient. The third quotient value is used as a partial bit of the combined quotient value of the next round of operation, or as a partial bit of the combined quotient value of the current round but is more used to predict the content required for the next round of operations.

This case makes the round-point divider's round of operations not only perform a quotient table query. The quotient value query results obtained multiple times can be combined and combined with the quotient value output in one round of operation of the floating point divider. The long bit quotient that the larger base floating-point divider should output in each round of operations can be combined by a plurality of short bit data obtained by looking up the table. In addition, each round of the floating-point divider of this case includes a partial bit that predicts the combined quotient value output by the next round of operations, which is much more efficient than the traditional floating-point divider architecture.

The invention is described in detail below with reference to the accompanying drawings.

200‧‧‧ floating point divider

202‧‧‧When part of the wheel remainder generator

204‧‧‧Partial remainder simulator

206‧‧‧First Business Value Form

207‧‧‧First multiplexer

208‧‧‧Second business value form and second multiplexer

210‧‧‧Commerce value converter

212‧‧‧Subsequent round part remainder generator

400‧‧‧Floating point divider

410‧‧‧Partial remainder simulator

420‧‧‧ first commercial value form and first multiplexer

430‧‧‧Commerce value converter

440‧‧‧Subsequent round part remainder generator

D‧‧‧Divisor

Q‧‧‧Combined quotient

Q0...q3, q(i+1), qa, qb, qc, qan‧‧‧ quotient

Qp1...qpN‧‧‧second/third quotient value to be measured

S1...S3, S(i+1), Sa, Sb, San‧‧‧ partial remainder

S302...S314, S502...S518‧‧‧ steps

San1...SanN, Sc1...ScN, San11...San1N,...,SanN1...SanNN‧‧‧ Partial candidate

Qan1...qanN‧‧‧ third quotient candidate

w‧‧‧Divisor

W0...w2, w(i+1)‧‧‧ intermediate remainder

FIG. 1A illustrates each operand of the division operation; FIG. 1B and FIG. 1C show the quotient value table in two-dimensional coordinates; FIG. 2 illustrates a floating-point divider 200 according to an embodiment of the present invention; The operation method of the floating-point divider 200 of FIG. 2 is illustrated to provide a division operation (w/d); FIG. 4 illustrates a floating-point divider 400 according to another embodiment of the present invention; and the processes of FIGS. 5A and 5B are processes. FIG. 4 illustrates the operation of the floating point divider 400 to provide a division operation (w/d).

The following description sets forth various embodiments of the invention. The following description sets forth the basic concepts of the invention and is not intended to limit the invention. The scope of the actual invention shall be defined in accordance with the scope of the patent application.

FIG. 1A illustrates an operation unit of a division operation including a dividend w and a divisor d, and sequentially obtains quotient values q0, q1, q2, and q3 in the operation. It should be noted that the operation of the four quotient values q0~q3 is only an example, and the present invention is not limited thereto. The number of quotient values is determined by when the divisor w is divided by the divisor d or converged, so the division operation is likely The number of other quotients obtained is not limited to four. In this embodiment, the radix 4 is used, that is, a quotient of 2 bits is generated per clock cycle. During the calculation of the quotient q0, q1, q2, q3, the decimal point of the intermediate remainder wi is shifted to the right by 2 bits (ie 4×wi), and i is the number. In this case, the values wi and 4×wi are referred to as partial remainders, and the label S(i+1). The quotient q(i+1) can be obtained by looking up the table according to the partial remainder S(i+1) and the divisor d.

Figure 1B shows a quotient value table in two-dimensional coordinates. A method of table lookup is to use a partial remainder 4×wi (ie S(i+1)) lookup table to compare the partial remainder 4×wi (ie S(i+1)) with various multiples of the divisor d. Corresponding quotient q(i+1) line. On the quotient q(i+1) line, the partial remainder 4×wi, which is a certain multiple of the divisor d, is the same, and the quotient q(i+1) within a certain range is the same, as shown in Figure 1B, [- d, The partial remainder 4 × wi in the d] interval corresponds to the quotient q(i+1)=0. In the following, in conjunction with FIG. 1A, how to query the quotient value table to obtain the corresponding quotient value, for example, the partial remainder 4×w0=1.110101B 1.75D (where B represents a binary number, D represents a decimal number), and divisor d=1.101B 1.625D, the partial remainder 4×w0 is represented as approximately 1.08 times the divisor d, so the quotient value table in the 1B graph can be queried to know that the corresponding quotient q1=1. On the partial remainder 4×wi (ie S(i+1)) axis, more critical values can be designed, so that the partial remainder 4×wi corresponding to multiple quotient q(i+1) lines can be correctly derived from the quotient The q(i+1) line selects the correct counterpart. Figure 1C shows a quotient value table in another two-dimensional coordinate, where wi is the partial remainder, that is, the value of the value system wi on the S(i+1) axis, and the partial remainder wi is used to look up the table, and the partial remainder wi Corresponding quotient q(i+1) lines are obtained by comparison with various multiples of the divisor d. The quotient value table of Fig. 1B or 1C is used to obtain the quotient value q(i+1) based on the partial remainder S(i+1) and the divisor d table. The above quotient table concept can be used in floating point divider applications of various cardinalities. In this embodiment, the radix 4 is obtained, that is, the quotient value of 2 bits is generated every clock cycle. If the quotient value table can be queried only once per clock cycle, the quotient value ranges from {-2, -1. 0,1,2}. In other embodiments using other cardinalities, for example, a base number of 16, a quotient of 4 bits is generated per clock cycle. If the quotient value table can only be queried once per clock cycle, the quotient value ranges from {-15 ,-14,-13,-12,...-1,0,1,...12,13,14,15}, ie [-15,15], but the invention is not limited thereto, taking different When the quotient encoding method is used, the range of quotient values will vary. It is time-consuming to query the quotient value table in floating-point division operation, and the more quotient bits obtained by each table lookup, the greater the hardware overhead. Therefore, the present invention proposes a floating-point divider for performing a multi-quota table query with one round of operations, even if a quotient value table with a small hardware overhead is used, for example, even if a table is used, only a 2-bit quotient can be obtained. A table of values (for example, querying the quotient value table of Figure 1B), a round of arithmetic queries can also get a 4-bit quotient, that is, the implementation base 16, such as SRT-16, without having to use a quotient with a large hardware overhead. A quotient value table with a value range of [-15, 15].

This case makes the round-point divider's round of operations not only perform a quotient table query. The quotient value query results obtained multiple times can be combined and combined with the quotient value output in one round of operation of the floating point divider. The long-bit quotient value that the larger base floating-point divider should output in each round of operations can be combined by the short-bit metadata obtained by looking up the table. In addition, each round of the floating-point divider of this case includes a partial bit that predicts the combined quotient value output by the next round of operations, which is much more efficient than the traditional floating-point divider architecture.

2 illustrates a floating point divider 200 according to an embodiment of the present invention, including a wheel portion remainder generator 202, a portion of the remainder simulator 204, a first quotient table 206, and a first multiplexer 207, a first The second quotient table and a second multiplexer (indicated by block 208), a quotient converter 210, and a subsequent wheel partial remainder generator 212.

The wheel partial remainder generator 202 generates a second partial remainder Sb based on a first partial remainder Sa, a divisor d, and a first quotient value qa. The partial remainder simulator 204 is based on the second partial remainder Sb, the divisor d, and a plurality of The second quotient value to be measured qp1...qpN generates a plurality of third partial remainder candidates San1...SanN. The second quotient value to be measured qp1...qpN may be all possible values of the second quotient value qb. For example, qp1...qpN takes values of all possible quotient values in the quotient value table of FIG. 1B or FIG. 1C. The first quotient value table 206 is queried to supply a second quotient value qb corresponding to the second part remainder Sb and the divisor d. The first quotient value table 206 is further used to query the supply of the third partial remainder candidates San1...SanN and the plurality of third quotient candidates qan1...qanN of the divisor d, and the first multiplexer 207 is based on the first multiplexer 207. The second quotient value qb selects an output corresponding to the second quotient value qb from the third quotient value candidates qan1...qanN as a third quotient value qan, that is, selects the second quotient value qb (as a plurality of The third quotient candidate (one of qan1...qanN) corresponding to the third partial remainder candidate (one of San1...SanN) corresponding to the second quotient value to be measured qp1...qpN is taken as the third quotient value qan. In particular, the second quotient table and the second multiplexer (208) are used in a first round of operation of the floating point divider 200, corresponding to a dividend w and the divisor d to supply the first The quotient value qa and the first portion remainder Sa are to the wheel portion remainder generator 202. As shown in the figure, the quotient converter 210 combines the first quotient value qa and the second quotient value qb for providing M-bit information into a combined quotient value Q of 2M bits in each round of operation. M is a numerical value. As for the third quotient qan, this embodiment uses it as a partial bit of the next round of quotient Q. The third quotient value qan will be switched via the second multiplexer in block 208 as the first quotient value qa used in the next round of operations. The first partial remainder Sa required for the next round of combined quotient Q operations is provided by the subsequent round partial remainder generator 212. The subsequent round part remainder generator 212 generates a third partial remainder San according to the second partial remainder Sb, the divisor d and the second quotient value qb. The second multiplexer within block 208 switches the supply of the first partial remainder Sa required for the next round of operations. As described above, the second quotient table and the second multiplexer (208) are only used in the first round of the floating-point divider 200 for the divisor w and the divisor d to obtain the first partial remainder Sa and A quotient value qa is used; and in the subsequent round of operations, the second quotient value in block 208 is not needed, but the second multiplexer in block 208 directly selects the third quotient obtained from the previous round of operations. Qan is used as the first quotient value qa of the current round operation, and the third partial remainder San obtained from the previous round operation is selected as the first partial remainder Sa of the current round operation.

In an embodiment, the wheel portion remainder generator 202, the partial remainder simulator 204, and the subsequent wheel portion remainder generator 212 are all based on r x wi-q(i+1) x d=w(i+ 1) Designed by operation, where r is the intermediate remainder wi shift bit amount. For example, in the embodiment of FIG. 1A, r takes a value of 4, w(i+1)=4×wi-q(i+1)×d, and a partial remainder S(i+1)=4×wi, specifically For example, d=1.101B, and q1=1 according to the first partial remainder S1=4×w0=1.110101B query quotient value table; then w1=4×w0-q1×d=1.110101B-1×1.101B= 0.001101B, the remainder of the second part S2 = 4 × w1 = 0.1101B. Depending on the different definition of the partial remainder S(i+1) (eg, S(i+1)=r×wi or S(i+1)=wi), the wheel partial remainder generator 202, the partial remainder simulator The logic circuit design of 204 and the subsequent wheel portion remainder generator 212 will be adjusted accordingly. The wheel partial remainder generator 202, the partial remainder simulator 204, and the subsequent wheel partial remainder generator 212 can implement the above r×wi-q(i) using logical arithmetic elements such as a serial adder, an adder, and a multiplier. +1)×d=w(i+1) operation, such that the partial remainder S is output according to the partial remainder S(i+1) (ie r×wi or wi), the divisor d, and the quotient q(i+1) i+2) (ie r×w(i+1) or w(i+1)). First quotient form 206 It is also based on the definition of the partial remainder.

Taking the base 256 as an example, the combined quotient value Q that the floating-point divider 200 should output is 8 bits, wherein the upper 4 bits are provided by the first quotient value qa, and the lower 4 bits are represented by the second quotient value. Qb is provided. The 4-bit quotient operation is much smaller and simpler than the 8-bit hardware. The displacement of the intermediate remainder wi is only ²⁴ bits, which is much lower than the ²⁸ bits required by the traditional floating-point divider architecture. In addition, with regard to the floating point divider 200 architecture of base 256, the second quotient value to be measured qp1...qpN can be set to {-15,-14,-13,-12,...-1,0,1,. ..12,13,14,15} 31 values to estimate 31 third-part remainder candidates. Of course, the present invention is not limited to the quotient range of radix 256 [-15, 15]. When different quotient coding methods are adopted, the range of quotient values will be different, which is [-N, N]. 2N+1 values, where N {8,9,10,11,12,13,14,15}.

Fig. 3 is a flow chart illustrating the operation of the floating point divider 200 of Fig. 2 to provide a division operation (w/d).

Step S302 receives the dividend w and the divisor d, and obtains the first quotient value qa according to the second quotient value table in the query block 208. Step S304 operates the wheel partial remainder generator 202 to generate a second partial remainder Sb based on the dividend w (the first partial remainder Sa calculated as the first round combined quotient Q), the divisor d, and the first quotient qa. Step S306 operates the partial remainder simulator 204 to generate third partial remainder candidates San1...SanN based on the second partial remainder Sb, the divisor d, and the second quotient value to be measured qp1...qpN. Step S308 queries the first quotient value table 206 according to the second partial remainder Sb and the divisor d to obtain the second quotient value qb. Step S310, according to the third partial remainder candidate San1...SanN and the divisor d, the first quotient value table 206 is obtained to obtain the third quotient candidate qan1...qanN, which is sent to the first multiplexer 207 according to step S308. The second quotient value qb selects an output corresponding to the second quotient value qb from the third quotient candidate qan1...qanN as the third quotient value qan. Step S312 operates the subsequent wheel partial remainder generator 212 to generate a third partial remainder San based on the second partial remainder Sb, the divisor d, and the second quotient value qb. In step S314, the third quotient value qan and the third partial remainder San are passed by the second multiplexer in block 208 to the wheel portion remainder generator 202 as a new round of operations required by the floating point divider 200. A quotient value qa and a first partial remainder Sa, that is, the third quotient value qan generated by the previous round operation is used as the first quotient value qa required for the new round of operation, and the third partial remainder San generated by the previous round operation is taken as a new round. The first partial remainder Sa required for the operation is generated to generate the second partial remainder Sb of the new round of operations, and the flow returns to step S306. The process shown in Figure 3 can be cycled until the number of remaining remainders is insufficient. The disclosed division process will obtain the first quotient value qa and the second quotient value qb in each round of operations, and the conversion is combined into the combined quotient value Q. All the combined quotient values Q obtained by the different round operations will be combined into the result of the division operation w/d. In other embodiments, step S308 may be arranged before step S306 or in step S310, that is, step S306 and step S308 are in no particular order.

4 illustrates a floating point divider 400 according to another embodiment of the present invention, which provides a partial remainder simulator 410, a first quotient table, and a first multiplexer (in combination with block 420) as compared to the floating point divider 200. The representation, the quotient converter 430, and the subsequent wheel partial remainder generator 440 are such that the combined quotient value Q obtained for each round of operations is converted from a combination of three quotient values qa, qb, and qc.

The partial remainder simulator 410 generates a plurality of third partial remainder candidates Sc1...ScN according to the second partial remainder Sb, the divisor d, and the plurality of second quotient value to be measured qp1...qpN, and further according to the third portion Residual candidate Sc1...ScN, the divisor d, and a plurality of third quotient value to be tested (this example is also qp1...qpN) yield a plurality of fourth partial remainder candidates San11...San1N, ..., SanN1...SanNN. The first quotient value table in block 420 is queried to supply a second quotient value qb corresponding to the second partial remainder Sb and the divisor d; the first quotient value table in block 420 is further queried, corresponding to And the third partial remainder candidate Sc1...ScN and the divisor d supply a plurality of third quotient candidate qc1...qcN (not shown) to the first multiplexer in block 420 from the second quotient qb An output of the third quotient candidate qc1...qcN corresponding to the second quotient value qb is selected as a third quotient value qc, that is, the second quotient value qb is selected first (as a plurality of second quotient values to be measured qp1 A third quotient candidate (one of qc1...qcN) corresponding to the third partial remainder candidate (one of Sc1...ScN) corresponding to one of qpN is taken as the third quotient value qc. In addition, the first quotient table in block 420 is further queried, and a plurality of fourth quotients are supplied according to the (N x N) fourth partial remainder candidates San11...San1N, ..., SanN1...SanNN and the divisor d. Value candidates qan11...qan1N,...,qanN1...qanNN (not shown), the first multiplexer in block 420 corresponds to the second quotient value qb and the third quotient value qc is selected as a fourth quotient The value qan is output. For example, the first multiplexer in block 420 selects the second quotient value qb (as one of the plurality of second quotient values to be measured qp1...qpN) according to the second quotient value qb obtained by looking up the table. The third part of the remainder candidate (one of Sc1...ScN) corresponds to the N fourth partial remainder candidates (a group of San11...San1N, ..., SanN1...SanNN, for example, Sani1...SaniN); The third quotient value qc selects the third quotient value qc from the N selected fourth partial remainder candidates (formerly Sani1...SaniN) (as a plurality of third quotient values to be measured, also qp1 ...qpN one) corresponding to the fourth The fourth quotient candidate (which is one of qani1...qaniN) corresponding to the partial remainder candidate (which is one of Sani1...SaniN) is output as the fourth quotient value qan. In other embodiments, the second quotient value qb may be further input to the partial remainder simulator 410 such that the partial remainder simulator 410 is no longer redundantly providing the third partial remainder candidates Sc1...ScN and the fourth portion The remainder candidate San11...San1N, ..., SanN1...SanNN does not correspond to the second quotient qb.

The quotient converter 430 is designed in each round of operations, and combines the first quotient value qa, the second quotient value qb, and the third quotient value qc that provide M-bit information into 3M bits. The combined quotient value Q, the above M is a numerical value. Taking the base 2 ⁹ as an example, the floating point divider 400 can generate a combined quotient Q of 9 bits in each round of operations, which is a first quotient value qa of 3 bits, a second quotient value qb of 3 bits, and The 3-bit third quotient qc is obtained by combining conversion.

The subsequent round portion remainder generator 440 operates as follows. Based on the second partial remainder Sb, the divisor d, and the second quotient value qb, the subsequent round partial remainder generator 440 generates a third partial remainder Sc (within block 440, not shown), and further The third partial remainder Sc (not shown), the divisor d, and the third quotient value qc produces a fourth partial remainder San. The fourth quotient qan and the fourth partial remainder San generated by the floating point divider 400 are switched by the second multiplexer in the block 208 after the first round operation of the floating point divider 400, and the output is switched to the next round of operations. The above-mentioned first quotient value qa and the first part remainder Sa are required. Compared with the floating point divider 200, the third quotient value qc generated by the floating point divider 400 is used as a partial bit of the combined quotient Q of the current round, but is more used to predict the content required for the next round of operations (for example, Qan and San are based on qc). Compared with the floating point divider 200, the floating point divider 400 performs the third quotient table query in parallel in the same round operation. For example, the partial remainder simulator 410 performs operations to generate N third partial remainder candidates Sc1...ScN, and then performs nesting operations according to the generated N third partial remainder candidates Sc1...ScN to generate N×N fourth portions. The remainder candidates San11...San1N, ..., SanN1...SanNN, from the determined qb and qc as the selection signals of the multiplexer logic in the first multiplexer in block 420, from N x N fourth partial remainder candidates San11...San1N The selected one of N × N q values corresponding to , ..., SanN1 ... SanNN is output as qan. The embodiment of Fig. 4 compares the time-consuming output quotient qb, qc and qan three quotient table query operations side by side, so that it can be completed in the same round of operations, and must wait for the first round of lookup table than the prior art. After the second quotient value qb, the third part residual value Sc is calculated by the second quotient value qb to perform the second round of lookup table by the third quotient value qc, and then the third part quotient qc is used to calculate the fourth part remainder San. The third round of checklists has qan, which is greatly reduced in time.

5A and 5B are flowcharts illustrating the operation of the floating point divider 400 of Fig. 4 to provide a division operation (w/d).

Step S502 receives the dividend w and the divisor d, and obtains the first quotient value qa according to the second quotient value table in the query block 208. Step S504 operates the wheel partial remainder generator 202 to generate the second partial remainder Sb based on the dividend w (the first partial remainder Sa calculated as the first round combined quotient Q), the divisor d, and the first quotient qa. Step S506 operates the partial remainder simulator 410 to generate the third partial remainder candidates Sc1...ScN based on the second partial remainder Sb, the divisor d, and the second quotient value to be measured qp1...qpN. Step S508 again operates the partial remainder simulator 410 to generate the fourth partial remainder candidate San11...San1N according to the third partial remainder candidate Sc1...ScN, the divisor d, and the third quotient value to be measured (this example is also qp1...qpN). ..., SanN1...SanNN. Step S510, according to the second part remainder Sb and the divisor d, the query block The first quotient value table in 420 obtains the second quotient value qb. Step S512 obtains the third quotient candidate qc1...qcN according to the third partial remainder candidate Sc1...ScN and the divisor d, and the first quotient table in the query block 420 is passed to the first multiplexer in the block 420 according to step S510. The generated second quotient value qb selects an output corresponding to the second quotient value qb from the third quotient value candidates qc1...qcN as the third quotient value qc. Step S514 obtains fourth quotient candidate qan11...qan1N,... according to the fourth partial remainder candidates San11...San1N, ..., SanN1...SanNN (N×N) and the divisor d, in the first quotient table in the query block 420. qanN1...qanNN (N×N), the first multiplexer in block 420 selects the output corresponding to the second and third quotient values qb and qc as the fourth quotient value qan. Step S516 operates the subsequent wheel partial remainder generator 440 to generate a third partial remainder Sc (inside of block 440) based on the second partial remainder Sb, the divisor d, and the second quotient qb, and further based on the third partial remainder Sc, The divisor d and the third quotient value qc produce a fourth partial remainder San. In step S518, the fourth quotient value qan and the fourth partial remainder San are passed by the second multiplexer in the block 208 to the wheel portion remainder generator 202 as a new round of operations required by the floating point divider 400. A quotient value qa and a first partial remainder Sa are generated to generate a second partial remainder Sb of the new round of operations, and the flow returns to step S506. The flow shown in Figures 5A and 5B can be cycled until the number of remaining remainder bits is insufficient. The disclosed division process will obtain the first quotient value qa, the second quotient value qb, and the third quotient value qc in each round of operations, and the operator quotient converter 430 converts the combination into the combined quotient value Q. All the combined quotient values Q obtained by the different round operations will be combined into the result of the division operation w/d. In other embodiments, steps S510 and S512 can be fine-tuned to the previous or subsequent steps.

In other embodiments, a partial remainder simulator can simulate The number of quotients can be more than one (qan) shown in Figure 2 or two (qc and qan) shown in Figure 4. According to the same concept described above, the partial remainder simulator can even simulate more than two quotient values.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

200‧‧‧ floating point divider

202‧‧‧When part of the wheel remainder generator

204‧‧‧Partial remainder simulator

206‧‧‧First Business Value Form

207‧‧‧First multiplexer

208‧‧‧Second business value form and second multiplexer

210‧‧‧Commerce value converter

212‧‧‧Subsequent round part remainder generator

D‧‧‧Divisor

Q‧‧‧Combined quotient

Qa, qb, qan‧‧‧ first, second and third quotient

Qp1...qpN‧‧‧second quotient value to be measured

Qan1...qanN‧‧‧ third quotient candidate

Sa, Sb, San‧‧‧ the first, second and third parts of the remainder

San1...SanN‧‧‧Part III Residual Candidate

w‧‧‧Divisor

Claims (16)

A floating point divider comprising: a wheel part remainder generator, generating a second partial remainder according to a first partial remainder, a divisor and a first quotient; a part of the remainder simulator, according to the second part remainder And the divisor and the plurality of second quotient values to be tested, generating a plurality of third partial remainder candidates; a first quotient value table and a first multiplexer; and a subsequent round partial remainder generator, wherein: The first quotient table is queried, and supplies a second part of the remainder and a second quotient of the divisor; the first quotient table is further queried, and the supply corresponds to the third part of the remainder candidate and the divisor a plurality of third quotient candidate; the first multiplexer selects a output corresponding to the second quotient from the third quotient candidates as a third quotient; the subsequent round partial remainder generator is based on the a second partial remainder, the divisor, and the second quotient, generating a third partial remainder; in a first round of the floating point divider, the first quotient is based on a dividend and the division Obtained by number, and the Used as the first partial remainder; in the subsequent round operation of the floating-point divider following the first round of operations, the first quotient is obtained based on the third quotient, and the first partial remainder is based on The third part of the remainder is obtained; and the second quotient value to be measured is included in the first quotient value table. The floating-point divider according to claim 1, wherein the first multiplexer selects the third corresponding to the corresponding one of the plurality of second quotient values to be measured by the second quotient value The third quotient candidate corresponding to the partial remainder candidate is used as the third quotient. The floating point divider according to claim 1, further comprising a second quotient value table, wherein: in the first round of operation of the floating point divider, the second quotient table is queried, The divisor and the divisor should be supplied with the first quotient value; and in the first round of operation, the dividend is used as the first partial remainder input to the current wheel portion remainder generator. The floating point divider according to claim 1, further comprising: a quotient converter, wherein each of the rounds of operations provides the first quotient of the M bit information and the second quotient The conversion is combined into a quotient of 2M bits, and the above M is a positive integer. The floating-point divider as described in claim 1, further comprising: a second multiplexer, switching the output of the third quotient in the subsequent round operation of the floating-point divider following the first round of operations As the first quotient value, and outputting the remainder of the third part as the remainder of the first part. The floating-point divider as claimed in claim 1, wherein: the partial remainder simulator further determines, according to the third-part remainder candidate, the second quotient, the divisor, and the plurality of third quotient values. a plurality of fourth partial remainder candidates are generated; the first quotient table is further queried, and the fourth partial remainder candidate corresponding to the fourth remainder and the plurality of fourth quotient candidates of the divisor are supplied; The first multiplexer further selects a third quotient value output from the fourth quotient candidate as a fourth quotient value; and the third quotient value to be measured is included in the first quotient Value table. The floating point divider as described in claim 1, further comprising: a quotient converter, wherein the first quotient value and the second quotient value of each of the M bit information are provided in each round of operations And the third quotient conversion is combined into a quotient of 3M bits, and the above M is a positive integer. The floating-point divider of claim 6, wherein: the subsequent-round partial remainder generator further generates a fourth partial remainder according to the third partial remainder, the divisor and the third quotient; The floating point divider further includes a second multiplexer, wherein the floating point divider continues to output the fourth quotient value as the first quotient value in the subsequent round operation of the first round operation, and outputs the first The four-part remainder is the remainder of the first part above. A floating point divider operation method for operating a floating point divider including a first quotient value table, comprising: generating a second partial remainder according to a first partial remainder, a divisor, and a first quotient; Generating a plurality of third partial remainder candidates according to the second partial remainder, the divisor and the plurality of second quotient value to be tested; querying the first quotient value table, supplying the second partial remainder and the divisor a second quotient value; querying the first quotient value table, supplying a third-part remainder candidate corresponding to the third part, and a plurality of third quotient candidate of the divisor; Providing a first multiplexer, selecting, from the third quotient candidate, a output corresponding to the second quotient as a third quotient; and according to the second part remainder, the divisor, and the second quotient a value, generating a third partial remainder, wherein: in a first round of the floating-point divider, the first quotient is obtained based on a dividend and the divisor, and the dividend is used Making the first partial remainder; in the subsequent round operation of the floating-point divider following the first round of operations, the first quotient is obtained based on the third quotient, and the first partial remainder is based on the first Obtained from the three-part remainder; and the second quotient values to be measured are included in the first quotient value table. The method for operating a floating-point divider according to claim 9, wherein the first multiplexer is operated to select the second quotient corresponding to the corresponding one of the plurality of second quotient values to be measured. The third quotient candidate corresponding to the third partial remainder candidate is used as the third quotient. The floating point divider operation method of claim 9, further comprising: providing a second quotient value table; and querying the second quotient value table in the first round operation of the floating point divider The first quotient value is supplied to the divisor and the divisor. The method for operating a floating point divider according to claim 9 of the patent application, further comprising: providing a quotient value converter, and providing each of the M bit information in each round of operations The first quotient value and the second quotient value conversion are combined into a quotient value of 2M bits, and the above M is a positive integer. The method for operating a floating point divider according to claim 9, further comprising: providing a second multiplexer, switching the output of the first multiplexer in the subsequent round operation of the first round of the floating point divider The third quotient is used as the first quotient value, and the remainder of the third part is output as the remainder of the first part. The method for operating a floating-point divider as described in claim 9 further includes: determining, according to the third-part remainder candidate, the second quotient, the divisor, and the plurality of third quotient values to be measured Generating a plurality of fourth partial remainder candidates; querying the first quotient value table, supplying a fourth partial remainder candidate corresponding to the fourth remainder candidate and the divisor of the fourth quotient candidate; and using the first multiplexer And selecting a fourth quotient candidate to output the third quotient value as a fourth quotient value, wherein the third quotient value to be measured is included in the first quotient value table. The method for operating a floating-point divider as described in claim 9 further includes: providing a quotient converter, wherein each of the rounds of operations provides the first quotient of the M-bit information, the first The two quotient values and the third quotient value conversion are combined into a quotient of 3M bits, and the above M is a positive integer. The method for operating the floating point divider as described in claim 14 of the patent application further includes: Generating a fourth partial remainder according to the third partial remainder, the divisor, and the third quotient value; and providing a second multiplexer in the subsequent round operation of the floating point divider following the first round of operations And switching the fourth quotient value as the first quotient value, and outputting the fourth part remainder as the first part remainder.