TWI592788B - Multi-phase clock generator - Google Patents

Description

Multiphase clock generator

The present invention relates to a multi-phase clock generator, and more particularly to a multi-phase clock generator having a built-in two delay phase locked loop.

In an integrated circuit, each cycle of the clock typically needs to be divided into multiple phases so that the digital circuit can select a phase from multiple phases to sample the data. In order to achieve the above functions, the integrated circuit usually has to be configured with a multi-phase clock generator.

Figure 1 is a block diagram of a conventional multi-phase clock generator. As shown in FIG. 1, the conventional multi-phase clock generator 100 generates an output clock signal clk12 having 256 phase selections according to the 8-bit digital signal S1. The delay locked loop 110 generates 256 phase clock signals P0~P255 according to the input clock signal clk11. In addition, the phase selector 120 selects an output from the 256 phase clock signals P0 to P255 according to the digital signal S1 as the output clock signal clk12. In other words, the multi-phase clock generator 100 is composed of a single delay phase-locked loop 110 and a single phase selector 120, and the delay-locked loop 110 must simultaneously generate 256 phase clock signals to cause the multi-phase clock generator. 100 has 256 phase selections.

However, in the conventional architecture, the delay phase-locked loop 110 must generate 256 phase clock signals by serially connecting 256 delay elements. Therefore, when the divided phases are large, the layout area and power consumption of the conventional multi-phase clock generator 100 will be large. In the worst case, it will even limit the maximum operating frequency of the entire circuit. In addition, when the divided phases are excessive, the input buffer and the multiplexer built in the phase selector 120 are also increased, thereby causing the layout area and power consumption of the conventional multi-phase clock generator 100 to be increased again. .

The present invention provides a multi-phase clock generator with built-in two delay phase-locked loops, thereby reducing the layout area and power consumption of the multi-phase clock generator.

The invention provides a multi-phase clock generator comprising a first delay phase locked loop, a reference signal generator and a second delay phase locked loop. The first delay phase-locked loop generates 2 ^N phase clock signals according to the input clock signal, and N is a positive integer. The reference signal generator selects the i-th and i+1th phase clock signals from the 2 ^N phase clock signals according to the digital signal, and the reference signal is generated in the 2 ^M clock cycles of the input clock signal. The device selects an output from the ith and i+1th phase clock signals according to the digital signal in each clock cycle as a reference clock signal, where i is an integer and 1≦i≦(2 ^N -1) , M is a positive integer. The second delay phase-locked loop delays the first phase clock signal generated by the first delay phase-locked loop according to the phase difference between the reference clock signal and the output clock signal, and outputs the output clock signal.

In an embodiment of the invention, the resolution of the digital signal is N+M bits. In addition, the reference signal generator selects the i-th and i+1-th phase clock signals from the 2 ^N phase clock signals according to the N+M to M+1th bits in the digital signal. Thereafter, the reference signal generator selects an output from the ith and i+1th phase clock signals in each clock cycle according to the Mth to the first bit in the digital signal.

In an embodiment of the present invention, the reference signal generator uses triangulation integral modulation to control the i-th and i+1th phase clock signals as reference clock signals in the 2 ^M clock cycles. proportion.

In an embodiment of the invention, the reference signal generator includes a first multiplexer, a second multiplexer, a delta-sigma modulator, and a third multiplexer. The first multiplexer receives the 2 ^N phase clock signals, and outputs the i-th phase clock signal according to the N+M to M+1th bits of the digital signal. The second multiplexer receives the 2 ^N phase clock signals, and outputs an i+1th phase clock signal according to the N+Mth to the M+1th bits of the digital signal. The delta-sigma modulator receives the Mth to the first bit and the integrated clock signal in the digital signal, and updates the modulation signal in each clock cycle. The third multiplexer selects an output from the ith and i+1th phase clock signals according to the modulation signal as a reference clock signal.

In an embodiment of the invention, the second delay phase locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage controlled delay line. The phase detector detects a phase difference between the reference clock signal and the output clock signal, and generates a plurality of switching signals accordingly. The charge pump generates a control current based on these switching signals. The low pass filter receives the control current and accordingly generates a control voltage. The voltage controlled delay line delays the first phase clock signal generated by the first delay phase locked loop according to the control voltage, and generates an output clock signal accordingly.

Based on the above, the present invention generates 2 ^N phase clock signals through the first delay phase locked loop, and first divides the period of the input clock signal into 2 ^N preset phases. In addition, the present invention further divides each preset phase into 2 ^M sub-phases by reference to the signal generator and the second delay-locked loop. In this way, the output clock signal generated by the multi-phase clock generator of the present invention has 2 ^N+M phase selections, thereby reducing the layout area and power consumption of the multi-phase clock generator.

The above described features and advantages of the present invention will be more apparent from the following description.

2 is a block diagram of a multi-phase clock generator in accordance with an embodiment of the present invention. Referring to FIG. 2, the multi-phase clock generator 200 includes a first delay phase locked loop 210, a reference signal generator 220, and a second delay phase locked loop 230. The first delay phase-locked loop 210 generates 2 ^N phase clock signals according to an input clock signal clk_in, where N is a positive integer. For example, the present embodiment takes N=4 as an example, so the first delay phase-locked loop 210 generates 16 phase clock signals PH[0]~PH[15].

In addition, the first delay phase-locked loop 210 outputs the phase clock signals PH[0]~PH[15] in a parallel manner, so the reference signal generator 220 can simultaneously receive the phase clock from the first delay-locked loop 210. Signal PH[0]~PH[15]. In addition, FIG. 3 is a timing diagram of signals according to an embodiment of the present invention. As shown in FIG. 3, the periods of the input clock signal clk_in and the phase clock signals PH[0]~PH[15] are both T3, and This is defined as the clock cycle T3. In addition, the two adjacent phase clock signals in the phase clock signals PH[0]~PH[15] are separated by a preset phase P3. For example, the phase difference between two adjacent phase clock signals PH[1] and PH[2] is P3.

On the other hand, the reference signal generator 220 receives the digital signal SEL having N+M bits, where N and M are positive integers. In addition, the reference signal generator 220 selects the i th and i+1th phase clocks from the 2 ^N phase clock signals according to the N+M to M+1th bits in the digital signal SEL. Signal, where i is an integer and 1≦i≦(2 ^N -1). Furthermore, in the 2 ^M clock cycle T3, the reference signal generator 220 will follow the i-th and the i+1th phase in each clock cycle according to the Mth to the first bit in the digital signal SEL. Select an output from the pulse signal as a reference clock signal clk_ref. In addition, the reference signal generator 220 uses delta-sigma modulation to control the ratio of the i-th and i+1-th phase clock signals as reference clock signals in the 2 ^M clock cycles. .

For example, taking N=M=4 as an example, the resolution of the digital signal SEL is 8 bits. In addition, the reference signal generator 220 selects adjacent two-phase clock signals from the phase clock signals PH[0]~PH[15] according to the first four bits SEL[8:5] of the digital signal SEL. For example: phase clock signals PH[1] and PH[2]. In addition, when the reference clock signal clk_ref is composed of one of the phase clock signals PH[1] and PH[2], the reference signal generator 220 according to the digital signal SEL during the 16 clock periods T3. The last four bits SEL[4:1] are selected from the phase clock signals PH[1] and PH[2] as the reference clock signal clk_ref in each clock cycle.

It should be noted that the reference signal generator 220 controls the phase clock signals PH[1] and PH[2] to be output as the reference clock signal clk_ref in 16 clock cycles T3 in a triangular integral modulation manner. proportion. That is, the reference signal generator 220 selectively outputs the phase clock signal PH[1] or the phase clock signal PH[2] in a triangular integral modulation manner. Therefore, when the bit value of SEL[4:1] is higher, the number of times of the phase clock signal PH[2] appears in the 16 clock cycles T3. In contrast, when the bit value of SEL[4:1] is lower, the number of times of the phase clock signal PH[1] appears in the 16 clock periods T3. For example, when the bit value of SEL[4:1] is 0, the reference clock signal clk_ref output by the reference signal generator 220 is used by the phase clock signal PH[1] in the 16 clock periods T3. Composition.

On the other hand, in the 2 ^M clock cycle T3, the second delay phase-locked loop 230 sequentially receives the reference clock formed by the ith phase clock signal or the i+1th phase clock signal. Signal clk_ref. In addition, the second delay phase locked loop 230 delays the first phase clock signal PH[0] according to the phase difference between the reference clock signal clk_ref and the output clock signal clk_out, and locks to adjust the output clock signal clk_out.

The operation of the reference signal generator 220 and the second delay phase locked loop 230 will be further described below by taking N=M=4 as an example. Here, when the bit value of the first four bits SEL[8:5] of the digital signal SEL is 0, the reference clock signal clk_ref will be the phase clock signal PH[0] or the phase clock signal PH[ 1] is composed. In addition, the reference clock signal clk_ref transmitted to the second delay phase locked loop 230 may have 16 different combinations within 16 clock cycles T3. In addition, the 16 different combinations can be controlled by the last four bits SEL[4:1] of the digital signal SEL, thereby causing the second delay phase locked loop 230 to be at the phase clock signal PH[0] and PH. Further, 16 sub-phases are divided between [1].

For example, when the bit value of SEL[4:1] is 0, the reference clock signal clk_ref sequentially transmitted to the second delay phase-locked loop 230 is phase clocked in 16 clock cycles T3. The signal PH[0] is composed. Therefore, after 16 clock cycles T3 have elapsed, the output clock signal clk_out locked by the second delay phase locked loop 230 will be synchronized with the phase clock signal PH[0]. Furthermore, when the bit value of SEL[4:1] is 1, the reference signal generator 220 transmits the reference clock signal clk_ref formed by the clock signal PH[0] through one clock period T3, and The reference clock signal clk_ref formed by the clock signal PH[1] is transmitted through 15 clock cycles T3. In this way, after 16 clock cycles T3, the output clock signal clk_out locked by the second delay phase locked loop 230, the rising edge of which will be between the phase clock signals PH[0] and PH[1]. Between rising edges.

In addition, as the bit value of SEL[4:1] becomes larger, the rising edge of the output clock signal clk_out will gradually move away from the rising edge of the phase clock signal PH[0], but it is still in the phase clock signal PH. The rising edge of [0] is between the rising edge of the phase clock signal PH[1]. In other words, when the bit value of the first four bits SEL[8:5] of the digital signal SEL is 0, the bit value of the last four bits SEL[4:1] of the digital signal SEL changes, and the second The delay phase locked loop 230 will further divide the 16 subphases between the phase clock signals PH[0] and PH[1]. That is, the preset phase P3 between the phase clock signals PH[0] and PH[1] can be equally divided into 16 sub-phases.

Similarly, when the bit value of the first four bits SEL[8:5] of the digital signal SEL is 1, the reference clock signal clk_ref will be the phase clock signal PH[1] or the phase clock signal PH[ 2] constitutes. In addition, as the bit value of the four-bit SEL[4:1] after the digital signal SEL changes, the second delay-locked loop 230 will further extend between the phase clock signals PH[1] and PH[2]. The ground is divided into 16 sub-phases. That is, the preset phase P3 between the phase clock signals PH[1] and PH[2] can be equally divided into 16 sub-phases. By analogy, the preset phase P3 between the phase clock signals PH[2] and PH[3] can be equally divided into presets between 16 subphases, phase clock signals PH[3] and PH[4]. Phase P3 will be equally divided into 16 subphases, ..., and so on.

In other words, the multi-phase clock generator 200 first generates 16 phase clock signals PH[0]~PH[15] through the first delay phase-locked loop 210, and first divides the period of the input clock signal clk_in into 16 segments. Preset phase P3. Thereafter, the multi-phase clock generator 200 further transmits the predetermined phase P3 into 16 sub-phases through the reference signal generator 220 and the second delay-locked loop 230. As a result, the output clock signal clk_out generated by the multi-phase clock generator 200 will have 256 phase selections.

It is worth mentioning that since the multi-phase clock generator 200 does not need to generate 256 phase clock signals at the same time, an output clock signal clk_out having 256 phase selections can be generated. Therefore, the layout area and power consumption of the multi-phase clock generator 200 can be reduced, thereby helping to reduce the production cost of the multi-phase clock generator 200.

Further, the second delay phase locked loop 230 includes a phase detector (PD) 231, a charge pump (CP) 232, a low pass filter (LPF) 233, and a voltage control. Voltage-Controlled Delay Line (VCDL) 234. The phase detector 231 is electrically connected to the reference signal generator 220 and the voltage controlled delay line 234. The charge pump 232 is electrically connected to the phase detector 231. Further, the low pass filter 233 is electrically connected between the charge pump 232 and the voltage controlled delay line 234.

In operation, the phase detector 231 detects a phase difference between the reference clock signal clk_ref and the output clock signal clk_out, and generates a plurality of switching signals accordingly. Furthermore, the charge pump 232 generates a control current I2 according to the plurality of switching signals, and the low-pass filter 233 is configured to receive the control current I2 and accordingly generate the control voltage V2. In addition, the voltage controlled delay line 234 delays the phase clock signal PH[0] according to the control voltage V2. Thereby, when the reference clock signal clk_ref lags behind the output clock signal clk_out, the charge pump 232 will lower the control current I2 according to the switching signal. At this time, the control voltage V2 generated by the low pass filter 233 will decrease as the control current I2 decreases.

Moreover, for the voltage controlled delay line 234, the smaller the control voltage V2, the greater the delay provided. Therefore, as the control voltage V2 decreases, the voltage controlled delay line 234 increases the delay of the phase clock signal PH[0], thereby causing the output clock signal clk_out to move forward along the time axis. On the contrary, when the reference clock signal clk_ref leads the output clock signal clk_out, the control current I2 generated by the charge pump 232 will increase, thereby raising the level of the control voltage V2. Thereby, as the control voltage V2 rises, the voltage controlled delay line 234 reduces the delay of the phase clock signal PH[0], thereby causing the output clock signal clk_out to move backward along the time axis.

4 is a block diagram of a reference signal generator in accordance with an embodiment of the present invention. Referring to FIG. 4, the reference signal generator 220 includes a first multiplexer 410, a second multiplexer 420, a third multiplexer 430, and a delta-sigma modulator 440. The third multiplexer 430 is electrically connected to the first multiplexer 410 and the second multiplexer 420. In addition, the delta-sigma modulator 440 is electrically connected to the third multiplexer 430.

In the overall operation, the first multiplexer 410 receives 2 ^N phase clock signals from the first delay phase locked loop 210. For example, taking N=M=4 as an example, the first multiplexer 410 receives 16 Phase clock signals PH[0]~PH[15]. In addition, the first multiplexer 410 outputs the i-th phase clock signal according to the N+Mth to the M+1th bits in the digital signal SEL, for example, SEL[8:5]. 4 shows the i-th phase clock signal by clk_lead. Furthermore, the second multiplexer 420 also receives 2 ^N phase clock signals from the first delay phase locked loop 210, for example, phase clock signals PH[0]~PH[15]. In addition, the second multiplexer 420 outputs the i+1th phase clock signal according to the N+M to M+1th bits in the digital signal SEL, for example, SEL[8:5]. 4 shows the i+1th phase clock signal by clk_lag.

The triangular integral modulator 440 receives the Mth to the first bit (eg, SEL[4:1]) and the integral clock signal clk_ig of the digital signal SEL, wherein the frequency of the integrated clock signal clk_ig is equal to the input clock. The frequency of the signal clk_in. In addition, the delta-sigma modulator 440 updates the modulation signal S4 during each clock cycle T3, and outputs the modulation signal S4 to the third multiplexer 430. Thereby, the third multiplexer 430 selects one of the i-th phase clock signal clk_lead and the i+1th phase clock signal clk_lag according to the modulation signal S4 as the reference clock signal clk_ref.

For example, when the bit value of the first four bits SEL[8:5] of the digital signal SEL is 0, the first multiplexer 410 selects the phase clock signal PH[0] and outputs it as The i-th phase clock signal clk_lead, and the second multiplexer 420 selects the phase clock signal PH[1] and outputs it as the i+1th phase clock signal clk_lag. Similarly, when the bit value of the first four bits SEL[8:5] of the digital signal SEL is 1, the first multiplexer 410 selects the phase clock signal PH[1] and outputs it as the first The i phase clock signals clk_lead, and the second multiplexer 420 selects the phase clock signal PH[2] and outputs it as the i+1th phase clock signal clk_lag. In other words, the two-phase clock signal constituting the reference clock signal clk_ref can be set through the first four bits SEL[8:5] of the digital signal SEL.

Furthermore, the delta-sigma modulator 440 determines the number of times the modulation signal S4 is set to logic 1/0 in the 16 clock cycles T3 according to the last four bits SEL[4:1] of the digital signal SEL. And the modulation signal S4 is updated in each clock cycle T3 according to the setting result. For example, when the bit value of SEL[4:1] is 0, the number of times the modulation signal S4 is set to logic 0 will be 16, and the number of times the modulation signal S4 is set to logic 1 will be 0.

Therefore, the delta-sigma modulator 440 updates the modulation signal S4 to a logic 0 during each clock cycle T3. In this way, in the 16 clock cycles T3, the third multiplexer 430 outputs the i-th phase clock signal clk_lead as the reference clock signal clk_ref. In addition, when the bit value of SEL[4:1] is higher, the number of times the modulation signal S4 is set to logic 1 will increase one by one. In this way, in the 16 clock cycles T3, the number of times when the reference clock signal clk_ref is formed by the (i+1)th phase clock signal clk_lag will also increase.

In summary, the present invention generates 2 ^N phase clock signals through the first delay phase-locked loop, and first divides the period of the input clock signal into 2 ^N preset phases. In addition, the present invention further divides each preset phase into 2 ^M sub-phases by reference to the signal generator and the second delay-locked loop. In this way, the output clock signal generated by the multi-phase clock generator of the present invention will have 2 ^N+M phase selections. Furthermore, since the multi-phase clock generator of the present invention only needs to generate 2 ^N phase clock signals at the same time, that is, there are 2 ^N+M phase selections, the layout area of the multi-phase clock generator of the present invention and Power consumption can be reduced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Traditional multiphase clock generator

110. . . Delayed phase locked loop

120. . . Phase selector

Clk11. . . Input clock signal

P0~P255. . . Phase clock signal

S1. . . Digital signal

Clk12. . . Output clock signal

200. . . Multiphase clock generator

210. . . First delay phase locked loop

220. . . Reference signal generator

230. . . Second delay phase locked loop

231. . . Phase detector

232. . . Charge pump

233. . . Low pass filter

234. . . Voltage controlled delay line

Clk_in. . . Input clock signal

PH[0]~PH[15]. . . Phase clock signal

SEL, SEL[4:1], SEL[8:5]. . . Digital signal

Clk_ref. . . Reference clock signal

I2. . . Control current

V2. . . Control voltage

Clk_out. . . Output clock signal

T3. . . Clock cycle

P3. . . Preset phase

410. . . First multiplexer

420. . . Second multiplexer

430. . . Third multiplexer

440. . . Triangular integral modulator

Clk_lead. . . I-th phase clock signal

Clk_lag. . . The i+1th phase clock signal

Clk_ig. . . Integral clock signal

S4. . . Modulation signal

Figure 1 is a block diagram of a conventional multi-phase clock generator.

2 is a block diagram of a multi-phase clock generator in accordance with an embodiment of the present invention.

3 is a timing diagram of signals in accordance with an embodiment of the present invention.

4 is a block diagram of a reference signal generator in accordance with an embodiment of the present invention.

200. . . Multiphase clock generator

210. . . First delay phase locked loop

220. . . Reference signal generator

230. . . Second delay phase locked loop

231. . . Phase detector

232. . . Charge pump

233. . . Low pass filter

234. . . Voltage controlled delay line

Clk_in. . . Input clock signal

PH[0]~PH[15]. . . Phase clock signal

SEL. . . Digital signal

Clk_ref. . . Reference clock signal

I2. . . Control current

V2. . . Control voltage

Clk_out. . . Output clock signal

Claims (9)

A multi-phase clock generator includes: a first delay phase-locked loop, generating 2 ^N phase clock signals according to an input clock signal, N being a positive integer; a reference signal generator, according to a digital signal Selecting the i-th and i+1th phase clock signals from the phase clock signals, and in the 2 ^M clock cycles of the input clock signal, the reference signal generator is based on the digital signals Selecting an output from the i-th and i+1th phase clock signals in the clock cycle, and controlling the i-th and i-th-th phase clock signals to be output in the 2 ^M clock cycles as a reference clock signal ratio, according to which the reference clock signal is constructed, wherein i is an integer and 1≦i≦(2 ^N -1), M is a positive integer; and a second delay phase-locked loop is Receiving the reference clock signal in sequence within 2 ^M clock cycles, and delaying the first phase clock signal according to the phase difference between the reference clock signal and an output clock signal, and outputting the output clock signal . The multi-phase clock generator according to claim 1, wherein the resolution of the digital signal is N+M bits, and the reference signal generator is based on the N+M to the M+ of the digital signal. 1 bit, and selecting the i-th and i+1th phase clock signals from the phase clock signals, and the reference signal generator is based on the Mth to the first bit in the digital signal, During the clock cycles, an output is selected from the i-th and i+1th phase clock signals. Multi-phase clock generation as described in item 2 of the patent application scope The first bit of the digital signal is a least significant bit, and the N+M bit of the digital signal is a most significant bit. The multi-phase clock generator of claim 2, wherein the reference signal generator comprises: a first multiplexer, receiving the phase clock signals, and according to the N+ of the digital signals M to the M+1th bit output the i-th phase clock signal; a second multiplexer receives the phase clock signals according to the N+M to M+1th bits of the digital signal The i+1th phase clock signal; a triangular integral modulator receives the Mth to the first bit of the digital signal and an integral clock signal, and updates a tone in each of the clock cycles And a third multiplexer that selects an output from the i-th and i+1th phase clock signals according to the modulation signal as the reference clock signal. The multi-phase clock generator of claim 4, wherein the frequency of the integrated clock signal is equal to the frequency of the input clock signal. The multi-phase clock generator of claim 1, wherein the second delay-locked loop comprises: a phase detector for detecting a phase difference between the reference clock signal and the output clock signal, And generating a plurality of switching signals; a charging pump generates a control current according to the switching signals; a low pass filter receives the control current and generates a control accordingly And a voltage controlled delay line, delaying the first phase clock signal according to the control voltage, and generating the output clock signal accordingly. The multi-phase clock generator according to claim 1, wherein the first delay-locked loop outputs the phase clock signals in a side-by-side manner. The multi-phase clock generator of claim 1, wherein two adjacent phase clock signals of the phase clock signals are separated by a predetermined phase. The multi-phase clock generator of claim 1, wherein the reference signal generator controls the i-th and i+1-th phase clock signals in the 2 ^M clocks by using trigonometric integral modulation The ratio of the reference clock signal in the period.