TWI585945B - An esd protection device with gated diode - Google Patents

Description

Electrostatic discharge protection component with thyristor diode

The invention relates to a protection technology for electrostatic discharge, and is an electrostatic discharge protection component based on a laterally controlled rectifier.

In recent years, although semiconductor technology continues to advance, Electro-Static Discharge (ESD) protection is becoming more and more difficult to handle. In general, the lateral-controlled parallel rectifier (SCR) is considered to be the most effective ESD protection component because it is compared to other protection components. It has a preferred electrostatic body discharge mode (HBM), a failure threshold voltage, and a second breakdown current (I _t2 ).

However, the holding voltage (V _H ) of the step-controlled rectifier is lower than the operating voltage of the above-mentioned circuit component compared to the circuit component to be protected, so that under the normal operation of the above-mentioned circuit component External noise is easy to trigger the rectifier rectifier and cause it to enter a latch-up state, which will further cause malfunction or permanent damage to the above circuit components. In addition, current techniques are difficult to achieve if the voltage-controlled rectifier is fully immune to latch-up and the circuit component to be protected is at a higher operating voltage (eg, 3.3 V or higher). Therefore, it is necessary to develop new electrostatic discharge protection technologies to improve the above problems.

In order to achieve the object, according to an aspect of the present invention, an embodiment provides an electrostatic discharge protection component including: an anode terminal and a cathode terminal; and a floating gated rectifier unit, including: a P-type semiconductor substrate and a formation An N-type semiconductor well region in the P-type semiconductor substrate; a first insulating region and a second insulating region are formed in the N-type semiconductor well region; a first N ⁺ -type semiconductor region and a floating first a P ⁺ -type semiconductor region formed between the first insulating region and the second insulating region; a gate capacitance formed between the first N ⁺ -type semiconductor region and the floating first P ⁺ -type semiconductor region An insulating layer and a conductive layer formed on the insulating layer; a third insulating region and a fourth insulating region are formed in the P-type semiconductor substrate; and a second N ⁺ -type semiconductor region is formed in Between the second insulating region and the third insulating region; and a second P ⁺ -type semiconductor region formed between the third insulating region and the fourth insulating region; and a trigger switch unit including a filter , having a first end, a second end, and a third end, One end is connected to the anode end and serves as an input end of the signal to be filtered, and the second end is connected to the gate capacitance of the step-controlled rectifying unit and serves as an output end of the filtered signal, and the third end is grounded; The first N ⁺ -type semiconductor region is connected to the anode terminal, the second N ⁺ -type semiconductor region and the second P ⁺ -type semiconductor region are connected to the cathode terminal, and the floating first P ⁺ -type semiconductor region is in contact with the first The second insulating region and the N-type semiconductor well region are not connected to other locations.

According to another aspect of the present invention, an embodiment provides an electrostatic discharge protection component including: an anode terminal and a cathode terminal; and a floating gated rectifier unit, including: a P-type semiconductor substrate and a P-type semiconductor substrate formed thereon An N-type semiconductor well region in the semiconductor substrate; a first insulating region, a second insulating region and a third insulating region are formed in the N-type semiconductor well region; and a first N ⁺ -type semiconductor region is formed in the semiconductor region Between the first insulating region and the second insulating region; a first P-type semiconductor region formed between the second insulating region and the third insulating region; and a fourth insulating region formed on the P-type semiconductor a floating second N ⁺ -type semiconductor region and a second P ⁺ -type semiconductor region formed between the third insulating region and the fourth insulating region; and a gate capacitance formed on the floating Between the second N ⁺ -type semiconductor region and the second P ⁺ -type semiconductor region, comprising an insulating layer and a conductive layer formed on the insulating layer; and a trigger switch unit including a filter having a first One end, a second end and a third end, the first end is connected to the And as an input terminal of the signal to be filtered, and a gate connected to the second end of the capacitor silicon controlled rectifier unit and as an output signal after being filtered, and the third terminal; wherein the first N ^{a +} -type semiconductor region and the first P ⁺ -type semiconductor region are connected to the anode terminal, the second P ⁺ -type semiconductor region is connected to the cathode terminal, and the floating second N ⁺ -type semiconductor region is in contact with the third insulating region and The P-type semiconductor substrate is not connected to other places.

100, 200, 300‧‧‧ Electrostatic discharge protection components

110‧‧‧Anode end

120‧‧‧ cathode end

130‧‧‧Controlled rectifier unit

131‧‧‧P type semiconductor substrate

132‧‧‧N type semiconductor well area

1331‧‧‧First insulation zone

1332‧‧‧Second insulation zone

1333‧‧‧3rd insulation zone

1334‧‧‧4th insulation zone

1341‧‧‧First N ⁺ type semiconductor region

1342‧‧‧Second N ⁺ type semiconductor region

1351‧‧‧First P ⁺ type semiconductor region

1352‧‧‧Second P ⁺ type semiconductor region

136‧‧‧ gate capacitance

1361‧‧‧Insulation

1362‧‧‧ Conductive layer

160‧‧‧Trigger switch unit

C‧‧‧ capacitor

R‧‧‧resistance

Fig. 1 is a block diagram showing an electrostatic discharge protection element according to an embodiment of the present invention.

Fig. 2 is a schematic view of an electrostatic discharge protection element according to a first embodiment of the present invention.

Figure 3 is a schematic view of an electrostatic discharge protection element in accordance with a second embodiment of the present invention.

In order to further understand and understand the features, objects and functions of the present invention, the embodiments of the present invention are described in detail with reference to the drawings. In all of the specification and the drawings, the same component numbers will be used to designate the same or similar components.

In the description of the various embodiments, when an element is described as "above/on" or "below/under" another element, it is meant to be directly or indirectly above or below the other element. , which may contain other elements set in between; the so-called "directly" means that no other intermediary elements are set in between. The descriptions of "Upper/Upper" or "Bottom/Lower" are based on the schema, but also include other possible direction changes. The so-called "first", "second", and "third" are used to describe different elements that are not limited by such predicates. In order to say Convenience and clarity of the disclosure, the thickness or size of each element in the drawings is expressed in an exaggerated or omitted or schematic manner, and the dimensions of the elements are not completely their actual dimensions.

1 is a block diagram of an electrostatic discharge protection component 100 in accordance with an embodiment of the present invention. The ESD protection component 100 is an electronic component having two connection terminals: an anode terminal 110 and a cathode terminal 120, and includes two main circuit units: a floating control rectifier unit 130 and a trigger switch unit 160, the main functions of which are It is used to prevent external integrated circuit components from being damaged by electrostatic discharge (ESD). The anode end 110 and the cathode end 120 are for connection to an external circuit component of the desired electrostatic discharge protection. The floating control rectifier unit 130 is based on a lateral SCR which is commonly used for electrostatic discharge protection, and changes its circuit structure to a floating state to improve its electrostatic discharge protection performance. In addition, the floating control rectifier unit 130 is further equipped with the trigger switch unit 160 to provide a trigger switch mechanism, so that the ESD protection component 100 can determine whether to activate according to whether the external circuit component is subjected to an electrostatic discharge attack. The floating connection controls the electrostatic discharge protection function of the rectifying unit 130. The internal circuit structure and operation of the floating-controlled voltage-controlled rectifying unit 130 and the trigger switching unit 160 will be described in detail below according to different embodiments.

2 is a schematic diagram of an ESD protection component 200 having a thyristor diode according to a first embodiment of the present invention; wherein block 130 illustrates a component cross-sectional structure of the floating 矽 controlled rectification unit 130 and its equivalent The circuit diagram, and block 160 illustrates the circuit configuration of the trigger switch unit 160. The controlled rectifier unit 130 is a semiconductor component constructed on a P-type semiconductor substrate 131, and includes: an N-type semiconductor well region 132 formed in the P-type semiconductor substrate 131, and four semiconductor regions for isolating the respective semiconductor regions. An insulating region (a first insulating region 1331 and a second insulating region 1332 are formed in the N-type semiconductor well region 132, a third insulating region 1333 and a fourth insulating region 1334 are formed in the P-type semiconductor substrate), and two N ⁺ a semiconductor region and two P ⁺ -type semiconductor regions (the first N ⁺ -type semiconductor region 1341 and the first P ⁺ -type semiconductor region 1351 are formed between the first insulating region 1331 and the second insulating region 1332, the second N ^{a +} -type semiconductor region 1342 is formed between the second insulating region 1332 and the third insulating region 1333, and a second P ⁺ -type semiconductor region 1352 is formed between the third insulating region 1333 and the fourth insulating region 1334, And a gate capacitor 136 (formed between the first N ⁺ -type semiconductor region 1341 and the first P ⁺ -type semiconductor region 1351). In the present embodiment, the gate capacitor 136 includes an insulating layer 1361 formed on the N-type semiconductor well region 132 and a conductive layer 1362 formed on the insulating layer 1361. The conductive layer 1362 is formed by the element structure. The insulating layer 1361 and the N-type semiconductor well region 132 may form a metal/oxide layer/semiconductor capacitor (referred to as a metal oxide half capacitor), and the potential difference between the conductive layer 1362 and the N-type semiconductor well region 132 increases. When large, the amount of stored charge of the gate capacitor 136 will increase.

As shown in FIG. 2, the first P ⁺ -type semiconductor region 1351, the N-type semiconductor well region 132, and the P-type semiconductor substrate 131 can equivalently form a PNP-type bipolar junction transistor (Bipolar Junction Transistor). , referred to as BJT for short, and the second N ⁺ -type semiconductor region 1342, the P-type semiconductor substrate 131 and the N-type semiconductor well region 132 can equivalently form an NPN-type bipolar junction transistor; a P ⁺ -type semiconductor region 1351 , the N-type semiconductor well region 132 and the P-type semiconductor substrate 131 are respectively an emitter, a base and a collector of the PNP-type bipolar junction transistor, and the second N ⁺ -type semiconductor The region 1342, the P-type semiconductor substrate 131 and the N-type semiconductor well region 132 are respectively an emitter, a base and a collector of the NPN-type bipolar junction transistor. Therefore, the two PNP type and NPN type bipolar junction transistors can be combined into a PNPN type of controlled rectifier.

In this embodiment, the first N ⁺ -type semiconductor region 1341 is connected to the anode terminal 110, and the second N ⁺ -type semiconductor region 1342 and the second P ⁺ -type semiconductor region 1352 are connected to the cathode terminal 120 in common. The first P ⁺ -type semiconductor region 1351 floats, that is, the first P ⁺ -type semiconductor region 1351 is not connected to the second insulating region 1332 and the N-type semiconductor well region 132 except for structurally contacting Other circuits or components. In addition, the floating first P ⁺ -type semiconductor region 1351, the N-type semiconductor well region 132 and the first N ⁺ -type semiconductor region 1341 can equivalently form a reverse biased diode D, and the diode The anode of D is connected to the emitter of the PNP-type bipolar junction transistor, and the gold-oxide half capacitor 136 and the reverse biased diode D constitute a gate polarization diode. As shown in FIG. 2, the N-type semiconductor well region 132 can equivalently form a resistor R _N , and the P-type semiconductor substrate 131 can equivalently form a resistor R _P . On the other hand, the trigger switch unit 160 may be a filter element having three end points (first end to third end): the first end is connected to the anode end 110 and serves as an input end of a signal to be filtered. The two ends are connected to the gate capacitance 136 of the step-controlled rectifying unit 130 as an output end of the filtered signal, and the third end is grounded as shown in FIG.

In general, when an electrostatic discharge occurs, an ESD pulse of about 100 to 200 ns is generated between the anode terminal 110 and the cathode terminal 120. For the waveform and frequency of the ESD pulse that the external integrated circuit component to be protected may suffer, we can design the trigger switch unit 160 to be a filter having an appropriate time constant for discriminating or confirming entry from the anode terminal 110. Is an ESD pulse or other signal. In this embodiment, the trigger switch unit 160 is a series connection of a capacitor C and a resistor R. The resistor R is between the first end and the second end of the trigger switch unit 160, and the capacitor C is between the second end of the trigger switch unit 160 and the third end.

Please refer to the equivalent circuit of the controlled rectifier unit 130 and the circuit of the trigger switch unit 160 shown in FIG. 2. When the integrated circuit is in normal operation, no ESD pulse enters the anode terminal 110, and the trigger is triggered. The switching unit 160 is not actuated, and the gate capacitance 136 is also turned off, so that the controlled rectification unit 130 is not actuated without affecting the normal operation of the external integrated circuit. Conversely, when the ESD protection device 100 is subjected to an electrostatic discharge attack, an ESD pulse will enter the anode terminal 110, so that the capacitor C in the trigger switch unit 160 is short-circuited and current flows through the resistor R, and A voltage drop greater than a threshold is generated between the anode terminal 110 and the second end, thereby generating an electrically inverted hole layer channel below the gate capacitance 136 to trigger the collapse of the reverse bias diode D early. Turning on, and then starting the floating controlled rectifier unit 130 to perform electrostatic discharge protection mechanism, it is particularly noted that the breakdown conduction performance of the gate polarization diode in the present invention is higher than that of the conventional gateless polarization diode Faster and better.

For the floating-controlled voltage-controlled rectifying unit 130, the purpose of floating the first P ⁺ -type semiconductor region 1351 is to turn off the electrostatic discharge protection element 100 during normal operation of the integrated circuit, and the voltage-controlled rectifying unit 130 can Maintaining an open state between its anode (the first N ⁺ -type semiconductor region 1341) and the cathode (the second P ⁺ -type semiconductor region 1352); that is, its holding voltage (V _H ) is sufficient to exceed The power supply voltage, and the controlled rectifier unit 130 is hardly triggered or activated to enhance the immunity of the latch-up. In this embodiment, the trigger switch unit 160 is configured to trigger the reverse bias diode D in the early stage of the electrostatic discharge attack, so that the reverse bias diode D is turned on and turned on early, thereby reaching the floating connection early. The secondary breakdown current/I _{t2 of the} rectifying unit 130 is controlled. When the ESD pulse strikes the trigger switch unit 160, the ESD pulse causes the capacitor C to be short-circuited, and the current conduction through the resistor R generates a voltage drop when the voltage from the anode terminal 110 to the gate of the gate capacitor 136 is greater than When the threshold voltage (|V _TP |), the gate capacitance 136 generates a reverse hole layer on the surface of the N-type semiconductor well region 132, and the hole charges are injected into the N-type semiconductor well region 132 and the P ⁺ -type semiconductor region. The PN junction region formed between 1351 makes the reverse biased polarization diode D easy to collapse and conduct, and the breakdown conduction performance of the gate polarization diode is faster than the conventional gateless polarization diode. better. On the other hand, in the case of the normal operation of the integrated circuit, the anode terminal 110 is applied with a DC power supply voltage, the capacitor C is quickly charged and then the circuit is closed, and no current flows through the resistor R and no voltage drop occurs. The pole capacitor 136 is turned off, and the reverse biasing diode D cannot be triggered or turned on; at this time, the holding voltage of the step-controlled rectifying unit 130 is higher than the power source voltage. Therefore, the trigger switch unit 160 may be subjected to an electrostatic discharge attack or a general circuit operation condition to determine whether to trigger or turn on the reverse bias polarization diode D to achieve electrostatic discharge protection. Purpose, and in the case of normal operation can provide good latch-up immunity.

3 is a schematic diagram of an ESD protection component 300 having a thyristor diode according to a second embodiment of the present invention; wherein block 130 illustrates the component cross-sectional structure of the floating 矽 controlled rectification unit 130 and its equivalent The circuit diagram, and block 160 illustrates the circuit configuration of the trigger switch unit 160. The floating-controlled voltage-controlled rectifying unit 130 is a semiconductor element constructed on a P-type semiconductor substrate 131, and includes: an N-type semiconductor well region 132 formed in the P-type semiconductor substrate 131, and four isolation semiconductors. The insulating region of the region (the first insulating region 1331 and the second insulating region 1332 are formed in the N-type semiconductor well region 132, the third insulating region 1333 and the fourth insulating region 1334 are formed in the P-type semiconductor substrate), and two An N ⁺ -type semiconductor region and two P ⁺ -type semiconductor regions (the first N ⁺ -type semiconductor region 1341 is formed between the first insulating region 1331 and the second insulating region 1332), and the first P ⁺ -type semiconductor region 1351 is formed Between the second insulating region 1332 and the third insulating region 1333, a second N ⁺ -type semiconductor region 1342 and a second P ⁺ -type semiconductor region 1352 are formed between the third insulating region 1333 and the fourth insulating region 1334 And a gate capacitor 136 (formed between the second N ⁺ -type semiconductor region 1342 and the second P ⁺ -type semiconductor region 1352). In this embodiment, the gate capacitor 136 includes an insulating layer 1361 formed on the P-type semiconductor substrate 131 and a conductive layer 1362 formed on the insulating layer 1361. The conductive layer 1362 is formed by the element structure. The insulating layer 1361 and the P-type semiconductor substrate 131 can form a metal/oxide layer/semiconductor capacitor. When the potential difference between the conductive layer 1362 and the P-type semiconductor substrate 131 increases, the capacitance of the gate capacitor 136 increases. The value will increase accordingly.

As shown in FIG. 3, the first P ⁺ -type semiconductor region 1351, the N-type semiconductor well region 132, and the P-type semiconductor substrate 131 can equivalently form a PNP-type bipolar junction transistor, and the first The N ⁺ -type semiconductor region 1342, the P-type semiconductor substrate 131 and the N-type semiconductor well region 132 can equivalently form an NPN-type bipolar junction transistor; wherein the first P ⁺ -type semiconductor region 1351 The N-type semiconductor well region 132 and the P-type semiconductor substrate 131 are respectively an emitter, a base and a collector of the PNP-type bipolar junction transistor, and the second N ⁺ -type semiconductor region 1342 and the P-type semiconductor substrate 131 and the N-type semiconductor well region 132 are respectively an emitter, a base and a collector of the NPN-type bipolar junction transistor. Therefore, the two PNP type and NPN type bipolar junction transistors can be combined into a PNPN type of controlled rectifier.

In this embodiment, the first N ⁺ -type semiconductor region 1341 and the first P ⁺ -type semiconductor region 1351 are commonly connected to the anode terminal 110, and the second P ⁺ -type semiconductor region 1352 is connected to the cathode terminal 120, and The second N ⁺ -type semiconductor region 1342 is floating, that is, the floating second N ⁺ -type semiconductor region 1342 is not structurally connected to the third insulating region 1333 and the P-type semiconductor substrate 131. Connect to other circuits or components. In addition, the second P ⁺ -type semiconductor region 1352, the P-type semiconductor substrate 131, and the floating second N ⁺ -type semiconductor region 1342 can equivalently form a reverse biased diode D, and the diode D The cathode is connected to the emitter of the NPN-type bipolar junction transistor, and the gold-oxide half capacitor 136 and the reverse biased diode D form a gate polarization diode. As shown in FIG. 3, the N-type semiconductor well region 132 can equivalently form a resistor R _N , and the P-type semiconductor substrate 131 can equivalently form a resistor R _P . On the other hand, the trigger switch unit 160 may be a filter element having three end points (first end to third end): the first end is connected to the anode end 110 and serves as an input end of a signal to be filtered. The two ends are connected to the gate capacitance 136 of the controlled rectifier unit 130 as an output end of the filtered signal, and the third end is connected to the cathode end 120, as shown in FIG. In this embodiment, the trigger switch unit 160 is a series consisting of a capacitor C and a resistor R. The capacitor C is interposed between the first end and the second end of the filter 161, and the resistor R Between the second end of the filter 161 and the third end.

Please refer to the equivalent circuit of the floating controlled rectifier unit 130 and the circuit of the trigger switch unit 160 shown in FIG. 3. When the integrated circuit is in normal operation, no ESD pulse enters the anode terminal 110. A power supply voltage is applied to the anode terminal 110. The capacitor C of the trigger switch unit 160 is quickly charged and then the circuit is closed. No current flows through the resistor R and no voltage drop occurs. Therefore, the trigger switch unit 160 is not actuated. The gate capacitance 136 is also turned off, so that the voltage controlled rectifier unit 130 is also not actuated, without affecting the normal operation of the external integrated circuit. Conversely, when the ESD protection device 100 is subjected to an electrostatic discharge attack, an ESD pulse will enter the anode terminal 110, so that the capacitor C in the trigger switch unit 160 is short-circuited and the current passes through the resistor R, and in the first A voltage drop greater than a threshold is generated between the second terminal and the cathode terminal 120, thereby generating an electrically inverted electronic layer channel under the gate capacitance 136, which triggers the collapse of the reverse bias diode D to be turned on early. The controlled rectifier unit 130 is then activated to perform a protection mechanism for electrostatic discharge. Similarly, the breakdown conduction performance of the gate polarization diode in this embodiment is faster and better than the conventional gateless polarization diode. Therefore, the trigger switch unit 160 may be subjected to an electrostatic discharge attack or a general circuit operation condition to determine whether to trigger or turn on the reverse bias polarization diode D to achieve electrostatic discharge protection. Purpose, and in the case of normal operation can provide good latch-up immunity.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto. It is to be understood that the scope of the present invention is not limited by the spirit and scope of the present invention, and should be considered as a further embodiment of the present invention.

100,200‧‧‧Electrostatic discharge protection components

110‧‧‧Anode end

120‧‧‧ cathode end

130‧‧‧Controlled rectifier unit

131‧‧‧P type semiconductor substrate

132‧‧‧N type semiconductor well area

1331‧‧‧First insulation zone

1332‧‧‧Second insulation zone

1333‧‧‧3rd insulation zone

1334‧‧‧4th insulation zone

1341‧‧‧First N ⁺ type semiconductor region

1342‧‧‧Second N ⁺ type semiconductor region

1351‧‧‧First P ⁺ type semiconductor region

1352‧‧‧Second P ⁺ type semiconductor region

136‧‧‧ gate capacitance

1361‧‧‧Insulation

1362‧‧‧ Conductive layer

160‧‧‧Trigger switch unit

R _P R _N ‧‧‧Resistor

D‧‧‧ diode

PNP, NPN‧‧‧PEP type, NPN type bipolar junction transistor

Claims (10)

An electrostatic discharge protection component comprising: an anode terminal and a cathode terminal; a floating gated rectifier unit comprising: a P-type semiconductor substrate and an N-type semiconductor well region formed in the P-type semiconductor substrate; An insulating region and a second insulating region are formed in the N-type semiconductor well region; a first N ⁺ -type semiconductor region and a floating first P ⁺ -type semiconductor region are formed in the first insulating region and the first Between the two insulating regions; a gate capacitance formed between the first N ⁺ -type semiconductor region and the floating first P ⁺ -type semiconductor region, comprising an insulating layer and a conductive layer formed on the insulating layer a third insulating region and a fourth insulating region are formed in the P-type semiconductor substrate; a second N ⁺ -type semiconductor region is formed between the second insulating region and the third insulating region; and a second P ⁺ -type semiconductor region formed between the third insulating region and the fourth insulating region; and a trigger switch unit including a filter having a first end, a second end, and a third end The first end is connected to the anode end and serves as an input signal for filtering , The second end connected to the silicon controlled rectifier gate capacitance unit and as an output signal after being filtered, and the third terminal; wherein the first N ⁺ type semiconductor region connected to the anode terminal, the second a second N ⁺ -type semiconductor region and the second P ⁺ -type semiconductor region are connected to the cathode end, and the floating first P ⁺ -type semiconductor region is not connected to the second insulating region and the N-type semiconductor well region At the office. The electrostatic discharge protection element of claim 1, wherein the cathode end is grounded. The electrostatic discharge protection device of claim 1, wherein the filter comprises a capacitor and a resistor, the two ends of the resistor being respectively connected to the first end and the second end, and two ends of the capacitor The second end and the third end are respectively connected. The electrostatic discharge protection device of claim 1, wherein the floating first P ⁺ -type semiconductor region, the N-type semiconductor well region, and the P-type semiconductor substrate form a PNP-type bipolar junction transistor And the second N ⁺ -type semiconductor region, the P-type semiconductor substrate and the N-type semiconductor well region form an NPN-type bipolar junction transistor. The electrostatic discharge protection device of claim 1, wherein the floating first P ⁺ -type semiconductor region, the N-type semiconductor well region, and the first N ⁺ -type semiconductor region form a reverse biased diode And the conductive layer, the insulating layer and the N-type semiconductor well region form a gold oxide half capacitor, and the gold oxide half capacitor and the reverse biased diode form a gate polarization diode. An electrostatic discharge protection component comprising: an anode terminal and a cathode terminal; a floating gated rectifier unit comprising: a P-type semiconductor substrate and an N-type semiconductor well region formed in the P-type semiconductor substrate; An insulating region, a second insulating region and a third insulating region are formed in the N-type semiconductor well region; a first N ⁺ -type semiconductor region is formed between the first insulating region and the second insulating region a first P-type semiconductor region formed between the second insulating region and the third insulating region; a fourth insulating region formed in the P-type semiconductor substrate; and a floating second N ⁺ -type semiconductor region And a second P ⁺ -type semiconductor region formed between the third insulating region and the fourth insulating region; and a gate capacitance formed in the floating second N ⁺ -type semiconductor region and the second P ⁺ Between the semiconductor regions, comprising an insulating layer and a conductive layer formed on the insulating layer; and a trigger switch unit comprising a filter having a first end, a second end and a third end The first end is connected to the anode end and serves as an input of a signal to be filtered The second end connected to the silicon controlled rectifier gate capacitance unit and as an output signal after being filtered, and the third terminal; wherein the first N ⁺ -type semiconductor region and the P ⁺ type first semiconductor The region is connected to the anode terminal, the second P ⁺ -type semiconductor region is connected to the cathode terminal, and the floating second N ⁺ -type semiconductor region is not connected to other portions except the third insulating region and the P-type semiconductor substrate. The electrostatic discharge protection element of claim 6, wherein the cathode end is grounded. The electrostatic discharge protection device of claim 6, wherein the filter comprises a capacitor and a resistor, the two ends of the capacitor are respectively connected to the first end and the second end, and two ends of the resistor The second end and the third end are respectively connected. The electrostatic discharge protection device of claim 6, wherein the first P ⁺ -type semiconductor region, the N-type semiconductor well region, and the P-type semiconductor substrate form a PNP-type bipolar junction transistor, and The floating second N ⁺ -type semiconductor region, the P-type semiconductor substrate, and the N-type semiconductor well region form an NPN-type bipolar junction transistor. The electrostatic discharge protection device of claim 6, wherein the second P ⁺ -type semiconductor region, the P-type semiconductor substrate, and the floating second N ⁺ -type semiconductor region form a reverse biased diode And the conductive layer, the insulating layer and the P-type semiconductor substrate form a metal oxide half capacitor, and the gold oxide half capacitor and the reverse biased diode form a gate polarization diode.