TWI584576B - Voltage generator and oscillation device - Google Patents

Description

Voltage generator and oscillating device

The present invention relates to an electronic device, and more particularly to a voltage generator and an oscillating device.

A voltage-controlled oscillator (VCO) is an electronic oscillating circuit that controls the oscillating frequency with an input voltage. The oscillation frequency of the voltage controlled oscillator will vary with different levels of the input voltage. However, when the conventional voltage controlled oscillator loses operating power, the adjusted relevant setting parameters (such as oscillation frequency, etc.) will be lost. After the conventional voltage controlled oscillator is restarted (re-powered), the user (or system) must re-adjust the oscillation frequency of the set voltage controlled oscillator.

Embodiments of the present invention provide an oscillating device including at least one non-volatile memory, a voltage generator, and a voltage controlled oscillating circuit. The voltage generator uses a non-volatile resistance value provided by the non-volatile memory to generate a bias voltage. The voltage controlled oscillating circuit is coupled to the voltage generator for generating a corresponding oscillating frequency according to the bias voltage. The voltage generator includes a current source, a reverse gate, a switch, and a capacitor. The non-volatile memory is located in the voltage generator. The first end and the second end of the non-volatile memory are respectively coupled to the current source and the low level voltage. The non-volatile memory includes at least one resistive non-volatile memory cell. The resistive non-volatile memory cell is coupled between the first end and the second end of the non-volatile memory to jointly provide a non-volatile resistance value. The first end of the non-volatile memory provides a bias voltage. The reverse gate has an input end and an output end. The input of the reverse gate receives the stylized signal. The switch has a control end, a first end and a second end. The control end of the switch is coupled to the output of the reverse gate. The first end of the switch is coupled to the first end of the non-volatile memory to receive a bias voltage. The second end of the switch is coupled to the input of the voltage controlled oscillation circuit. The capacitor is coupled between the second end of the switch and the low level voltage. During abnormal operation, the switch is off and the bias is maintained by the capacitor.

Embodiments of the present invention provide a voltage generator including a current source, a reverse gate, a switch, a capacitor, and a non-volatile memory. The first end and the second end of the non-volatile memory are respectively coupled to the current source and the low level voltage, wherein the non-volatile memory has a non-volatile resistance value through a programmed manner and is transmitted through The non-volatile resistance value is biased with the current source. The reverse gate has an input end and an output end, wherein the input terminal of the reverse gate receives the stylized signal. The switch has a control end, a first end and a second end. The control end of the switch is coupled to the output of the reverse gate. The first end of the switch is coupled to the first end of the non-volatile memory to receive a bias voltage. The second end of the switch is coupled to the input of the voltage controlled oscillation circuit. The capacitor is coupled between the second end of the switch and the low level voltage. During abnormal operation, the switch is off and the bias is maintained by the capacitor.

The above described features and advantages of the invention will be apparent from the following description.

The term "coupled (or connected)" as used throughout the specification (including the scope of the claims) may be used in any direct or indirect connection. For example, if the first device is described as being coupled (or connected) to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be A connection means is indirectly connected to the second device. In addition, wherever possible, the elements and/ Elements/components/steps that use the same reference numbers or use the same terms in different embodiments may refer to the related description.

FIG. 1 is a block diagram showing the circuit of an oscillating device 200 according to an embodiment of the invention. As shown in FIG. 1, the oscillating device 200 can include a voltage generator 210 and a voltage controlled oscillating circuit 250. In this embodiment, the control voltage value of the voltage controlled oscillation circuit 250 is generated by the voltage generator 210. The voltage generator 210 can generate a bias voltage (control voltage value) using a non-volatile resistance value provided by at least one non-volatile memory (NVM). The non-volatile memory in the voltage generator 210 can be a resistive random access memory (RRAM), a phase-change random access memory (PCRAM) or the like. A memory of an embodiment of the present invention is implemented.

Under the control voltage value, the voltage controlled oscillation circuit 250 can oscillate at a specific frequency according to the bias voltage. To facilitate adjustment of the oscillation frequency of the voltage controlled oscillation circuit 250, the voltage generator 210 can provide an adjustment mechanism to adjust the control voltage value, and adjust the oscillation frequency of the voltage control oscillation circuit 250 correspondingly by using the control voltage value. For example, the non-volatile memory in the voltage generator 210 can determine the non-volatile resistance value according to the digital signal through a program, and provide the voltage to the voltage control through the non-volatile resistance value and a current source. The oscillation circuit 250. When the oscillating device 200 loses operating power, the non-volatile memory within the voltage generator 210 can maintain associated setting parameters for the adjustment mechanism. After the oscillating device 200 is restarted (eg, re-powered), the user (or system) does not have to re-tune the set voltage generator 210.

2 is a schematic diagram of an oscillating device 300 in accordance with another embodiment of the present invention. The embodiment shown in FIG. 2 can be analogized with reference to the related description of FIG. 1. As shown in FIG. 2, the oscillating device 300 can include a voltage generator 310 and a voltage controlled oscillating circuit 350. The voltage generator 310 can generate the bias voltage V _ctrl to the voltage controlled oscillation circuit 350 using the non-volatile resistance value R _out provided by the non-volatile memory 313. The non-volatile memory 313 can have a non-volatile resistance value R _out by way of programming. For example, the non-volatile memory 313 can be programmed according to the digital signal to determine the non-volatile resistance value R _out .

Taking the embodiment shown in FIG. 2 as an example, the voltage generator 310 includes a current source 311 and a non-volatile memory 313. The current source 311 is coupled between the system voltage V _DD and the first end of the non-volatile memory 313 , and the second end of the non-volatile memory 313 is coupled to the low level voltage VSS (eg, a ground voltage). The reference current I _ref provided by the current source 311 may flow from the first end of the non-volatile memory 313 to the second end of the non-volatile memory 313. Since the non-volatile memory 313 has a non-volatile resistance value R _out between the first end and the second end, the reference current I _ref can form a bias voltage V _ctrl at the first end of the non-volatile memory 313 Where the bias voltage V _ctrl = I _ref * R _out . Therefore, the first end of the non-volatile memory 313 can provide a bias voltage V _ctrl to control the oscillation frequency of the voltage controlled oscillation circuit 350. Therefore, the non-volatile memory 313 can provide a corresponding bias voltage V _ctrl through the non-volatile resistance value R _out and the current source 311 to control the oscillation frequency of the voltage-controlled oscillation circuit 350.

The non-volatile memory 313 can be implemented in any manner. For example, in some embodiments, non-volatile memory 313 can include one or more resistive non-volatile memory cells. The resistive non-volatile memory cells are coupled between the first end and the second end of the non-volatile memory 313 to jointly provide a non-volatile resistance value R _out .

In any event, voltage generator 310 should not be limited to the embodiment shown in FIG. For example, in other embodiments, the current source 311 can be coupled between the low level voltage VSS (eg, ground voltage) and the second end of the non-volatile memory 313 instead of the volatile memory 313. One end is coupled to the system voltage V _DD . Therefore, the second end of the non-volatile memory 313 can provide a bias voltage V _ctrl to the voltage controlled oscillating circuit 350.

Referring to FIG. 2, the voltage-controlled oscillating circuit 350 is coupled to the voltage generator 310 for generating a corresponding oscillating frequency according to the bias voltage V _ctrl . The bias voltage V _{ctrl is} responsive to the non-volatile resistance value R _out of the non-volatile memory 313. In other words, when the non-volatile resistance value R _out of the non-volatile memory 313 is adjusted, the oscillation frequency of the voltage-controlled oscillation circuit 350 can be correspondingly changed. When the oscillating device 300 loses operating power, the resistance state (non-volatile resistance value R _out ) of the non-volatile memory 313 is not lost. After the oscillating device 300 is restarted (e.g., re-powered), the non-volatile memory 313 can be regenerated according to the non-volatile resistance value _Rout and provide a bias voltage _Vctrl to the voltage controlled oscillating circuit 350. Furthermore, since the resistance state (non-volatile resistance value R _out ) of the non-volatile memory 313 can be set correspondingly by the user (or system) according to the application requirements, the oscillation frequency output by the oscillation device 300 can be programmed. characteristic.

In the embodiment shown in FIG. 2, the voltage controlled oscillation circuit 350 may have a ring oscillator or various other types of voltage controlled oscillators, which are not limited herein. The ring oscillator is a feedback network composed of a multi-stage delay cell, which has no steady state. The ring oscillator is connected end to end by an odd number of inverters. For example, FIG. 3 is a circuit diagram illustrating the voltage controlled oscillation circuit 350 used in FIG. 2 in accordance with an embodiment of the present invention. The embodiment shown in Fig. 3 is a ring oscillator constructed by connecting seven complementary CMOS inverters in series, but the number and type of inverters are not limited here. Compared to LC oscillators implemented using inductors and capacitors, ring oscillators have a smaller size and are advantageous for miniaturization. The oscillation frequency of the ring oscillator is determined according to the Barkhausen Criteria, which is known to those of ordinary skill in the art to which the present invention pertains, and will not be described herein.

4 is a schematic diagram of a voltage generator 310 and a voltage controlled oscillating circuit 350 in accordance with another embodiment of the present invention. The embodiment shown in FIG. 4 can be analogized with reference to the related description of FIG. 2. The voltage generator 310 of the embodiment shown in FIG. 4 further includes a reverse gate 314, a switch 315 and a capacitor 316. The reverse gate 314 has an input end and an output end. Referring to FIG. 4, the input terminal of the reverse gate 314 receives the stylized signal Progm. The switch 315 has a control end, a first end and a second end. Switch 315 can be implemented in any manner. For example, in the present embodiment, the switch 315 may be an N-type Metal Oxide Semiconductor (NMOS) transistor. In other embodiments, the switch 315 can be a P-type Metal Oxide Semiconductor (PMOS) transistor, a transmission gate, or other switching device. The control end of the switch 315 is coupled to the output end of the reverse gate 314, and the first end of the switch 315 is coupled to the first end of the non-volatile memory 313 to receive the bias V _ctrl , the second end of the switch 315 is coupled to the input end of the voltage controlled oscillation circuit 350 . The capacitor 316 is coupled between the second end of the switch 315 and a low level voltage VSS (eg, a ground voltage). During normal operation of voltage generator 310, switch 315 is turned "on" to transfer bias voltage V _ctrl provided by non-volatile memory 313 to capacitor 316 and voltage controlled oscillating circuit 350. During abnormal operation of voltage generator 310 (e.g., during stylization), switch 315 is off, at which point capacitor 316 maintains the bias voltage of voltage controlled oscillating circuit 350. The turn-off of switch 315 can prevent bias voltage V _ctrl during abnormal operation from affecting the output frequency of voltage controlled oscillating circuit 350.

As shown in FIG. 4, in the present embodiment, the non-volatile memory 313 can include one or more resistive non-volatile memory cells 60. The embodiment shown in FIG. 4 illustrates that three resistive non-volatile memory cells 60 are connected in parallel with each other. However, in other embodiments, the number and connection of the resistive non-volatile memory cells 60 should not be limited to the FIG. Related instructions. The number and connection of the resistive non-volatile memory cells 60 can be determined depending on the design requirements of the actual product. One or more resistive non-volatile memory cells 60 coupled between the first end and the second end of the non-volatile memory 313 may collectively provide a non-volatile resistance value _Rout .

Each of the resistive non-volatile memory cells 60 includes at least one resistive non-volatile memory circuit 600, wherein the resistive non-volatile memory circuit 600 is coupled to the first end of the associated resistive non-volatile memory cell 60 and Between the two ends, as shown in Figure 4. The number of the resistive non-volatile memory circuits 600 of these resistive non-volatile memory cells 60 is different from each other. In other embodiments, the number of resistive non-volatile memory circuits 600 of these resistive non-volatile memory cells 60 are the same for each other. The number and connection manner of the resistive non-volatile memory cell 60 and the resistive non-volatile memory circuit 600 in the resistive non-volatile memory cell 60 may be determined according to the design requirements of the actual product, and are not limited herein. For example, the resistive non-volatile memory cells 60 in the non-volatile memory 313 may be connected in series, in parallel with each other, or in various combinations of series and parallel, and a plurality of resistive types within the resistive non-volatile memory cell 60. The non-volatile memory circuit 600 can be connected in series, in parallel with each other, or in various combinations of series and parallel to provide a non-volatile resistance value R _out of the non-volatile memory 313. An implementation example of the resistive non-volatile memory circuit 600 will be described in detail later.

A plurality of resistive non-volatile memory cells 60 may be connected in parallel between the first end and the second end of the non-volatile memory 313. For example, as shown in FIG. 4, three mutually resistive non-volatile memory cells 60 are connected in parallel. There may be one, two and four resistive non-volatile memory circuits 600, respectively, to form a binary weighted configuration. In another embodiment of the present invention, a plurality of resistive non-volatile memory cells 60 may also be connected in series between the first end and the second end of the non-volatile memory 313 (for example, as shown in FIG. ).

The non-volatile memory 313 can set/adjust the impedance of each resistive non-volatile memory circuit 600 according to the input of the data signal Data, the programmed voltage V _pp and the programmed signal Progm to change the non-volatile memory 313. The non-volatile resistance value _Rout , in turn, changes the oscillation frequency of the voltage controlled oscillation circuit 350. For example, it is assumed that the data signal Data shown in FIG. 4 is a three-bit signal, wherein the first bit of the data signal Data can be transmitted to each resistive non-volatile memory circuit 600 of the first resistive non-volatile memory cell 60. The second bit of the data signal Data can be transmitted to each resistive non-volatile memory circuit 600 of the second resistive non-volatile memory cell 60, and the third bit of the data signal Data can be transmitted to the third bit. Resistive non-volatile memory circuits 600 of resistive non-volatile memory cells 60. When the programmed signal Progm is at the first logic level (eg, a logic "0" indicating that the voltage generator 310 is operating during normal operation), the programming operation of the resistive non-volatile memory circuit 600 is disabled ( Disable). When the programd signal Progm is at a second logic level (eg, a logic "1" indicating that the voltage generator 310 is operating during the stylization), each of the resistive non-volatile memory circuits 600 can each correspond to a corresponding bit of the data signal Data. The element is set to "low resistance state" or reset to "high resistance state". The resistance of the "low resistance state" is greater than 0 ohms, and the resistance value of the "high resistance state" is greater than the resistance value of the "low resistance state".

FIG. 5 is a schematic diagram showing the resistive non-volatile memory circuit 600 of FIG. 4 in accordance with an embodiment of the invention. Referring to FIG. 5, the resistive non-volatile memory circuit 600 of the resistive non-volatile memory cell 60 includes at least one resistive memory element 610 and a control circuit 650. The resistive memory element 610 can have a first end and a second end. The control circuit 650 is coupled to the first end and the second end of the resistive memory element 610 for selectively transmitting the programmed voltage V _pp to the first end or the second end of the resistive memory element 610 during the stylization Or selectively coupling the first end and the second end of the resistive memory element 610 to the first end (end point A) and the second end of the resistive non-volatile memory circuit 600 during normal operation ( End point B).

The resistive memory element 610 described above can be implemented in any manner as desired by the design. For example, the resistive memory element 610 includes a lower electrode, a variable resistor body, and an upper electrode, wherein the variable resistor body is disposed between the lower electrode and the upper electrode. The lower electrode material may be a beryllium copper oxide YBa ₂ Cu ₃ O ₇ (YBCO) film, or titanium nitride (TiN), or may be selected from the group consisting of manganese, iron, nickel, cobalt, titanium, copper, vanadium. An oxide, a nitride, an oxynitride or a combination of the foregoing (for example, titanium (Ti), cerium oxide (SiO ₂ ), cerium (Si), etc.). The variable resistor material may be a crystalline strontium calcium manganese oxide Pr1-XCaXMnO ₃ (PCMO) film of a perovskite type oxide, or a ZnSe-Ge heterostructure, or about Ti, Nb, Hf, Zr, An oxide of a metal such as Ta, Ni, V, Zn, Sn, In, Th, or Al (for example, a hafnium oxide (HfO ₂ ) film). The upper electrode material may be a deposited Ag film or a titanium nitride (TiN). The resistance value and the clamp voltage of the resistive memory element 610 may vary depending on the material and/or process conditions of the upper electrode, the variable resistor, and the lower electrode. By adjusting the voltage direction and voltage between the upper electrode and the lower electrode of the resistive memory element 610, the resistance state of the resistive memory element 610 can be changed, thereby adjusting the non-volatile impedance value of the resistive non-volatile memory circuit 600. .

During the stylization, if the control circuit 650 transmits the programmed voltage V _pp (greater than the threshold voltage of the resistive memory element 610) to the upper electrode of the resistive memory element 610, the low level voltage VSS (eg, ground voltage) is transmitted to In the lower electrode of the resistive memory element 610, the resistive memory element 610 undergoes a "set" operation, causing the resistive state of the resistive memory element 610 to change to a low resistance state. The low resistance state has a resistance value greater than several hundred ohms (eg, several KΩ). Or during the programming period, if the control circuit 650 transmits the programmed voltage V _pp to the lower electrode of the resistive memory element 610 and the low level voltage VSS (eg, the ground voltage) to the upper electrode of the resistive memory element 610, then The resistive memory element 610 will undergo a "reset" operation to change the resistive state of the resistive memory element 610 to a high impedance state. The resistance value of the high resistance state is more than several tens of times higher than the resistance value of the low resistance state (for example, 10K to 100 MΩ).

However, in various embodiments, the operating conditions of the resistive memory element 610 may vary. For example, in other embodiments, if the control circuit 650 transmits the programmed voltage V _pp to the upper electrode of the resistive memory element 610, the low level voltage VSS (eg, the ground voltage) is transmitted to the lower electrode of the resistive memory element 610. Then, the resistance state of the resistive memory element 610 may be changed to "high resistance state". If the control circuit 650 transmits the programmed voltage V _pp to the lower electrode of the resistive memory element 610 and the low level voltage VSS to the upper electrode of the resistive memory element 610, the resistive memory element 610 may be changed to "low" Resistance state."

As shown in FIG. 5, the control circuit 650 includes a switching unit 651, a stylizing unit 652, and an impedance output unit 653. The switching unit 651 can selectively transmit the programmed voltage V _pp to the first end of the switching unit 651 according to one of the corresponding bits Data[n] of the data signal Data, and the low level voltage VSS (for example, the ground voltage or The other fixed voltage is transmitted to the second end of the switching unit 651. Alternatively, the switching unit 651 can also selectively transmit the programmed voltage V _pp to the second end of the switching unit 651 according to the corresponding bit Data[n], and transmit the low level voltage VSS to the first end of the switching unit 651. . The programming unit 652 is coupled to the first end and the second end of the resistive memory element 610 and to the first end and the second end of the switching unit 651. The programming unit 652 can selectively couple the first end and the second end of the switching unit 651 to the first end and the second end of the resistive memory element 610 respectively during the stylization according to the programming signal Progm, or select The electrical connection between the resistive memory element 610 and the switching unit 651 is disconnected during normal operation.

The impedance output unit 653 is coupled between the first end of the resistive non-volatile memory circuit 600 and the first end of the resistive memory element 610, and the second end of the resistive memory element 610 and the resistive non-volatile Between the second ends of the memory circuit 600. According to the programmed signal Progm, the impedance output unit 653 can selectively couple the first end of the resistive memory element 610 to the first end of the resistive non-volatile memory circuit 600 during normal operation, and make the resistive memory element The second end of the 610 is coupled to the second end of the resistive non-volatile memory circuit 600. Alternatively, the impedance output unit 653 can selectively disconnect the electrical connection between the first end of the resistive non-volatile memory circuit 600 and the first end of the resistive memory element 610 during the stylization according to the programmed signal Progm. And disconnecting the electrical connection between the second end of the resistive memory element 610 and the second end of the resistive non-volatile memory circuit 600.

Switching unit 651 can be implemented in any manner. For example, in the present embodiment, the switching unit 651 includes a reverse gate 511, a transistor 512, a transistor 513, a transistor 514, and a transistor 515. The input end of the reverse gate 511 receives one of the corresponding bit elements Data[n] of the data signal Data. The transistor 512 has a control end, a first end and a second end, wherein the control end of the transistor 512 is configured to receive the corresponding bit Data[n] of the data signal Data, the transistor 512 The first end is coupled to the first end (end point C) of the switching unit 651, and the second end of the transistor 512 is configured to receive the stylized voltage V _pp . The transistor 513 has a control end, a first end and a second end, wherein the control end of the transistor 513 is coupled to the output end of the reverse gate 511, and the first end of the transistor 513 is coupled to the first end of the transistor 512. The second end of the transistor 513 is configured to receive the low level voltage VSS (eg, a ground voltage or other fixed voltage). The transistor 514 has a control end, a first end and a second end, wherein the control end of the transistor 514 is configured to receive one of the corresponding bit elements Data[n] of the data signal Data, the first of the transistor 514 One end is coupled to the second end (end point D) of the switching unit 651, and the second end of the transistor 514 is configured to receive the low level voltage VSS. The transistor 515 has a control end, a first end and a second end, wherein the control end of the transistor 515 is coupled to the output end of the reverse gate 511, and the first end of the transistor 515 is coupled to the transistor The first end of the transistor 515 is configured to receive the stylized voltage V _pp .

Styling unit 652 can be implemented in any manner. For example, in the present embodiment, the stylizing unit 652 includes a transistor 521 and a transistor 522. The transistor 521 has a control end, a first end and a second end, wherein the control end of the transistor 521 is configured to receive the stylized signal Progm, and the first end of the transistor 521 is coupled to the resistive memory element 610. The first end of the transistor 521 is coupled to the first end of the switching unit 651. The transistor 522 has a control end, a first end and a second end, wherein the control end of the transistor 522 is configured to receive the stylized signal Progm, and the first end of the transistor 522 is coupled to the resistive memory element 610. The second end of the transistor 522 is coupled to the second end of the switching unit 651.

When the programd signal Progm is at the first logic level (eg, logic "0", indicating that the voltage generator 310 is operating during normal operation), the transistors 521 and 522 are turned off, so that the program of the resistive non-volatile memory circuit 600 The programming operation is disabled. When the programmed signal Progm is at the second logic level (e.g., a logic "1" indicating that the voltage generator 310 is operating during the stylization), the transistors 521 and 522 are turned on. During the stylization, when the corresponding bit Data[n] is at the first logic level (for example, logic "0"), the transistors 512 and 514 are turned off, and the transistors 513 and 515 are turned on, and the low level voltage is at this time. VSS (eg, ground voltage) is transmitted to the first end of the resistive memory element 610 via the transistor 513 and the transistor 521, and the programmed voltage V _pp is transmitted to the resistive via the transistor 515 and the transistor 522. The second end of the memory element 610. Therefore, the resistive memory element 610 will undergo a "reset" operation, causing the resistive state of the resistive memory element 610 to change to a high impedance state. When the corresponding bit Data[n] is at the second logic level (for example, logic "1"), the transistors 512 and 514 are turned on, and the transistors 513 and 515 are turned off, at which time the programmed voltage V _pp is turned on. The crystal 512 and the transistor 521 are transmitted to the first end of the resistive memory element 610, and the low level voltage VSS (eg, the ground voltage) is transmitted to the resistive memory element 610 via the transistor 514 and the transistor 522. Two ends. Therefore, the resistive memory element 610 will undergo a "set" operation, causing the resistive state of the resistive memory element 610 to change to a low resistance state.

However, the present embodiment is not limited to the contents of the above paragraphs. For example, in other embodiments, the transistors 512-515, 521-522, or 532-533 may be PMOS transistors. In one embodiment, when the transistors 512-515 are PMOS transistors, the input terminal of the reverse gate 511 receives one of the corresponding bit data Data[n] of the data signal Data, and the output terminal of the reverse gate 511 is coupled. Connected to the control terminals of transistors 512 and 514, the control terminals of transistors 513 and 515 receive the aforementioned bit Data[n]. During the stylization, when the corresponding bit Data[n] is logic "0", the transistors 512 and 514 are turned off, and the transistors 513 and 515 are turned on. At this time, the low level voltage VSS (for example, the ground voltage) is passed. The transistor 513 and the transistor 521 are transmitted to the first end of the resistive memory element 610, and the stylized voltage Vpp is transmitted to the second end of the resistive memory element 610 via the transistor 515 and the transistor 522. When the corresponding bit Data[n] is logic "1", the transistors 512 and 514 are turned on, and the transistors 513 and 515 are turned off, at which time the programmed voltage Vpp is transmitted via the transistor 512 and the transistor 521. To the first end of the resistive memory element 610, the low level voltage VSS (eg, ground voltage) is transmitted to the second end of the resistive memory element 610 via the transistor 514 and the transistor 522.

The impedance output unit 653 can be implemented in any manner. For example, in the present embodiment, the impedance output unit 653 includes a reverse gate 531, a transistor 532, and a transistor 533. The reverse gate 531 has an input end and an output end, wherein the input end of the reverse gate 531 receives the stylized signal Progm. The control terminal of the transistor 532 is coupled to the output of the reverse gate 531. The first end of the transistor 532 is coupled to the first end of the resistive non-volatile memory circuit 600, and the second end of the transistor 532 is coupled. To the first end of the resistive memory element 610. The control end of the transistor 533 is coupled to the output of the reverse gate 531. The first end of the transistor 533 is coupled to the second end of the resistive memory element 610, and the second end of the transistor 533 is coupled to the resistive non-volatile The second end of the memory circuit 600.

When the programmed signal Progm is at the first logic level (for example, a logic "0" indicating that the voltage generator 310 is operating during normal operation), the stylized operation of the resistive non-volatile memory circuit 600 is disabled, and the power is disabled. The crystals 532 and 533 are turned on, and the resistive memory element 610 can be connected in parallel (or in series) with other resistive non-volatile memory circuits in the resistive non-volatile memory cell 60. When the programmed signal Progm is at the second logic level (eg, a logic "1" indicating that the voltage generator 310 is operating during the stylization), the stylized operation of the resistive non-volatile memory circuit 600 is enabled. While transistors 532 and 533 are off. Because transistors 532 and 533 are turned off, the programmed voltage V _pp does not affect the output frequency of voltage controlled oscillator circuit 350. In other embodiments, when transistors 532 and 533 are PMOS transistors and there is no reverse gate 531 present. If the programmed signal Progm is at the first logic level (e.g., a logic "0" indicating that the voltage generator 310 is operating during normal operation), the stylized operation of the resistive non-volatile memory circuit 600 is disabled. When the programmed signal Progm is at the second logic level (eg, a logic "1" indicating that the voltage generator 310 is operating during the stylization), the stylized operation of the resistive non-volatile memory circuit 600 is enabled. .

FIG. 6 is a schematic diagram showing the arrangement of the resistive non-volatile memory circuit 600 inside the non-volatile memory 313 shown in FIG. 2 or FIG. 4 according to another embodiment of the present invention. The embodiment shown in FIG. 6 can be analogized with reference to the related descriptions of FIGS. 2, 4, and 5. In the embodiment shown in Fig. 6, a plurality of resistive non-volatile memory circuits 600 inside the resistive non-volatile memory cell 60 are connected to each other in series. Taking FIG. 6 as an example, assume that the data signal Data is a three-bit signal, wherein the first bit of the data signal Data is transmitted to each resistive non-volatile memory circuit 600 of the first resistive non-volatile memory cell 60, The second bit of the data signal Data is transmitted to each resistive non-volatile memory circuit 600 of the second resistive non-volatile memory cell 60, and the third bit of the data signal Data is transmitted to the third resistive type. Each resistive non-volatile memory circuit 600 of the non-volatile memory cell 60. When the programmed signal Progm indicates that the voltage generator 310 is operating during the stylization period, each of the resistive non-volatile memory circuits 600 can be set to "low-resistance state" or reset according to the corresponding bit of the data signal Data. It is "high resistance state". When the programmed signal Progm indicates that the voltage generator 310 is operating during normal operation, the stylized operation of the resistive non-volatile memory circuit 600 is disabled.

FIG. 7 is a schematic diagram showing the arrangement of the resistive non-volatile memory circuit 600 inside the non-volatile memory 313 of FIG. 2 or FIG. 4 according to still another embodiment of the present invention. The embodiment shown in FIG. 7 can be analogized with reference to the related descriptions of FIGS. 2, 4, and 5. In the embodiment shown in Figure 7, a plurality of resistive non-volatile memory cells 60 are connected to each other in series. Referring to FIG. 7, when the programmed signal Progm indicates that the voltage generator 310 is operating during the stylization period, each of the resistive non-volatile memory circuits 600 can be set to a "low resistance state" according to the corresponding bit of the data signal Data. Or reset to "high impedance state". When the programmed signal Progm indicates that the voltage generator 310 is operating during normal operation, the stylized operation of the resistive non-volatile memory circuit 600 is disabled.

FIG. 8 is a schematic diagram showing the arrangement of the internal resistive non-volatile memory circuit 600 of the non-volatile memory 313 shown in FIG. 2 or FIG. 4 according to still another embodiment of the present invention. The embodiment shown in FIG. 8 can be analogized with reference to the related descriptions of FIGS. 2, 4, 5, 6, and 7. In the embodiment shown in FIG. 8, a plurality of resistive non-volatile memory circuits 600 in the resistive non-volatile memory cell 60 are connected in series with each other, and another resistive non-volatile memory cell 60 has multiple resistors inside. The non-volatile memory circuits 600 are connected in parallel with each other. The required non-volatile resistance value Rout can be obtained according to the needs of the user by the arrangement pattern as shown in FIG. 4 and FIG. 6 to FIG.

FIG. 9 is a circuit diagram illustrating an oscillating device 900 in accordance with another embodiment of the present invention. The oscillating device 900 of the embodiment shown in FIG. 9 includes a voltage generator 910 and a voltage controlled oscillating circuit 950. The voltage generator 910 and the voltage-controlled oscillation circuit 950 shown in FIG. 9 can be referred to the related description of the voltage generator 210 and the voltage-controlled oscillation circuit 250 shown in FIG. 1, and can also refer to the voltage generation shown in FIG. 2 to FIG. The device 310 is analogous to the description of the voltage controlled oscillator circuit 350.

Referring to FIG. 9, the voltage generator 910 includes a current source 311, a non-volatile memory 313, a reverse gate 314, a switch 315, and a capacitor 316. The first end and the second end of the non-volatile memory 313 are respectively coupled to the current source 311 and the low level voltage VSS (eg, a ground voltage). The reference current I _ref provided by the current source 311 may flow from the first end of the non-volatile memory 313 to the second end of the non-volatile memory 313. Since the non-volatile memory 313 has a non-volatile resistance value R _out between the first end and the second end, the reference current I _ref can form a bias voltage V _ctrl at the first end of the non-volatile memory 313 Where the bias voltage V _ctrl = I _ref * R _out . Therefore, the first end of the non-volatile memory 313 can provide a bias voltage V _ctrl to control the oscillation frequency of the voltage controlled oscillation circuit 950.

In this embodiment, the switch 315 can be an NMOS transistor. In other embodiments, the switch 315 can be a PMOS transistor, a transfer gate, or other switching element. During normal operation of voltage generator 910, switch 315 is turned "on" to transfer bias voltage V _ctrl provided by non-volatile memory 313 to capacitor 316 and voltage controlled oscillating circuit 950. During abnormal operation of the voltage generator 910 (e.g., during program), switch 315 is turned off, this time to maintain the bias voltage V _ctrl voltage controlled oscillator circuit 950 by a capacitor 316. The turn-off of switch 315 can prevent the first terminal voltage of non-volatile memory 313 from affecting the output frequency of voltage controlled oscillating circuit 950 during abnormal operation.

In the embodiment shown in FIG. 9, the voltage controlled oscillation circuit 950 is a ring oscillator constructed by connecting seven CMOS inverters in series with each other. However, in other embodiments, the number and type of inverters should not be limited to FIG. Shown. The oscillation frequency of the ring oscillator can be determined according to the Barkhausen criterion, which is known to those of ordinary skill in the art to which the present invention pertains, and will not be described herein. In addition to the ring oscillator, the voltage controlled oscillation circuit 950 further includes a PMOS transistor 951, a PMOS transistor 925, and an NMOS transistor 953. The PMOS transistor 925 can determine the current I _osc according to the control of the bias voltage V _ctrl . The PMOS transistor 951 and the NMOS transistor 953 can mirror the current I _osc to some (or all) of the CMOS inverters of the ring oscillator shown in FIG. Therefore, the bias voltage V _ctrl can control the oscillation frequency of the voltage controlled oscillation circuit 950. In an embodiment, the magnitude of the current I _osc and the number of inverters may affect the oscillating frequency of the voltage controlled oscillating circuit 950. As described above, the PMOS transistor 925 can determine the current I _osc according to the control of the bias voltage V _ctrl , and the larger the I _osc , the higher the oscillation frequency. In addition, as the number of inverters increases, the transmission time of the signal is delayed, and thus the oscillation frequency of the voltage controlled oscillation circuit 950 can be changed.

FIG. 10 is a flow chart showing a method of operating a voltage controlled oscillation circuit according to an embodiment of the invention. The related description of Fig. 10 can be applied to the embodiment shown in Fig. 2 or Fig. 4. Referring to FIG. 2 and FIG. 10, after the oscillating device 300 is powered on, the voltage generator 310 enters a normal operation period and proceeds to step S910 to provide a non-volatile resistance value R _out by at least one non-volatile memory 313. In step S920, the current source 311 supplies the reference current I _ref to the non-volatile memory 313. Since the non-volatile memory 313 has a non-volatile resistance value R _out between the first end and the second end, the reference current I _ref forms a bias voltage V _ctrl at the first end of the non-volatile memory 313. Where the bias voltage V _ctrl = I _ref * R _out . Therefore, the non-volatile memory 313 can generate the bias voltage V _ctrl to the voltage-controlled oscillation circuit 350 by the non-volatile resistance value R _out . During the stylization, the non-volatile memory 313 sets the non-volatile resistance value R _out of the non-volatile memory 313 to adjust the bias voltage V _ctrl in step S930, thereby controlling the voltage-controlled oscillation circuit 350 according to the bias voltage V _ctrl . Generate the corresponding oscillation frequency.

Taking FIG. 4 as an example, a plurality of resistive non-volatile memory cells 60 are provided between the first end and the second end of the non-volatile memory 313 to jointly provide a non-volatile resistance value R _out . The non-volatile memory 313 can set the resistance states of the plurality of resistive non-volatile memory circuits 600 to determine the non-volatile resistance value R _out of the non-volatile memory 313. During normal operation, current source 311 provides current I _ref to non-volatile memory 313 such that non-volatile memory 313 generates a bias voltage V _{ctrl in} accordance with the non-volatile resistance value R _out . The bias voltage V _ctrl provided by the first end of the non-volatile memory 313 is transmitted via the switch 315 to the capacitor 316 and the voltage controlled oscillating circuit 350 to control the voltage controlled oscillating circuit 350 to generate a corresponding oscillating frequency. In other words, the bias voltage V _{ctrl is} responsive to the non-volatile resistance value R _out . When the non-volatile resistance value R _out of the non-volatile memory 313 is adjusted, the oscillation frequency of the voltage-controlled oscillation circuit 350 can be correspondingly changed. During the stylized, resistive non-volatile memory cell 60 resistance states can be respectively set, to determine the non-volatile memory of non-volatile resistance value of R _out 313, thereby changing the bias voltage V _ctrl. During the change of the bias voltage V _ctrl , the switch 315 is in an off state. Capacitor 316 can maintain the bias voltage of voltage controlled oscillating circuit 350 during the off period of switch 315.

In summary, the embodiment of the present invention provides an oscillating device 300 that retains the non-volatile resistance value R _out previously set by the non-volatile memory 313 even after restarting, so that the operator can conveniently use it without having to re-tune the non-re The volatile resistance value R _out does not require an external memory device to store the digital value of the non-volatile resistance value. The operation mode of the voltage controlled oscillation circuit 350 disclosed in the embodiment of the present invention can provide a stable oscillation frequency.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

60‧‧‧Resistive non-volatile memory cells

200, 300, 900‧‧‧ oscillating devices

210, 310, 910‧‧ ‧ voltage generator

250, 350, 950‧‧‧voltage controlled oscillator circuit

311‧‧‧current source

313‧‧‧ Non-volatile memory

314, 511, 531‧‧ ‧ reverse gate

315‧‧‧ switch

316‧‧‧ Capacitance

512~515, 521~522, 532~533‧‧‧Optoelectronics

600‧‧‧Resistive non-volatile memory circuit

610‧‧‧Resistive memory components

650‧‧‧Control circuit

651‧‧‧Switch unit

652‧‧‧Stylized unit

653‧‧‧impedance output unit

951, 925‧‧‧ PMOS transistor

953‧‧‧NMOS transistor

Data‧‧‧Information Signal

Data[n]‧‧‧ one of the corresponding bits of the data signal

Iref‧‧‧reference current

Progm‧‧‧Stylized signal

Vctrl‧‧‧ bias

VDD‧‧‧ system voltage

Vpp‧‧‧ stylized voltage

VSS‧‧‧low level voltage

1 is a block diagram showing the circuit of an oscillating device according to an embodiment of the invention. 2 is a circuit block diagram of an oscillating device in accordance with another embodiment of the present invention. 3 is a circuit diagram showing the voltage controlled oscillation circuit used in FIG. 2 according to an embodiment of the present invention. 4 is a circuit block diagram of an oscillating device in accordance with another embodiment of the present invention. FIG. 5 is a schematic diagram showing the circuit structure of the resistive non-volatile memory circuit shown in FIG. 4 according to an embodiment of the invention. FIG. 6 is a schematic view showing the arrangement pattern of the internal non-volatile memory circuit of the non-volatile memory shown in FIG. 2 or FIG. 4 according to another embodiment of the present invention. FIG. 7 is a schematic view showing the arrangement pattern of the non-volatile memory internal non-volatile memory circuit shown in FIG. 2 or FIG. 4 according to still another embodiment of the present invention. FIG. 8 is a schematic view showing the arrangement pattern of the internal non-volatile memory circuit of the non-volatile memory shown in FIG. 2 or FIG. 4 according to still another embodiment of the present invention. FIG. 9 is a circuit diagram showing an oscillating device according to another embodiment of the present invention. FIG. 10 is a flow chart showing a method of operating a voltage controlled oscillation circuit according to an embodiment of the invention.

60‧‧‧Resistive non-volatile memory cells

310‧‧‧Voltage generator

311‧‧‧current source

313‧‧‧ Non-volatile memory

314‧‧‧ reverse gate

315‧‧‧ switch

316‧‧‧ Capacitance

350‧‧‧Variable Control Oscillation Circuit

600‧‧‧Resistive non-volatile memory circuit

Data‧‧‧Information Signal

I _ref ‧‧‧reference current

Progm‧‧‧Stylized signal

V _ctrl ‧‧‧ bias

V _DD ‧‧‧ system voltage

Vpp‧‧‧ stylized voltage

VSS‧‧‧low level voltage

Claims (18)

An oscillating device comprising: at least one non-volatile memory; a voltage generator that generates a bias voltage using a non-volatile resistance value provided by the at least one non-volatile memory; and a voltage-controlled oscillating circuit The voltage generator is coupled to the voltage generator to generate a corresponding oscillation frequency according to the bias voltage; wherein the voltage generator includes a current source, a reverse gate, a switch, and a capacitor, wherein the non-volatile memory is located In the voltage generator, a first end and a second end of the non-volatile memory are respectively coupled to the current source and a low level voltage, and the non-volatile memory includes at least one resistive non-volatile memory cell. The non-volatile memory cell is coupled between the first end and the second end of the non-volatile memory to jointly provide the non-volatile resistance value, and the first end of the non-volatile memory provides the bias Pressing, the reverse gate has an input end and an output end, and the input end of the reverse gate receives a stylized signal, the switch has a control end, a first end and a second end, the switch The first end of the switch is coupled to the first end of the non-volatile memory to receive the bias, and the second end of the switch is coupled to the output end of the switch An input terminal of the voltage controlled oscillator circuit is coupled between the second end of the switch and a low level voltage, wherein the switch is turned off during an abnormal operation, and the capacitor is maintained by the capacitor Pressure. The oscillating device of claim 1, wherein the non-volatile memory is a resistive random access memory or a phase change random access memory. The oscillating device of claim 1, wherein the non-volatile memory determines the non-volatile resistance value according to a digital signal in a programmed manner, and provides the bias voltage to the current source through the non-volatile resistance value. . The oscillating device of claim 1, wherein the bias voltage is responsive to the non-volatile resistance value of the non-volatile memory. The oscillating device of claim 1, wherein the resistive non-volatile memory cells are connected in parallel or in series with each other between the first end and the second end of the non-volatile memory. The oscillating device of claim 5, wherein the resistive non-volatile memory cells each comprise at least one resistive non-volatile memory circuit; and wherein one of the resistive non-volatile memory cells The at least one resistive non-volatile memory circuit is connected in series or in parallel with each other. The oscillating device of claim 1, wherein each of the resistive non-volatile memory cells comprises at least one resistive non-volatile memory circuit, and any resistive non-volatile memory circuit comprises: a resistor The memory device has a first end and a second end; and a control circuit coupled to the first end and the second end of the resistive memory element for selectively during a stylization Transmitting a stylized voltage to the first end or the second end of the resistive memory element, or selectively coupling the first end and the second end of the resistive memory element respectively during a normal operation Connected to a first end and a second end of the resistive non-volatile memory circuit. The oscillating device of claim 7, wherein the control circuit comprises: a switching unit that selectively transmits the programmed voltage to a first end of the switching unit according to a data signal and Transmitting a low level voltage to a second end of the switching unit, or selectively transmitting the programmed voltage to the second end of the switching unit and transmitting the low level voltage to the first end of the switching unit; a stylized unit coupled to the first end and the second end of the resistive memory element and the switching unit for selectively selecting the switching unit during the stylizing according to a programmed signal The first end and the second end are respectively coupled to the first end and the second end of the resistive memory element, or selectively disconnect the resistive memory element and the switching unit during the normal operation And an electrical impedance connection; and an impedance output unit coupled between the first end of the resistive non-volatile memory circuit and the first end of the resistive memory element, and coupled to the resistive memory Between the second end of the component and the second end of the resistive non-volatile memory circuit, the first end of the resistive memory element is coupled to the programmable signal during the normal operation according to the programmed signal The first end of the resistive non-volatile memory circuit and the second end of the resistive memory element are coupled to the second end of the resistive non-volatile memory circuit, or are interrupted during the stylization Opening an electrical connection between the first end of the resistive non-volatile memory circuit and the first end of the resistive memory element, and disconnecting the second end of the resistive memory element from the resistive Swing An electrical connection between the second ends of the memory circuit. A voltage generator includes: a current source; a non-volatile memory having a first end and a second end coupled to the current source and a low level voltage, wherein the non-volatile memory is programmed The method has a non-volatile resistance value and provides a bias voltage with the current source through the non-volatile resistance value; and a reverse gate having an input end and an output end, wherein the input end of the reverse gate receives the a switch having a control end, a first end and a second end, wherein the control end of the switch is coupled to the output end of the switch, the first end of the switch is coupled to The first end of the non-volatile memory receives the bias voltage, the second end of the switch is coupled to an input end of a voltage controlled oscillation circuit, and a capacitor coupled to the second end of the switch Between and a low level voltage; wherein during a non-normal operation, the switch is off, at which time the bias is maintained by the capacitor. The voltage generator of claim 9, wherein the non-volatile memory determines the non-volatile resistance value according to a digital signal in a programmed manner. The voltage generator of claim 9, wherein the non-volatile memory comprises: at least one resistive non-volatile memory cell coupled to the non-volatile memory The first end and the second end are used together to provide the non-volatile resistance value. The voltage generator of claim 11, wherein the resistive non-volatile memory cells are connected in parallel or in series with each other between the first end and the second end of the non-volatile memory. The voltage generator of claim 12, wherein the resistive non-volatile memory cells each comprise at least one resistive non-volatile memory circuit; and wherein the resistive non-volatile memory cells are In one case, the at least one resistive non-volatile memory circuit is connected in series or in parallel with each other. The voltage generator of claim 11, wherein each of the resistive non-volatile memory cells comprises at least one resistive non-volatile memory circuit, and any resistive non-volatile memory circuit comprises: The resistive memory device has a first end and a second end; and a control circuit coupled to the first end and the second end of the resistive memory element for selectively during a stylization Transmitting a stylized voltage to the first end or the second end of the resistive memory element, or selectively causing the first end and the second end of the resistive memory element to be respectively during a normal operation The first end and the second end of the resistive non-volatile memory circuit are coupled to the first end and the second end. The voltage generator of claim 14, wherein the control circuit comprises: a switching unit that selectively transmits the programmed voltage to a first end of the switching unit according to a data signal and Transmitting a low level voltage to a second end of the switching unit or selectively transmitting the programmed voltage to the switching list The second end of the element and the low level voltage are transmitted to the first end of the switching unit; a stylizing unit coupled to the first end and the second end of the resistive memory element and the switching unit The first end and the second end of the switching unit are respectively coupled to the first end and the second end of the resistive memory element during the stylization according to a programmed signal Or selectively disconnecting the electrical connection between the resistive memory element and the switching unit during the normal operation; and an impedance output unit coupled to the first of the resistive non-volatile memory circuit Between the end and the first end of the resistive memory element, and coupled between the second end of the resistive memory element and the second end of the resistive non-volatile memory circuit, a programmed signal, the first end of the resistive memory element is coupled to the first end of the resistive memory circuit and the second end of the resistive memory element is coupled during the normal operation To the resistive non-volatile Recovering the second end of the circuit, or disconnecting the electrical connection between the first end of the resistive non-volatile memory circuit and the first end of the resistive memory element during the stylization, and An electrical connection between the second end of the resistive memory element and the second end of the resistive non-volatile memory circuit is opened. The voltage generator of claim 15, wherein the switching unit comprises: a reverse gate having an input end and an output end, the input end of the reverse gate receiving the data signal; a first transistor having a control end, a first end and a second end, wherein the control end of the first transistor is configured to receive the data signal, the first end coupling of the first transistor Connected to the first end of the switching unit, the second end of the first transistor is configured to receive the stylized voltage; a second transistor having a control end, a first end and a second end The first end of the second transistor is coupled to the first end of the first transistor, and the second end is coupled to the output end of the second transistor. The second end of the crystal is configured to receive the low level voltage; a third transistor has a control end, a first end and a second end, wherein the control end of the third transistor is configured to receive the Data signal, the first end of the third transistor is coupled to the second end of the switching unit, the second end of the third transistor is configured to receive the low level voltage, and a fourth transistor is The control terminal has a control end, a first end and a second end, wherein the control end of the fourth transistor is coupled to the opposite end The output terminal, the first terminal of the fourth transistor is coupled to the first terminal of the third transistor, the second terminal of the fourth power of the crystal for receiving the stylized voltage. The voltage generator of claim 15, wherein the stylizing unit comprises: a first transistor having a control end, a first end and a second end, wherein the first transistor The control terminal is configured to receive the programmed signal, the first end of the first transistor is coupled to the first end of the resistive memory element, and the second end of the first transistor is coupled to the switch The first end of the unit; a second transistor having a control end, a first end and a second end, wherein the control end of the second transistor is configured to receive the stylized signal, the first end of the second transistor The second end of the second transistor is coupled to the second end of the switching unit. The voltage generator of claim 15, wherein the impedance output unit comprises: a reverse gate having an input end and an output end, wherein the input end of the reverse gate receives the stylized signal; The first transistor has a control end, a first end and a second end, wherein the control end of the first transistor is coupled to the output end of the reverse gate, the first of the first transistor The second end of the first transistor is coupled to the first end of the resistive memory device; and the second transistor is coupled to the first end of the resistive memory device a control terminal, a first end and a second end, wherein the control end of the second transistor is coupled to the output end of the reverse gate, the first end of the second transistor is coupled to the resistor The second end of the second memory transistor is coupled to the second end of the resistive non-volatile memory circuit.