TWI573391B - Variable gain amplifying circuit - Google Patents

Description

Variable gain amplifier circuit

The present invention relates to a variable gain amplifying circuit.

The variable gain amplifying circuit is configured to amplify or attenuate an input signal according to a gain control signal. The first figure shows a schematic diagram of a conventional variable gain amplifying circuit. The variable gain amplifying circuit 100 includes a differential operational amplifier 12, resistors R1B and R2B having fixed resistance values, and resistors R2A and R2B having variable resistance values.

As shown in the first figure, each of the resistors R2A and R2B has a plurality of circuit units connected in parallel, wherein each circuit unit is composed of a transistor switch and a resistor connected in series. A gain controller 14 generates a plurality of logic signals to a plurality of transistor switches in the resistor R2A, and a gain controller 16 generates a plurality of logic signals to a plurality of transistor switches in the resistor R2B. The resistance of the resistors R2A and R2B is determined by the conduction state of the transistor switch. Therefore, by turning on and off the switches, the resistances of the resistors R2A and R2B are varied, thereby changing the gain of the variable gain amplifying circuit 100.

According to this operation mode, when the resistance of the resistor R1A is equal to the resistance of the resistor R1B, and the resistance of the resistor R2A is equal to the resistance of the resistor R2B, the gain of the variable gain amplifier circuit 100 can be obtained by the resistance of the resistor R2A and Resistance R1A The resistance ratio is determined. When the gain of the variable gain amplifying circuit 100 requires an N-level change, the circuit cells in each of the resistors R2A and R2B require N transistor switches and N resistors. Therefore, the wafer area of the variable gain amplifying circuit 100 increases a lot as the number of stages N increases.

According to an embodiment of the present invention, a variable gain amplifying circuit is configured to amplify a voltage difference between a first input signal and a second input signal to generate an amplified differential output signal. . The variable gain amplifying circuit comprises an operational amplifier, a first input component, a feedback component, a detection circuit, a dynamic bias circuit and a transconductance amplifier. The operational amplifier has a first input, a second input and an output for providing the amplified differential output signal. The first input component has a first end for receiving the first input signal and a second end coupled to the first input of the operational amplifier. The feedback component has a first end coupled to the first input of the operational amplifier and a second end coupled to the output of the operational amplifier. The detecting circuit is configured to generate a set value according to a voltage value of one of the first input signal and the second input signal or according to a voltage value of the amplified differential output signal. The dynamic bias circuit is configured to generate a bias current according to the set value. The transconductance amplifier is configured to convert the voltage difference between the first input signal and the second input signal to generate an analog output current. The analog output current flows through the feedback element. The first input element has a fixed resistance. Analog output current of the transconductance amplifier It changes according to the bias current.

100‧‧‧Variable gain amplifier circuit

12‧‧‧Differential Operational Amplifier

14‧‧‧ Gain Controller

16‧‧‧ Gain Controller

200‧‧‧Variable gain amplifier circuit

22‧‧‧Gain Amplifier

224‧‧‧Operational Amplifier

24,24’‧‧‧Transduction Amplifier

26,26’‧‧‧ Dynamic Bias Circuit

262‧‧‧current generation circuit

2622‧‧‧Operational Amplifier

264‧‧‧current mirror circuit

400‧‧‧Variable gain amplifier circuit

42‧‧‧Gain Amplifier

424‧‧‧Operational Amplifier

48‧‧‧Detection circuit

49‧‧‧Charging pump

600‧‧‧Variable gain amplifier circuit

64‧‧‧Switch unit

66‧‧‧Switch unit

68‧‧‧Detection circuit

800‧‧‧Variable gain amplifier circuit

82‧‧‧Detection circuit

C1, CH‧‧‧ capacitor

I1, I2‧‧‧ current source

N1~N5‧‧‧O crystal

P1~P5‧‧‧O crystal

R1A, R2A, R1B, R2B‧‧‧ resistance

R1~R4‧‧‧ resistor

RLEL‧‧‧resistance

SW1, SW2‧‧‧ switch

The first figure shows a schematic diagram of a conventional variable gain amplifying circuit.

The second figure shows a block diagram of a variable gain amplifying circuit in accordance with one embodiment of the present invention.

The third figure shows a circuit diagram of the variable gain amplifying circuit in combination with an embodiment of the present invention.

The fourth figure shows a block diagram of a variable gain amplifying circuit in accordance with another embodiment of the present invention.

Fig. 5 is a circuit diagram showing a variable gain amplifying circuit in accordance with another embodiment of the present invention.

Fig. 6 is a block diagram showing a variable gain amplifying circuit which can increase the gain in combination with another embodiment of the present invention.

The seventh figure shows the operation of the variable gain amplifying circuit shown in the sixth figure.

The eighth figure shows a block diagram of a variable gain amplifying circuit which can increase the gain in combination with still another embodiment of the present invention.

The ninth drawing shows a circuit diagram of the variable gain amplifying circuit in combination with an embodiment of the present invention.

Used in the specification and subsequent patent applications These words refer to specific components. It should be understood by those of ordinary skill in the art that manufacturers may refer to the same elements by different nouns. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" or "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

The second figure shows a block diagram of a variable gain amplifying circuit 200 in accordance with one embodiment of the present invention. Referring to the second figure, the variable gain amplifying circuit 200 includes a gain amplifier 22, a transconductance amplifier 24, and a dynamic bias circuit 26.

The gain amplifier 22 is configured to receive an analog input signal VI to generate an analog output signal VO. In the present embodiment, the gain amplifier 22 is composed of a single-ended input single-ended output operational amplifier 224, a resistor R1 having a fixed resistance value, and a resistor R2 having a fixed resistance value. When the transconductance amplifier 24 does not supply current to the resistor R2, the gain G of the gain amplifier 22 is determined by equation (1).

G=R2/R1 (1)

However, the new gain G' of the gain amplifier 22 can be changed by changing the flow Obtained by the net current of the resistor R2. Referring to the second diagram, the transconductance amplifier 24 is operative to convert the difference between the input voltage VI and the reference voltage VREF to produce an analog output current IGM. Next, the transconductance amplifier 24 supplies the analog output current IGM to the gain amplifier 22, thereby adjusting the gain G' of the gain amplifier 22. Note that a bias current IDYN of the transconductance amplifier 24 is derived from the dynamic bias circuit 26. The bias current IDYN can be varied according to an input signal VLEL.

The third figure shows a circuit diagram of the variable gain amplifying circuit 200 incorporating an embodiment of the present invention. Referring to the third diagram, the dynamic bias circuit 26 includes a current generating circuit 262 and a current mirror circuit 264. The current generating circuit 262 is composed of an operational amplifier 2622, an NMOS transistor N1 and a resistor RLEL. The operational amplifier 2622 has a positive input terminal for receiving the input signal VLEL, a negative input terminal coupled to the resistor RLEL, and an output terminal coupled to a gate of the NMOS transistor N1. According to this configuration, the current IN1 flowing through the NMOS transistor N1 can be determined by the equation (2).

IN1=VLEL/RLEL (2)

Referring to the third diagram, the current mirror circuit 264 is composed of PMOS transistors P1, P2, and P3. The PMOS transistor P1 receives the current IN1 flowing through the NMOS transistor N1, and the PMOS transistors P2 and P3 generate a current proportional to the current IN1 according to the aspect ratio (W/L ratio). The current of the PMOS transistor P3 serves as the upper bias current of the transconductance amplifier 24. The current flowing through the PMOS transistor P2 flows to the NMOS transistor N2, and then the NMOS transistor N3 generates a current proportional to the NMOS transistor N2 according to the aspect ratio as the turn The lower bias current of the amplifier 24.

The transconductance amplifier 24 includes an input transistor pair consisting of a series connected PMOS transistor P1 and an NMOS transistor N4 and a series connected PMOS transistor P5 and NMOS transistor N5. Referring to the third figure, the PMOS transistor P4 and the NMOS transistor N4 are connected in series between the PMOS transistor P3 and the NMOS transistor N3, and the PMOS transistor P5 and the NMOS transistor N5 are connected in series to the PMOS. Between the transistor P3 and the NMOS transistor N3.

Referring to the third figure, the gates of the PMOS transistor P4 and the NMOS transistor N4 are used to receive the analog input signal VI, and the gates of the PMOS transistor P5 and the NMOS transistor N5 are used to receive the reference voltage VREF. . Therefore, the current value of the analog output current IGM of the transconductance amplifier 24 is proportional to the difference between the input voltage VI and the reference voltage VREF. Furthermore, the gain of the transconductance amplifier 24 corresponds to the bias current value of the PMOS transistor P3 or the NMOS transistor N3.

An operation of the variable gain amplifying circuit 200 will be described below with reference to the third figure. As the voltage value of the input signal VLEL rises, the current flowing through the resistor RLEL also increases. Since current mirror 264 produces a replica current, it is proportional to the current flowing through resistor RLEL. Therefore, the bias current values of the PMOS transistor P3 and the PMOS transistor P3 also increase. When VI>VREF, the transconductance amplifier 24 generates the analog output current IGM. At this time, the analog output current IGM will carry away the current flowing through the resistor R2, so the net current flowing through the resistor R2 will decrease, which makes The increase of the gain amplifying circuit 22 Benefits decline.

In the third diagram, a single-ended input single-ended output operational amplifier 224 is used in the gain amplifier 22. However, the invention should not be limited to this type of operational amplifier. The gain amplifier 22 can also be of the differential input differential output amplifier. The fourth figure shows a block diagram of a variable gain amplifying circuit 400 in accordance with another embodiment of the present invention. Referring to the fourth figure, the variable gain amplifying circuit 400 includes a gain amplifier 42, a transconductance amplifier 24', a dynamic bias circuit 26', a detecting circuit 48, and a charging pump 49. Elements in the fourth figure that are similar to the second figure are shown with similar reference numerals, and details of the circuit will not be described again.

In the present embodiment, the gain amplifier 42 is of the type of a double-ended differential input double-ended differential output amplifier. The gain amplifier 42 receives complementary analog input signals VIP and VIN to produce complementary analog output signals VOP and VON. As shown in the fourth figure, the gain amplifier 42 is composed of a differential operational amplifier 424 and resistors R1, R2, R3, R4 having fixed resistance values. When the resistance of the resistor R1 is equal to the resistance of the resistor R2, and the resistance of the resistor R3 is equal to the resistance of the resistor R4, the gain of the gain amplifier 42 is not provided when the transconductance amplifier 24' does not supply current to the resistor R3. G is determined by equation (3).

G=R3/R1 (3)

In this case, when the input voltage VIP is greater than the input voltage VIN, the direction of the current flowing through the resistor R3 and the direction of the current flowing through R4 are as indicated by the solid line in the fourth figure. As the difference between the input voltage VIP and the input voltage VIN increases, The current flowing through resistors R3 and R4 also increases.

On the other hand, when the detecting circuit 48 detects that the output voltage of the variable gain amplifying circuit 400 is not within a predetermined range, the gain of the gain amplifier 42 can start to be adjusted. An operation of the variable gain amplifying circuit 400 will be described below with reference to the fifth figure. When the detecting circuit 48 detects the output voltage VOP of the variable gain amplifying circuit 400, and the VON is not within the predetermined range, the detecting circuit 48 generates complementary control signals UP and DN to the charging pump 49. The charge pump 49 is used to generate the signal VLEL. As shown in the fifth figure, the charge pump 49 includes an upper bias current source I1, a lower bias current source I2, two switches SW1 and SW2, and a capacitor C1.

The charge pump 49 charges the capacitor C1 according to the control signal UP such that the voltage value of the signal VLEL rises; the charge pump 49 discharges the capacitor C1 according to the control signal DN, so that the voltage value of the signal VLEL decreases. When the detecting circuit 48 detects the output voltage VOP of the variable gain amplifying circuit 400, and the VON is not within the predetermined range, the charging pump 49 charges the capacitor C1. Therefore, the voltage value of the signal VLEL increases, and the current flowing through the resistor RLEL also increases. As the current flowing through the resistor RLEL increases, the bias current value of the PMOS transistor P3 or the NMOS transistor N3 also increases, so that the analog output currents IJ1 and IJ2 of the transconductance amplifier 24 increase. Therefore, the net current flowing through the resistors R3 and R4 drops, which causes the gain of the gain amplifier 42 to decrease. Note that the analog currents of the output currents IJ1 and IJ2 will be opposite. When the gain of the gain amplifier 42 decreases, the variable gain amplifying circuit 400 When the output voltage VOP, VON eventually returns to the predetermined range, the signal of the signal VLEL does not continue to increase and maintains a stable value.

The variable gain amplifying circuits in the second and fourth figures can be used in many communication systems and signal processing units. For example, the variable gain amplifying circuit 200 can be applied to a volume control unit to increase or attenuate the input audio signal. The sixth figure shows a block diagram of a variable gain amplifying circuit 600 that adds gain in conjunction with yet another embodiment of the present invention. Referring to the sixth figure, the variable gain amplifying circuit 600 includes a gain amplifier 42, a transducing amplifier 24', a switching unit 64, a switching unit 66, a dynamic bias circuit 26', a detecting circuit 68, and A charge pump 49. Elements in the sixth figure that are similar to the fourth figure are shown with similar reference numerals.

The mode of operation of the variable gain amplifying circuit 600 will now be described. When the detecting circuit 68 detects that the output voltages VOP and VON of the variable gain amplifying circuit 600 are not within a higher predetermined range (for example, 4 V), the switch in the switching unit 64 is turned on and the switching unit 66 is turned on. The switch will be cut off. Therefore, the transconductance amplifier 24' produces output currents IJ1 and IJ2 based on the difference between the input voltage VIP and the input voltage VIN. Next, the charge pump 49 charges the capacitor C1 to increase the voltage value of the signal VLEL. As the voltage value of the signal VLEL increases, the net current flowing through the resistors R3 and R4 decreases, which causes the gain of the gain amplifier 42 to decrease. In this manner, when the output voltages VOP and VON of the variable gain amplifying circuit 600 are not within a higher predetermined range, the variable gain amplifying circuit 600 can reduce the gain.

On the other hand, when the detecting circuit 48 detects the output voltage VOP of the variable gain amplifying circuit 400, and the VON is not within a lower predetermined range (for example, 0.5 V), the switch in the switching unit 64 is turned off. The switch in the switching unit 66 is turned on. Therefore, the transconductance amplifier 24' produces output currents IJ1 and IJ2 based on the difference between the input voltage VIP and the input voltage VIN. In this case, the voltage value of the signal VLEL will increase. As shown in the seventh figure, the net current flowing through the resistors R3 and R4 increases, which causes the gain of the gain amplifier 42 to rise.

The eighth diagram shows a block diagram of a variable gain amplifying circuit 800 that adds gain in conjunction with yet another embodiment of the present invention. Referring to the eighth figure, the variable gain amplifying circuit 800 includes a gain amplifier 42, a transconductance amplifier 24', a dynamic bias circuit 26', a detecting circuit 82, a switch SW, and a capacitor CH. The gain adjustment of the variable gain amplifying circuit 200 in the second figure and the variable gain amplifying circuit 400 in the fourth figure is not limited to the zero crossing of the input voltage or the output voltage. Therefore, even by introducing a small current IGM to the gain amplifier 22 or by introducing small currents IJ1 and IJ2 to the gain amplifier 42 to adjust the amplifier gain slightly, at the top of the analog input voltage, it is still possible to cause an audible instant. Audible transient. For high quality audio devices, sound transients are a problem. In order to solve this problem, the variable gain amplifying circuit 800 may require the detecting circuit 72 to detect the zero crossing of the input voltage or the output voltage, for example, when the input voltage or the output voltage changes from a positive value to a negative voltage. A zero crossing signal is generated when a value or a negative value transitions to a positive value to indicate that the signal enters a zero crossing.

The ninth diagram shows the variable gain in connection with an embodiment of the present invention A circuit diagram of the amplifying circuit 800. Elements in the ninth diagram similar to the fifth diagram are shown with similar reference numerals. Referring to the ninth figure, in the present embodiment, the detection circuit 82 receives the complementary analog output signals VOP and VON and generates a zero-crossing signal ZC at the zero crossing of the output signals VOP and VON. The switch SW is only turned on when the zero-over signal ZC is generated to transmit the voltage value of the signal VLEL to the capacitor CH. Next, the dynamic bias circuit 26' generates an upper bias current and a lower bias current supplied to the transconductance amplifier 24' based on the voltage VD across the capacitor CH. In this manner, the gain amplifier 42 adjusts the gain value only when the detection circuit 82 detects a zero crossing point.

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention is not to be construed as being limited by the scope of the invention, and

200‧‧‧Variable gain amplifier circuit

22‧‧‧Gain Amplifier

224‧‧‧Operational Amplifier

24‧‧‧Transduction amplifier

26‧‧‧ Dynamic Bias Circuit

R1, R2‧‧‧ resistance

Claims (12)

A variable gain amplifying circuit for amplifying a voltage difference between a first input signal and a second input signal to generate an amplified differential output signal, the variable gain amplifying circuit comprising: an operational amplifier, Having a first input end, a second input end and an output end for providing the amplified differential output signal; a first input element having a first end for coupling the first input signal and coupling a second end of the first input of the operational amplifier; a feedback component having a first end coupled to the first input of the operational amplifier and a first end coupled to the output of the operational amplifier a detecting circuit configured to generate a set value according to a voltage value of one of the first input signal and the second input signal or a voltage value according to the amplified differential output signal; a voltage circuit for generating a bias current according to the set value; and a transducing amplifier for converting the voltage difference between the first input signal and the second input signal to generate an analogy A current; wherein the ratio of the output of such a current flowing through the feedback element; wherein the first input member having a fixed resistance value; and Wherein, the analog output current of the transconductance amplifier changes according to the bias current. The variable gain amplifying circuit according to the first aspect of the patent application, further comprising a charging pump, wherein the detecting circuit is configured to generate a first when the voltage value of the amplified differential output signal is greater than a first preset value The signal is detected, and the charge pump is configured to generate the set value according to the first detection signal. A variable gain amplifying circuit according to claim 1, wherein when the set value is increased, the bias current is increased, so that the analog output current is increased such that a net current flowing through the feedback element is decreased. The variable gain amplifying circuit according to claim 2, wherein when the voltage value of the amplified differential output signal is greater than the first predetermined value, the set value is increased, so the bias current is increased to increase the analog output. Current, wherein the analog output current increases such that a net current flowing through the feedback element drops. According to the variable gain amplifying circuit of claim 2, when the voltage value of the amplified differential output signal is less than a second preset value, the detecting circuit generates a second detecting signal, the charging pump And generating the set value according to the second detection signal, wherein the first preset value is greater than the second preset value. The variable gain amplifying circuit according to claim 5, wherein when the voltage value of the amplified differential output signal is less than the second preset value, the set value is increased, so that a net flowing through the feedback element The current increases. The variable gain amplifying circuit according to claim 1, wherein the dynamic bias circuit comprises: a current generating circuit having an input terminal for receiving the set value and a second end for generating an output current; and a And a current mirror for generating the bias current according to the output current of the current generating circuit; wherein the output current of the current generating circuit varies according to the set value. The variable gain amplifying circuit of claim 1, wherein the transimpedance amplifier comprises: a first PMOS transistor and a first NMOS transistor connected in series between a first node and a second node; a second PMOS transistor and a second NMOS transistor are connected in series between the first node and the second node; wherein the first node is configured to receive the bias current; wherein the first PMOS transistor a gate and a gate of the first NMOS transistor for receiving the first input signal; wherein a gate of the second PMOS transistor and a gate of the second NMOS transistor are used for receiving The second input signal; and wherein the analog output current is generated at an intersection of the first PMOS transistor and the first NMOS transistor. The variable gain amplifying circuit according to claim 1 further includes a switch, wherein the detecting circuit generates a zero crossing signal when the voltage value of the amplified differential output signal is zero, and the switch is The zero crossing signal is turned on when the signal is generated, and the dynamic bias circuit receives the set value when the switch is turned on. The variable gain amplifying circuit of claim 1, further comprising a switch, wherein the detecting circuit generates a voltage when the voltage value of the one of the first input signal and the second input signal is zero A zero crossing signal, the switch is turned on when the zero crossing signal is generated, and the dynamic bias circuit receives the set value when the switch is turned on. A variable gain amplifying circuit according to claim 9 wherein the operational amplifier is a single-ended input single-ended output type amplifier, and wherein the second end of the operational amplifier receives the second input signal. The variable gain amplifying circuit of claim 1, further comprising: a second input element having a first end for receiving the second input signal and the second input coupled to the operational amplifier A second terminal; wherein the operational amplifier is a double-ended input double-ended output type amplifier.