TWI569138B - Analog device and hard disk backplane test system - Google Patents

Description

Analog device and hard disk backplane test system

The present invention relates to an analog device and a hard disk backplane test system, and more particularly to an analog device and a hard disk backplane test system using an internal integrated circuit bus.

Now the general server platform test method is to use the actual hard disk, and insert the hard disk on the hard disk backplane to verify the function of the hard disk backplane. However, using a large number of hard disks to test the hard disk backplane is not only costly, but also the size and weight of the hard disk makes it inconvenient to test multiple hard disk backplanes. Therefore, there is a need to develop a lightweight and inexpensive hard disk backplane test method and system.

In view of the above problems, the present invention provides an analog device for testing a hard disk backplane, which processes a signal sent by a module to simulate a hard disk, and generates a corresponding signal according to a signal reflected by a bus bar of the hard disk backplane. Test results. A plurality of said analog devices may be connected to each other by an inter-integrated circuit (I ² C) and connected to a control device, whereby the test results of the plurality of analog devices can be quickly collected by one control device.

Analog device according to an embodiment of the invention, suitable for connecting to a hard disk The backboard, the simulation device includes a processing module and an interface module. The processing module is configured to generate a test signal, analyze the feedback signal to generate a test result, and selectively forward the first data packet or respond to the first data according to the data address in the first data packet when receiving the first data packet. The test result is sent out by the packet. The interface module is electrically connected to the processing module and the hard disk backplane for converting the test signal into the first signal for transmission to the hard disk backplane, and converting the second signal from the hard disk backplane into a feedback signal. The format of the first signal and the format of the second signal are both the first data format, and are different from the format of the test signal or the format of the feedback signal.

In an embodiment of the invention, the processing module includes a first signal end, a second signal end, a processing unit, and a signal transceiving unit. The processing unit is electrically connected to the interface module to generate a test signal, analyze the feedback signal to generate a test result, and send the test result according to the request instruction. The signal transceiving unit is electrically connected to the first signal end, the second signal end and the processing unit. When the signal transceiving unit receives the first data packet from the first signal end, comparing the built-in address with the data bit in the first data packet site. And when the built-in address is different from the data address, the first data packet is sent from the second signal end. When the built-in address is the same as the data address, the request instruction is obtained according to the first data packet, and the request instruction is transmitted to the processing unit. And when the signal transceiving unit receives the test result from the processing unit, the signal transceiving unit controls the first signal end or the second signal end to send the test result.

A hard disk backplane test system in accordance with an embodiment of the present invention can be used to test a plurality of bus bars on a hard disk backplane. The hard disk backplane test system includes a plurality of analog devices and a control device. The foregoing plurality of simulation devices are pluggable separately Electrically connected to the plurality of bus bars, the analog devices are electrically connected to each other by a plurality of first bus bars, and are used to analyze the bus bars to generate a plurality of test results. The control device is electrically connected to one of the plurality of analog devices by a second bus bar for collecting the test results generated by the analog devices.

The above description of the present invention and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention.

10, 10a~10n‧‧‧ simulation device

101‧‧‧Processing module

1011‧‧‧Processing unit

1013‧‧‧Signal Transceiver Unit

1015, 1017‧‧‧ signal end

103‧‧‧Interface module

105‧‧‧Memory Module

11‧‧‧Control device

13‧‧‧ Hard disk backplane

15, 17‧‧‧ External devices

1 is a functional block diagram of a hard disk backplane test system in accordance with an embodiment of the present invention.

Figure 2 is a functional block diagram of a simulation device in accordance with an embodiment of the present invention.

Figure 3 is a functional block diagram of a processing module in accordance with an embodiment of the present invention.

4 is a flow chart of a method performed by a signal transceiving unit in accordance with an embodiment of the present invention.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

Please refer to FIG. 1 , which is a functional block diagram of a hard disk backplane test system according to an embodiment of the invention. As shown in FIG. 1, the hard disk backplane test system includes a plurality of analog devices 10a to 10n, a control device 11, and a hard disk backplane 13. The control device 11 is directly electrically connected to the analog device 10a, and the plurality of analog devices 10a to 10n are electrically connected to each other through an inter-integrated circuit (I ² C), and the analog devices 10a to 10n are electrically connected. A busbar on the hard disk backplane 13. The hard disk backplane 13 is the device under test (DUT) to be tested in the present invention.

Each of the aforementioned plurality of simulation devices 10a to 10n is used to analyze a bus bar on the hard disk backplane 13 to obtain a test result, so that the entire system can obtain a plurality of test results. Regarding how each of the simulation devices 10a to 10n operates, please refer to FIG. 2, which is a functional block diagram of a simulation device according to an embodiment of the present invention. As shown in FIG. 2, an analog device 10 (i.e., any of the analog devices 10a to 10n in FIG. 1) may include a processing module 101 and an interface module 103. The processing module 101 is electrically connected to the external device 15 and the external device 17, and the external device 15 and the external device 17 may be the aforementioned control device 11, or may be another analog device. The interface module 103 is electrically connected to a bus bar on the processing module 101 and the hard disk backplane 13, respectively.

The processing module 101 is used to refer to FIG. 3, which is a functional block diagram of a processing module according to an embodiment of the present invention. As shown in FIG. 3, the processing module 101 includes a processing unit 1011, a signal transceiving unit 1013, a first signal end 1015, and a second signal end 1017. The processing unit 1011 is electrically connected to the interface module 103. The signal transceiving unit is electrically connected to the processing unit 1011, the first signal end 1015 and the second signal end 1017, respectively.

The processing unit 1011 is configured to generate a test signal for testing the bus bar of the hard disk backplane 13, and analyze the feedback signal from the busbar of the hard disk backplane 13 to generate a test result, and according to the signal sent from the signal transceiver unit 1013. Request the command to send the test result. Specifically, the test signal generated by the processing unit 1011 is used to simulate the data sent by the real hard disk, and after receiving the feedback signal, the processing unit 1011 can analyze the feedback signal according to the test signal generated before, so as to know that the feedback signal is obtained. Whether the operation of one busbar connected to the processing unit 1011 on the hard disk backplane 13 is normal, and the processing unit 1011 can generate a test result accordingly. The test result is a set of defined codes to represent the state of the bus, such as "normal" or "insufficient voltage" or "reaction time is abnormal" and so on. In some embodiments, the processing unit 1011 has a cache memory for temporarily storing a plurality of test results in a test program. In another embodiment, returning to FIG. 2, the simulation device 10 may further include a memory module 105 electrically connected to the processing unit 1011 in the processing module 101, and the processing unit 1011 may perform multiple tests. The plurality of test results of the program are stored in the memory module 105. When the control device 11 issues a request command, the plurality of test results stored in the memory module 105 are sent out in batches.

For the manner of operation of the signal transceiving unit 1013, please refer to FIG. 3 and FIG. 4 together. FIG. 4 is a flowchart of a method performed by the signal transceiving unit according to an embodiment of the present invention. As described in step S401, the signal transceiving unit 1013 receives the first data packet through the first signal end 1015. Then as step S402 The signal transceiving unit 1013 determines whether the data address in the first data packet is equal to the built-in address in the processing module 101. If the data address is not equal to the built-in address, the signal transceiving unit 1013 sends the first data packet through the second signal end 1017 as described in step S403. If the data address is equal to the built-in address, the signal transceiving unit 1013 sends the request command in the first data packet to the processing unit 1011 as described in step S404. Then, as described in step S405, the signal transceiving unit 1013 sends the test result sent by the processing unit 1011 to the first signal end 1015. As can be seen from the above, the signal transceiving unit 1013 includes a temporary register to temporarily store the signal/data to be forwarded, and a multiplexer is included to selectively transfer the signal/data in the temporary register to the second signal end 1017. Or processing unit 1011.

The first signal terminal 1015 and the second signal terminal 1017 are used to receive the data packet from the internal integrated circuit bus, and can be used to transmit the test result through the internal integrated circuit bus (to the control device 11). Specifically, the first signal terminal 1015 may include one or more open drain gates or one or more open collector gates. The control terminal of the open circuit gate is electrically connected to the signal transceiver unit 1013, and the first end thereof is electrically connected to the ground end of the processing module 101 (or the entire backplane test system), and the second end thereof is electrically connected. Connect to a cable on the internal integrated internal circuit bus. Therefore, when the control terminal receives a signal with a high logic level, the voltage value of the second terminal (that is, the corresponding cable on the bus line integrating the internal circuit) is pulled to the "low logic level". If any of the multiple open gates connected to the same line on the integrated circuit bus has any signal that receives a high logic level, the voltage of the line Will be pulled to a low logic level.

In one embodiment, if the test result generated by one test has multiple sub-items, and as long as one sub-item is faulty, the processing unit 1011 determines that the corresponding bus bar on the hard disk backplane 13 is defective, and then each sub-item can be The logic level corresponding to the item "Test Pass" is set to low, and the logic level of "Test Pass" is set to high. In this way, when the signal transceiving unit outputs a plurality of result signals corresponding to the plurality of sub-items in one test result to the plurality of open-throw gates, as long as one sub-item test fails, the corresponding integrated lines in the internal integrated circuit The voltage will be pulled low.

The interface module 103 is configured to convert the test signal into a first signal for transmission to a bus bar on the hard disk backplane 13, and convert the second signal into feedback after receiving a second signal from the bus bar. The signal is sent to the processing module 101. The signal format of the first signal and the second signal conforms to the Peripheral Component Interconnect Express (PCIE), the Serial Attached SCSI (SAS), or the Serial Advanced Technology Attachment (SATA). format. Thus, even if the test signal sent by the processing module 101 is not the data transmission format of the hard disk, the first signal obtained after the interface module 103 is converted can truly simulate a PCIE hard disk, a SAS hard disk or a SATA hard disk. Data transfer. Moreover, converting the second signal into a feedback signal similar to the test signal format can also facilitate the processing module 101 to analyze the feedback signal. In practice, the interface module 103 has a serialization/deserialize (SerDes) function (or circuit structure).

Returning to Fig. 1, the control device 11 is for collecting test results obtained by the plurality of simulation devices 10a to 10n. In an implementation manner, the entire test flow may be that when the system architecture (including the hard disk backplane 13) as shown in FIG. 1 is completed, the control device 11 sends a request command requesting each analog device pair to correspond. A bus bar on the hard disk backplane 13 is tested and analyzed. Then, after the processing module in the simulation device completes the test and analysis, the test result is sequentially returned. In another implementation, after the backplane test system is set up, the user can issue a request command to all the analog devices through the control device 11, and each of the analog device pairs is required to be located on the hard disk backplane 13. The bus is tested, but does not require immediate return, and each analog device is required to temporarily store the test results. After the plurality of hard disk backplanes are replaced and tested as many times as described above, the user can again issue a request command to all the analog devices through the control device 11 to request each analog device to return the test results of the multiple tests in batches in sequence.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

10‧‧‧simulator

101‧‧‧Processing module

103‧‧‧Interface module

105‧‧‧Memory Module

13‧‧‧ Hard disk backplane

15‧‧‧External devices

17‧‧‧External devices

Claims (10)

An analog device is adapted to be connected to a hard disk backplane, comprising: a processing module for generating a test signal, analyzing a feedback signal to generate a test result, and receiving a first data packet according to the a data address in the first data packet, selectively forwarding the first data packet or returning the first data packet to send the test result; and an interface module electrically connected to the processing module and the a hard disk backplane for converting the test signal into a first signal for transmission to the hard disk backplane, and converting a second signal from the hard disk backplane to the feedback signal, wherein the first signal The format of the second signal and the format of the second signal are both a first data format, and is different from the format of the test signal or the format of the feedback signal. The analog device of claim 1, wherein the processing module comprises: a first signal terminal; a second signal terminal; and a processing unit electrically connected to the interface module for generating the test signal, The feedback signal is analyzed to generate the test result, and the test result is sent according to a request command; and a signal transceiver unit is electrically connected to the first signal end, the second signal end, and the processing unit, when from the first When receiving the first data packet, the signal end compares a built-in address with the data address, and when the built-in address is different from the data address, the first data packet is encapsulated from the second signal end Sending, when the built-in address is the same as the data address, according to the first data packet The request instruction transmits the request instruction to the processing unit, and when the test result is received, controlling the first signal terminal or the second signal terminal to send the test result. The analog device of claim 2, wherein the first signal terminal is electrically connected to an inter-integrated circuit (I2C) bus bar, and the first signal terminal comprises: an open drain An open drain gate (OD) includes a control terminal, a first end and a second end. The first end is electrically connected to a ground end, and the second end is electrically connected to the internal integrated circuit bus And the control terminal is electrically connected to the signal transceiver unit. The analog device of claim 1, wherein the format of the first data packet conforms to an internal integrated circuit protocol. The analog device of claim 1, wherein the first data format conforms to a Peripheral Component Interconnect Express (PCIE), Serial Attached SCSI (SAS), or Serial ATA (Serial) Advanced Technology Attachment, SATA) format. The simulation device of claim 1, further comprising a memory module electrically connected to the processing module, wherein the processing module stores the test result in the memory module, and when When the first data packet is encapsulated, the processing module reads and sends the test result from the memory module. A hard disk backplane test system for testing multiple confluences on a hard disk backplane The row includes: a plurality of analog devices that are electrically connected to the bus bars, and the plurality of first bus bars are electrically connected to each other, and the analog devices are configured to analyze the bus bars And generating a plurality of test results; and a control device electrically connected to one of the simulation devices by a second bus bar for collecting the test results generated by the simulation devices. The hard disk backplane test system of claim 7, wherein a first one of the analog devices is electrically connected to one of the first bus bars, the first simulation device comprising: a processing module a group, configured to generate a test signal, analyze a feedback signal to generate a first test result, and when receiving a first data packet, selectively forward the first data packet according to a data address in the first data packet a data packet or a first data packet is sent to send the first test result; and an interface module is electrically connected to the processing module and the first bus bar for converting the test signal into a first The signal is transmitted to the first bus, and a second signal from the first bus is converted into the feedback signal, wherein the format of the first signal and the format of the second signal are both a first data format And different from the format of the test signal or the format of the feedback signal. The hard disk backplane test system of claim 7, wherein the busbars are internal integrated circuit busbars. The hard disk backplane test system of claim 8, wherein each of the analog devices has an open gate and is electrically connected to one of the bus bars.