TWI559546B - Semiconductor device, method of manufacturing the same and method of operating the same - Google Patents

Description

Semiconductor component, method of manufacturing same and method of operating same

The present invention relates to a semiconductor device, and more particularly to a high voltage semiconductor device, a method of fabricating the same, and a method of operating the same.

High-voltage component processes are widely used in power management ICs (PMICs), switching mode power supplies (SMPS), and light emitting diode (LED) drivers. In recent years, with the rise of environmental awareness, the demand for green energy with high conversion efficiency and low standby power consumption has been gradually taken into account, making LEDs widely used in lighting. In general, LED drivers can be divided into linear LED drivers and Switch mode LED drivers.

The high voltage linear LED circuit uses a High Voltage Depletion MOS (HV-DMOS) device or a High Voltage Junction Field Effect Transistor (HV-JFET) as a current source. However, HV-JFETs require a large drift region area. A reduced surface field (RESURF) is formed, and the pinch off characteristic of the HV-JFET is also less sensitive. In contrast, HV-DMOS can increase the drain current by using the gate-to-source voltage difference, where the HV-DMOS has a greater than the HV-JFET's drain current. Therefore, high voltage components typically use HV-DMOS to achieve the effect of reducing component area and increasing gate current.

The present invention provides a semiconductor device which can increase a drain current with only a small increase in area.

The method of fabricating the semiconductor device of the present invention can be compatible with existing high voltage semiconductor processes without the need for additional masks and processes.

The present invention provides a semiconductor device comprising a gold oxide semi-transistor, a nano-energy diode, and a high-resistance conductor structure. The gold oxide semi-transistor is located on the substrate and includes a high voltage well region having a first conductivity type, an isolation structure, a source region and a drain region having the first conductivity type, and a gate structure. A high pressure well zone is located in the substrate. An isolation structure is located on the high pressure well region. A source region is located in the high voltage well region of the first side of the isolation structure. A drain region is located in the high pressure well region on the second side of the isolation structure. A gate structure is located on the high voltage well region and extends over a portion of the isolation structure. The doping depth of the high voltage well region under the gate structure is less than the doping depth of the high voltage well region under the source region and the drain region. The nano-diode is located on the substrate, and includes an anode electrically connected to the base gate; and a cathode electrically connected to the gate structure. a high resistance conductor structure is located above the isolation structure, which is a continuous structure, a first end thereof and the drain region Electrically connected, and the second end thereof is electrically connected to the cathode of the nano-dipole and the gate structure.

According to an embodiment of the present invention, the booster diode includes a first well region having the first conductivity type, a first doping region having the second conductivity type, and the first conductivity type a base region, a second doped region having the first conductivity type, a third doped region having the first conductivity type, a second well region having the second conductivity type, and having the a fourth doped region of the second conductivity type. A first well zone is located in the substrate. A first doped region is located in the first well region. A base region is located in the first well region, wherein the base region is located below the first doped region. A second doped region is located in the first well region of the first side of the first doped region. A third doped region is located in the first well region of the second side of the first doped region. A second well zone is located in the substrate adjacent to the first well zone. A fourth doped region is located in the second well region.

The present invention also provides a semiconductor device including a MOS transistor, a nano-dipole, and a high-resistance conductor structure. a gold-oxygen semi-transistor is disposed on the substrate, and includes a high-voltage well region having a first conductivity type, an isolation structure, a source region and a drain region having the first conductivity type, a gate structure, and a second a first well region of the conductivity type, a first field region having the second conductivity type, and a first doping region having the second conductivity type. A high pressure well zone is located in the substrate. An isolation structure is located on the high pressure well region. A source region is located in the high voltage well region of the first side of the isolation structure. A drain region is located in the high pressure well region on the second side of the isolation structure. a gate structure is located on the high voltage well region, wherein the gate structure partially covers the isolation structure. A first well region is located within the high pressure well region between the isolation structure and the source region. The first field zone is located in the first well zone. The first doped region is located in the first field region, wherein the first doped region is electrically connected to a substrate gate and adjacent to the gate structure. The nano-diode is located on the substrate, and includes an anode electrically connected to the base gate; and a cathode electrically connected to the gate structure. a high-resistance conductor structure is located above the isolation structure, which is a continuous structure, a first end of which is electrically connected to the drain region, and a second end thereof and the cathode of the nano-dipole And electrically connecting the gate structure.

According to an embodiment of the invention, the booster diode includes: a second well region having the first conductivity type, a second doping region having the second conductivity type, and the first conductivity type a base region, a third doped region having the first conductivity type, a fourth doped region having the first conductivity type, a third well region having the second conductivity type, having the second a second field region of the conductivity type and a fifth doping region having the second conductivity type. A second well zone is located in the substrate. A second doped region is located in the second well region. A base region is located in the second well region, wherein the base region is located below the second doped region. A third doped region is located in the second well region of the first side of the second doped region. A fourth doped region is located in the second well region of the second side of the second doped region. A third well region is located in the substrate adjacent to the first well region. The second field zone is located in the third well zone. The fifth doped region is electrically connected to the base gate and is located in the second field region.

The present invention further provides a method of fabricating a semiconductor device comprising forming a gold oxide semi-transistor on a substrate. The substrate on the first side of the MOS transistor A nano-polarizer is formed on the surface. The nano-nanoductor includes an anode and a cathode, wherein the anode is electrically connected to the substrate gate, and the cathode is electrically connected to the MOS transistor. The step of forming the nano-dipole includes forming a first well region having a first conductivity type in the substrate, and forming a first doping region having a second conductivity type in the first well region, Forming a base region having the first conductivity type in the first well region, wherein the base region is located below the first doped region. Forming a second doped region having the first conductivity type in the first well region of the first side of the first doping region. Forming a third doped region having the first conductivity type in the first well region of the second side of the first doping region. Forming a second well region having the second conductivity type in the substrate, the second well region being adjacent to the first well region. Forming a fourth doped region having the second conductivity type in the second well region. A high resistance conductor structure is formed over the isolation structure, wherein the high resistance conductor structure is a continuous structure. The first doped region and the fourth doped region serve as anodes of the nano-dipole. The second doped region and the third doped region serve as the cathode of the nano-dipole. The first end of the high-resistance conductor structure is electrically connected to the drain region, the second end of the high-resistance conductor structure and the cathode of the nano-dipole and the galvanic half The gate of the transistor is electrically connected.

According to an embodiment of the invention, the step of forming the MOS transistor includes forming a high voltage well region having the first conductivity type in the substrate. An isolation structure is formed on the high voltage well region. A source region having the first conductivity type is formed in the high voltage well region on the first side of the isolation structure. A drain region having the first conductivity type is formed in the high voltage well region on the second side of the isolation structure. Yusho Forming the gate structure on the high voltage well region, wherein the gate structure partially covers the isolation structure, and the doping depth of the high voltage well region under the gate structure is smaller than the source region and the The doping depth of the high voltage well region below the drain region.

According to an embodiment of the invention, the step of forming the MOS transistor includes forming a high voltage well region having the first conductivity type in the substrate. An isolation structure is formed on the high voltage well region. A source region having the first conductivity type is formed in the high voltage well region on the first side of the isolation structure. A drain region having the first conductivity type is formed in the high voltage well region on the second side of the isolation structure. A gate structure is formed on the high voltage well region, wherein the gate structure partially covers the isolation structure. Forming a third well region having the second conductivity type in the high voltage well region between the isolation structure and the source region. Forming a first field region of the second conductivity type in the third well region. Forming a fifth doped region having the second conductivity type in the first field region, wherein the fifth doped region is electrically connected to the substrate gate and adjacent to the gate structure. The step of forming the nano-dipole includes forming a second field region in the second well region, wherein the fourth doped region is formed in the second field region.

The present invention also provides a semiconductor device including a MOS transistor, a nano+ diode, and a resistor. The gold oxide semi-transistor includes a gate, a source and a drain. The resistor has one end electrically connected to the drain, wherein the resistor has a high resistance value sufficient for most of the current to flow through the metal oxide half transistor. The nano-integrator includes a cathode and an anode, the cathode is electrically connected to the gate and the other end of the resistor, and the anode is electrically connected to the gate of the substrate.

The present invention also provides a method of operating the above semiconductor device, including The drain applies a drain voltage of 0V to 600V and a 0V or negative voltage at the base gate.

The present invention also provides a method of operating the above semiconductor device, comprising applying a drain voltage of 0V to 600V to the drain, applying 0V to the source, and applying a negative voltage to the gate of the substrate to cause the metal oxide transistor to be pinched. status.

Based on the above, the semiconductor device of the present invention includes a gold oxide semi-transistor, a nano-energy diode, and a high-resistance conductor structure. The high-resistance conductor structure can be used as a high-resistance resistor to provide a voltage drop to the nano-diode, and the booster diode can generate a voltage difference to the gate of the MOS transistor to increase the gate voltage. The bungee current increases. Since the high-resistance conductor structure as a high-resistance resistor can be disposed on the original isolation structure of the semiconductor element, there is no need to add an additional layout area, and the area of the addition diode is small. Therefore, the present invention can Increase the current only by adding a small amount of area. In addition, the present invention can utilize a patterned mask layer and ion implantation process to adjust the doping depth of the high voltage well region below the gate structure. In addition, the method of fabricating the semiconductor device of the present invention can be compatible with existing high voltage semiconductor processes without requiring additional masks and processes.

The above described features and advantages of the invention will be apparent from the following description.

10, 30, 40, 50‧‧‧ isolation structure

20‧‧‧High resistance conductor structure

70‧‧‧ drive circuit

74‧‧‧ dimming circuit

100, 500‧‧‧ base

100a‧‧‧ base

102, 102a, 102b, 102c, 202, 202a, 202b, 202c‧‧‧ high-pressure well area

104‧‧‧ source area

106‧‧‧Bungee Area

108‧‧‧ gate structure

108a‧‧‧ gate

108b‧‧‧gate dielectric layer

110‧‧‧ top

112‧‧‧light doped layer

114, 116, 128‧‧‧ well area

118‧‧‧Base area

120, 122, 124, 126, 132‧‧‧ doped areas

130, 134‧‧‧

136‧‧‧ buried layer

138‧‧‧ epitaxial layer

200, 400‧‧‧ gold oxide semi-transistor

300, 600‧‧‧Ginseng diode

D1, D2, D3‧‧‧ Depth

W‧‧‧Width

G‧‧‧ gate

D‧‧‧汲

S‧‧‧ source

R, R’‧‧‧ resistance

Z‧‧‧Genna

BG‧‧‧Base Gate

DIM‧‧‧ dimming control signal

1A is a schematic cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.

Figure 1B is a top view of the semiconductor component of Figure 1A.

2 is an equivalent circuit diagram of the semiconductor element of FIG. 1A.

3 is a schematic perspective cross-sectional view showing a semiconductor device according to a second embodiment of the present invention.

Fig. 4A is a schematic cross-sectional view taken along line A-A' of Fig. 3;

Fig. 4B is a schematic cross-sectional view taken along line B-B' of Fig. 3;

4C is a schematic cross-sectional view taken along line C-C' of FIG. 3.

4D is a schematic cross-sectional view taken along line D-D' of FIG. 3.

Figure 5 is a cross-sectional view showing a semiconductor device in accordance with another embodiment of the present invention.

Fig. 6 is an equivalent circuit diagram of a semiconductor element to which the present invention is applied to drive an LED.

Fig. 7 is an equivalent circuit diagram of an application example of the circuit of Fig. 6.

In the following embodiments, when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, and the second conductivity type is N type. The P-type doping is, for example, boron; the N-type doping is, for example, phosphorus or arsenic. In the present embodiment, the first conductivity type is N-type and the second conductivity type is P-type as an example, but the invention is not limited thereto. In addition, the same or similar component symbols represent the same or similar components.

1A is a schematic cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. Figure 1B is a top view of the semiconductor component of Figure 1A. Referring to FIG. 1A, a semiconductor device according to a first embodiment of the present invention includes a MOS transistor 200, a nano-dipole 300, and a high-resistance conductor structure 20. The gold oxide semi-crystal 200 is located on the substrate 100. The nano-dipole 300 is located on the substrate 100 adjacent to the MOS transistor 200. base The material of the bottom 100 is, for example, at least one material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. Substrate 100 can also be a blanket insulated (SOI) substrate.

The MOS transistor 200 may be a depleted MOS transistor, but is not limited thereto. The MOS semiconductor 200 includes a high voltage well region 102 having a first conductivity type, an isolation structure 10, a gate structure 108, a source region 104 having a first conductivity type, and a drain region 106 having a first conductivity type.

A high pressure well region 102 having a first conductivity type is located in the substrate 100. In the embodiment of the present invention, the high pressure well region 102 can be divided into three parts of the high pressure well region 102a, 102b, and 102c. The high pressure well region 102c is located between the high pressure well region 102a and the high pressure well region 102b. More specifically, the high voltage well region 102c is located below the gate structure 108 with a doping depth D1 that is less than the doping depths D2, D3 of the high voltage well region 102 below the source region 104 and the drain region 106. The method of forming the high voltage well regions 102a, 102b, 102c can form a patterned mask layer on the substrate 100. The patterned mask layer overlies the substrate 100 that is intended to form the high voltage well region 102c, exposing the substrate 100 that is intended to form the high voltage well regions 102a, 102b. Next, an ion implantation process is performed to form high pressure well regions 102a, 102b. After that, a thermal process is performed. The doping implanted in the high voltage well regions 102a, 102b diffuses into the lower region of the gate structure 108 to form the high voltage well region 102c. Since the gradient of the doping concentration is different, the doping depth of the high pressure well region 102c formed by diffusion may be smaller than the doping depth of the high voltage well regions 102a, 102b. In one embodiment, the doping implanted in the high voltage well region 102 is, for example, phosphorus or arsenic, and the doping amount is, for example, 1 × 10 ¹¹ /cm ² to 8 × 10 ¹² /cm ² .

The isolation structure 10 is located on the high pressure well region 102. The material of the isolation structure 10 is, for example, doped or undoped yttria, low-stress yttrium nitride, ytterbium oxynitride or a combination thereof, and the method of forming the same can utilize local area thermal oxidation (LOCOS) or shallow trench isolation ( STI) or deep trench isolation (DTI).

A source region 104 having a first conductivity type is located in the high voltage well region 102 on the first side of the isolation structure 10. A drain region 106 having a first conductivity type is located in the high voltage well region 102 on the second side of the isolation structure 10. The source region 104 and the drain region 106 can be formed by forming a patterned mask layer and performing an ion implantation process. In one embodiment, the doping of the source region 104 and the drain region 106 is, for example, phosphorus or arsenic, and the doping amount is, for example, 8×10 ¹⁴ /cm ² to 1×10 ¹⁶ /cm ² .

The gate structure 108 is located on the high voltage well region 102 and covers a portion of the isolation structure 10. More specifically, the gate structure 108 includes a gate 108a and a gate dielectric layer 108b. The method of forming the gate dielectric layer 108b and the gate 108a may first form a gate dielectric material layer and a gate material layer. The material of the gate material layer includes polysilicon, metal, metal halide or a combination thereof, and the formation method is, for example, chemical vapor deposition. The material of the gate dielectric material layer is, for example, hafnium oxide, tantalum nitride or a high dielectric constant material having a dielectric constant of more than 4. The formation method is, for example, thermal oxidation or chemical vapor deposition. Thereafter, the gate material layer and the gate dielectric material layer are patterned by a lithography and etching process.

In the present embodiment, applying a voltage to the substrate gate causes the MOS transistor 200 to reach a pinch off state. Therefore, the clamping voltage of the MOS transistor 200 can be adjusted by the high-pressure well region 102 of different doping depths. In this embodiment, since the doping depth D1 of the high voltage well region 102c is lower than the high voltage The doping depths D2, D3 of the well regions 102a, 102b.

In an embodiment, the MOS semiconductor 200 may further include a top layer 110 having a second conductivity type and a lightly doped layer 112 having a first conductivity type. The top layer 110 is located in the high pressure well region 102 below the isolation structure 10. The top layer 110 has the effect of reducing the surface electric field (RESURF), thereby increasing the breakdown voltage of the MOS transistor 200. The top layer 110 can be formed by forming a patterned mask layer and performing an ion implantation process. In one embodiment, the doping implanted in the top layer 110 is, for example, boron, and the doping amount is, for example, 5 × 10 ¹¹ /cm ² to 5 × 10 ¹³ /cm ² . The lightly doped layer 112 is between the isolation structure 10 and the top layer 110. The lightly doped layer 112 can reduce the on-resistance of the region to increase the gate current of the MOS transistor 200. The lightly doped layer 112 can be formed by forming a patterned mask layer and performing an ion implantation process. In one embodiment, the doping of the lightly doped layer 112 is, for example, phosphorus or arsenic, and the doping amount is, for example, 5 × 10 ¹¹ /cm ² to 2 × 10 ¹³ /cm ² .

The high resistance conductor structure 20 is located above the isolation structure 10. Although the high resistance conductor structure 20 in the cross-sectional view 1A is a plurality of portions separated from each other. However, the high resistance conductor structure 20 of the present invention is shown as a continuous structure (Fig. 1B). Referring to FIG. 1B, the first end of the high-resistance conductor structure 20 is electrically connected to the drain region 106, and the second end of the high-resistance conductor structure 20 is electrically connected to the gate structure 108 and the Zener diode 300. connection. Incidentally, although the semiconductor element shown in FIG. 1B is circular and the high-resistance conductor structure 20 is spiral or annular, the invention is not limited thereto. The shape of the semiconductor device of the present invention can be designed according to actual needs, and the shape thereof can be circular, elliptical, and octagonal or a combination thereof; and the high resistance conductor structure 20 It can be changed in accordance with the shape of the semiconductor element. In addition, the semiconductor device of other embodiments of the present invention may also utilize a multi-channel to adjust the drain current and its saturation current.

In the present embodiment, the high resistance conductor structure 20 can be considered as a high resistance resistor. The method of forming the high-resistance conductor structure 20 is, for example, forming a layer of a conductor material, which is then patterned using a lithography and etching process. The material of the conductor material layer is, for example, doped polysilicon, non-doped polysilicon or a combination thereof, and the formation method thereof can be performed by chemical vapor deposition. The resistance of the high resistance conductor structure 20 described above can be adjusted using the dose of the ion implant dopant. In one embodiment, the doping implanted in the high resistance conductor structure 20 is, for example, phosphorus, and the doping dose is, for example, 1 x 10 ¹³ to 1 x 10 ¹⁵ /cm ² .

The nano-dipole 300 is adjacent to the MOS transistor 200. The nano-dipole 300 includes a well region 114 having a first conductivity type, a well region 116 having a second conductivity type, a base region 118 having a first conductivity type, and a doping region 120 having a second conductivity type, having a A doped region 122 of a conductivity type, a doped region 124 having a first conductivity type, and a doped region 126 having a second conductivity type. The doped region 120 and the doped region 126 can serve as an anode of the nano-dipole 300 and be electrically connected to the substrate gate (BG). The doped region 122 and the doped region 124 can serve as a cathode of the nano-dipole 300, and are electrically connected to the gate 108a of the MOS transistor 200 and the high-resistance conductor structure 20.

In more detail, the well region 114 having the first conductivity type is located in the substrate 100. The well region 114 can be formed by forming a patterned mask layer and performing an ion implantation process. In one embodiment, the doping implanted in well region 114 is, for example, phosphorus or arsenic, and the doping dose is, for example, 8 x 10 ¹¹ /cm ² to 4 x 10 ¹³ /cm ² .

A well region 116 having a second conductivity type is located in the substrate 100 between the high pressure well region 102 and the well region 114. The well region 116 can be formed by forming a patterned mask layer and performing an ion implantation process. In one embodiment, the doping implanted in well region 116 is, for example, boron, and the doping dose is, for example, 5 x 10 ¹² /cm ² to 1 x 10 ¹⁴ /cm ² .

Doped region 120 having a second conductivity type is located in well region 114; doped region 126 having a second conductivity type is located in well region 116. In one embodiment, the doping region 120 and the doping region 126 can serve as an anode of the nano-dipole 300 and be electrically connected to the substrate gate BG. The doped region 120 and the doped region 126 can be formed by forming a patterned mask layer and performing an ion implantation process. In one embodiment, the doping of the doped region 120 and the doped region 126 is, for example, boron, and the doping amount is, for example, 8×10 ¹⁴ /cm ² to 1×10 ¹⁶ /cm ² .

The doped region 122 having the first conductivity type and the doped region 124 having the first conductivity type are located in the well region 114 on the first side and the second side of the doping region 120, respectively. The doped region 122 and the doped region 124 can serve as a cathode of the nano-polarizer 300, and are electrically connected to the gate 108a and the high-resistance conductor structure 20. The doped region 122 and the doped region 124 can be formed by forming a patterned mask layer and performing an ion implantation process. In one embodiment, the doping of the doped region 122 and the doped region 124 is, for example, phosphorus or arsenic, and the doping amount is, for example, 8×10 ¹⁴ /cm ² to 1×10 ¹⁶ /cm ² .

A base region 118 having a first conductivity type is located in the well region 114 below the doped region 120. The breakdown voltage of the Zener diode 300 can be adjusted by the difference in doping concentration of the base region 118. The base region 118 can be formed by forming a patterned mask layer and performing an ion implantation process. In one embodiment, the doping implanted in the base region 118 is, for example, phosphorus or arsenic, and the doping amount is, for example, 8 × 10 ¹² /cm ² to 2 × 10 ¹³ /cm ² .

The nano-dipole 300 can further include an isolation structure 30 and an isolation structure 40. The isolation structure 30 is located on the substrate 100 between the doped region 126 of the nano-diode 300 and the source region 104 of the MOS transistor 200. The isolation structure 40 is located between the well region 114 and the well region 116. The material of the isolation structure 30 and the isolation structure 40 is, for example, doped or undoped yttrium oxide, low-stress yttrium nitride, ytterbium oxynitride or a combination thereof, and the method for forming the same can be performed by local area thermal oxidation method or shallow trench isolation method. Or deep trench isolation method.

In short, in the first embodiment of the present invention, the drain current of the MOS transistor 200 can be increased by the high resistance conductor structure 20 having the high resistance resistance characteristic and the nano FET 300. Since the high resistance conductor structure 20 can be disposed on the isolation structure 10, it is only necessary to increase the area of the nano diode 300, that is, the drain current can be greatly increased. In addition, the pinch-off voltage of the MOS transistor 200 can be reduced by reducing the doping depth D1 of the high voltage well region 102c below the gate structure 108. In addition, as the temperature increases, the drain current of the depleted MOS transistor 200 decreases, and the breakdown voltage of the Zener diode 300 increases to compensate for the effect of the temperature increase.

2 is an equivalent circuit diagram of FIG. 1A. Referring to FIG. 2, the semiconductor device of the present invention includes a MOS transistor, a resistor (R), and a Zener diode (Z). The gold-oxide semi-transistor includes a gate (G), a source (S), and a drain (D). The resistor (R) has one end electrically connected to the drain (D). The resistor (R) has a high resistance value sufficient to allow most of the current to flow through the MOS transistor. The nano-polarizer (Z) includes a cathode and an anode, The cathode is electrically connected to the other end of the gate (G) and the resistor (R), and the anode is electrically connected to the base gate (BG).

When a high voltage (Vdd) is applied to the drain (D) of the MOS transistor, most of the current (for example, greater than 99%) is drained by the drain due to the high resistance of the resistor (R). D) Flow through the MOS transistor, only a small fraction (for example, less than 1%) will flow through the high resistance resistor (R). When the current flows through the resistor (R), a voltage drop occurs. At this time, the diode (R) is reverse biased, so that the diode (Z) generates a voltage difference (for example, about 4-10V). This voltage difference is applied to the gate (G) of the MOS transistor to increase the voltage of the gate (G). Since the gate (G) voltage is increased, the drain current (D) is increased. In addition, the pinch off of the MOS transistor can be controlled by the applied voltage of the substrate gate (BG). By applying a voltage of, for example, 0 V or a negative voltage to the substrate gate (BG), the metal oxide semiconductor can be brought into a pinch state when a negative voltage is applied. For example, a negative 15V is the clamping voltage.

Referring to FIG. 2, in operation, for example, a voltage of 0V to 5V (Vdd) is applied to the drain D, and the base gate (BG) and the source (S) are 0V, and most of the current flows to the gold oxide. In the semi-transistor, the remaining current (about 1×10 ^-7 A) flows to the resistor R and the Zener diode (Z), and the gate source voltage (Vgs) rises from 0V to 5V, and the drain current increases with Vgs. increase.

In addition, when the voltage (Vdd) applied to the drain D is 5.1V to 600V and the base gate (BG) and the source (S) are 0V, most of the current flows to the gold oxide half transistor, and the remaining current (about 1 × 10 ^-6 A) flows to the resistor R and the Zener diode Z. When the gate source voltage (Vgs) rises to 5V, the drain current increases as Vdd increases until Vdd is greater than a predetermined value (eg, 20V), at which point the drain current is a saturated current.

In addition, a voltage Vdd of 15V to 600V is applied to the drain D, and the source S is 0V. At this time, most of the current flows to the MOS transistor, and the remaining current flows to the resistor (R) and the Zener diode (Z). When the gate source voltage (Vgs) rises to 5V, the drain current is saturated current and the gate current increases as the Vgs voltage increases. When the base gate (BG) applies a negative voltage to 15 V, the drain current is 0 A, at which time the gold-oxygen semiconductor is in a pinched state.

3 is a schematic perspective cross-sectional view showing a semiconductor device according to a second embodiment of the present invention. Fig. 4A is a schematic cross-sectional view taken along line A-A' of Fig. 3; Fig. 4B is a schematic cross-sectional view taken along line B-B' of Fig. 3; 4C is a schematic cross-sectional view taken along line C-C' of FIG. 3. 4D is a schematic cross-sectional view taken along line D-D' of FIG. 3.

Referring to FIGS. 3 through 4B, the semiconductor device of the second embodiment of the present invention includes a MOS transistor 400, a nano-dipole 600, and a high-resistance conductor structure 20. The MOS transistor 400 and the nano-energy diode 600 are located on the substrate 100. The material of the substrate 100 is as described in the above embodiments, and details are not described herein again.

The gold-oxide semi-transistor 400 may be a depleted metal oxide semi-transistor, but is not limited thereto. The MOS transistor 400 includes a gate structure 108, a source region 104 having a first conductivity type, a drain region 106 having a first conductivity type, a high voltage well region 202 having a first conductivity type, and a second conductivity type The well region 128, the field region 130 having the second conductivity type, the doping region 132 having the second conductivity type, the isolation structure 10, and the isolation structure 50.

Referring to FIG. 3, FIG. 4B and FIG. 4D, the high voltage well region 202 is located in the substrate 100. Specifically, the high pressure well region 202 can be divided into three parts: a high pressure well region 202a, a high pressure well region 202b, and a high pressure well region 202c. The high pressure well region 202a and the high pressure well region 202b may be connected to each other by the high pressure well region 202c. The high pressure well region 202c may have the same doping depth as the high pressure well region 202a and the high pressure well region 202b. In other words, this embodiment is different from the first embodiment in that the doping depth of the high voltage well region 202c located below the gate structure 108 may not require a doping depth higher than that of the high voltage well region 202a and the high voltage well region 202b. shallow. In addition, referring to FIG. 4C, in the present embodiment, the clamping voltage of the MOS transistor 400 can be adjusted by adjusting the width W of the high voltage well region 202c.

The high pressure well region 202a, the high pressure well region 202b, and the high pressure well region 202c of the high pressure well region 202 can be formed by forming a single patterned mask layer and performing an ion implantation process. In one embodiment, the doping implanted in the high pressure well region 202 is, for example, phosphorus or arsenic, and the doping amount is, for example, 1 × 10 ¹¹ /cm ² to 8 × 10 ¹² /cm ² .

Referring to FIGS. 3 and 4B, the gate structure 108 is located on the high voltage well region 202c and covers a portion of the isolation structure 10. The gate structure 108 includes a gate 108a and a gate dielectric layer 108b. The method of forming the gate electrode 108a and the gate dielectric layer 108b will not be described again as described above. The source region 104 and the drain region 106 are located in the high voltage well region 202b and are separated from the isolation structure 50 at the gate structure 108. The source region 104 and the drain region 106 can be formed by forming a patterned mask layer and performing an ion implantation process. In one embodiment, the doping of the source region 104 and the drain region 106 is, for example, phosphorus or arsenic, and the doping amount is, for example, 8×10 ¹⁴ /cm ² to 1×10 ¹⁶ /cm ² .

A well region 128 having a second conductivity type is located in the substrate 100. More specifically, from FIG. 4A, the well region 128 is located between the high pressure well region 202a and the high pressure well region 202b. From FIG. 4C, the high pressure well region 202c is sandwiched between the two portions of the well region 128. The doping depth of the well region 128 is less than the doping depth of the high voltage well regions 202a, 202b, 202c. The well region 128 can be formed by forming a patterned mask layer and performing an ion implantation process. In one embodiment, the doping implanted in well region 128 is, for example, boron, and the doping dose is, for example, 8 x 10 ¹¹ /cm ² to 8 x 10 ¹³ /cm ² .

Field region 130 having a second conductivity type is located in well region 128; doped region 132 having a second conductivity type is located in field region 130. The doping depth of the doping region 132 is, for example, 1000 Å to 4000 Å. The doping region 132 can be electrically connected to the substrate gate (BG). By controlling the voltage applied to the substrate gate (BG) (for example, applying 0V or a negative voltage), the gold-oxygen semiconductor transistor 400 can be clamped. . The doped region 132 can be formed by forming a patterned mask layer and performing an ion implantation process. Since the doped region 132 can be formed via ion implantation, the doping depth or profile of the doped region 132 can be adjusted by controlling the energy of ion implantation. In an embodiment, the doping implanted in the doping region 132 is, for example, boron, and the doping amount is, for example, 8 × 10 ¹⁴ /cm ² to 1 × 10 ¹⁶ /cm ² .

The doping concentration of the field region 130 is greater than the doping concentration of the well region 128, which can be used to lower the clamping voltage of the MOS transistor 400 such that the substrate gate (BG) electrically connected to the doping region 132 makes the gold oxide The half transistor 400 is more likely to reach the pinch state. In one embodiment, the field region 130 has a doping concentration that is 80 to 120 times the doping concentration of the well region 128. Field region 130 can be formed by forming a patterned mask layer and performing an ion implantation process. In one embodiment, the doping implanted in the field region 130 is, for example, boron, and the doping amount is, for example, 1 × 10 ¹² /cm ² to 1 × 10 ¹⁴ /cm ² .

The isolation structure 10 is located between the drain region 106 and the doped region 132. The isolation structure 50 is located between the source region 104 and the doped region 132. The material of the isolation structure 10 and the isolation structure 50 is, for example, doped or undoped yttrium oxide, low-stress yttrium nitride, ytterbium oxynitride or a combination thereof, and the method for forming the same can be performed by local area thermal oxidation method or shallow trench isolation method. Or deep trench isolation method.

In an embodiment, the MOS transistor 400 may further include a top layer 110 having a second conductivity type and a lightly doped layer 112 having a first conductivity type and a high resistance conductor structure 20. The position, material and formation method of the top layer 110 and the lightly doped layer 112 are as described in the first embodiment above, and details are not described herein again.

Referring to FIG. 4B, in the present embodiment, the doping depth of the high voltage well region 202c of the MOS transistor 400 need not be controlled shallow to increase the sensitivity of the pinch-off characteristics of the MOS transistor 400. As shown in FIG. 3, the substrate gate (BG) can control the MOS transistor 400 to the pinched state via the surface of the doped region 132. Moreover, the clamping voltage of the MOS transistor 400 can be adjusted by the doping concentration of the field region 130. The higher the doping concentration of the field region 130, the smaller the pinch voltage of the MOS transistor 400.

Referring to FIG. 3 and FIG. 4A, the adder diode 600 is located on the substrate 100 on the first side of the MOS transistor 400. The nano-dipole 600 of FIG. 4A is similar to the nano-dipole 300 of FIG. 1A. The addition diode 600 has a well region 114 having a first conductivity type, a well region 116 having a second conductivity type, a base region 118 having a first conductivity type, a doping region 120 having a second conductivity type, and having One conductivity type doped region 122. A doped region 124 having a first conductivity type and a doped region 126 having a second conductivity type further have a field region 134. The structure of the nano-substrate 600 of FIG. 3 is the same as that of the semiconductor diode 300 of FIG. 1A, and details are not described herein again. Of particular note, the difference is that the Zener diode 600 of FIG. 3 has a field region 134. Field region 134 is located in well region 116 and doped region 126 is located in field region 134. Since the doping concentration of the field region 134 is greater than the doping concentration of the well region 116, it can be used to lower the clamping voltage of the MOS transistor 400, so that the substrate gate electrically connected to the doping region 126 is more susceptible to gold oxide. The half transistor 400 is in a pinched state. In one embodiment, the field region 134 has a doping concentration that is 100 to 130 times the doping concentration of the well region 116.

The high-resistance conductor structure 20 is also used as a high-resistance resistor, and its position, material, connection relationship, and formation method are as described in the above first embodiment, and will not be described herein.

In the present embodiment, the base gate (BG) can bring the MOS transistor 400 into a pinched state via the surface of the doped region 132. Moreover, since the doping concentration of the field region 130 of the present invention is greater than the doping concentration of the well region 128, the pinch voltage of the MOS transistor 400 can be reduced. Therefore, the doped region 132 electrically connected to the substrate gate can more easily turn off the MOS transistor 400. Moreover, the doping region 132 is formed by ion implantation rather than simply by thermal diffusion, and thus, a desired profile can be formed. In addition, the width W of the high voltage well region 202c can also be used to adjust the clamping voltage of the MOS transistor 400. When the width W of the high voltage well region 202c is smaller, the pinch voltage of the MOS transistor 400 is smaller.

Figure 5 is a cross-sectional view showing a semiconductor device in accordance with another embodiment of the present invention. Referring to FIG. 5, the semiconductor device of FIG. 5 is similar to the semiconductor device of FIG. 1A, and the difference between the two is that the substrate 500 of FIG. 5 includes a substrate 100a, an epitaxial layer 138 having a second conductivity type, and a first conductive layer. Type buried layer 136. The substrate 100a is, for example, at least one material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. The epitaxial layer 138 has a second conductivity type, such as an epitaxial layer having a P-type doping, located on the substrate 100a. The material of the epitaxial layer 138 includes tantalum or tantalum carbide. In one embodiment, the doping of the epitaxial layer 138 is, for example, boron, and the doping amount is, for example, 8 × 10 ¹² /cm ² to 8 × 10 ¹⁴ /cm ² . The buried layer 136 has a first conductivity type, such as an N-type buried layer, which is located between the epitaxial layer 138 and the substrate 100a. The buried layer 136 can increase the breakdown voltage of the semiconductor element. The buried layer 136 may be formed on the surface of the substrate 100a on which the oxynitride 200 is to be formed by forming a patterned mask layer and performing an ion implantation process before forming the epitaxial layer 138. In one embodiment, the doping implanted in the buried layer 136 is, for example, phosphorus or arsenic, and the doping amount is, for example, 1 × 10 ¹³ /cm ² to 1 × 10 ¹⁵ /cm ² .

The MOS transistor 200, the nano-diode 300, and the high-resistance conductor structure 20 are formed in or on the epitaxial layer 138 having the second conductivity type, and the method of forming the same is as described above. This will not be repeated here.

Fig. 6 is an equivalent circuit diagram of a semiconductor element to which the present invention is applied to drive an LED. Referring to FIG. 6, the semiconductor device of the present invention can be applied to an example of a driving circuit of an LED. The semiconductor device (driving circuit) 70 of the present invention is connected to the negative side of the LED string. In the driving circuit 70, the substrate gate (BG) is grounded and the source (S) is connected to the ground via a resistor (R'), and the drain D is connected to the cathode of the LED string LED. This resistance (R') is optional, but it is omitted from actual requirements. drive In the above-described operation mode, the dynamic circuit 70 provides a large driving current (drain current) to drive the LED string LED. As described above, the semiconductor element circuit of the present invention can provide a large drain current without increasing the area of the element layout too much. Therefore, with the circuit design of the semiconductor element circuit of the present invention, it is possible to provide a large drain current to drive or dim the LED without excessively increasing the area.

Fig. 7 is an equivalent circuit diagram showing an application example of the circuit for driving the LED of Fig. 6. As shown in FIG. 7, in this example, a dimming circuit 74 is further added to FIG. The brightness of the LED string LED is adjusted by inputting the dimming control signal DIM.

In summary, the semiconductor device of the present invention includes a MOS transistor, a nano-diode, and a high-resistance resistor. The high-resistance resistor provides a voltage drop to the Zener diode, causing the Zener diode to create a voltage differential to the gate of the MOS transistor, increasing the gate voltage and increasing the gate current. Since the high-resistance conductor structure as a high-resistance resistor can be disposed on the original isolation structure of the semiconductor element, there is no need to add an additional layout area, and the area of the addition diode is small. Therefore, the present invention can Increase the current only by adding a small amount of area. Furthermore, the nano-dipole of the present invention has the effect of stabilizing the voltage. Additionally, in some embodiments, the present invention can reduce the MOS half-electrode clamping voltage by reducing the doping depth of the high pressure well region or reducing the width of the high voltage well region. In another embodiment, the doped region in which the nano-polarizer is electrically connected to the substrate gate can be brought into a pinch state via the surface of the doped region. In other words, the pinch-off characteristics of the MOS transistor will be more sensitive. Furthermore, the clamping voltage of the MOS transistor can also be reduced by the setting of the field region. In addition, the method for fabricating the semiconductor device of the present invention can be compared with the existing high voltage semiconductor process. No additional reticle and process is required. Further, the circuit design of the semiconductor element circuit of the present invention can provide a large drain current to drive or dim the LED without excessively increasing the area. In addition, by adding a dimming circuit to the circuit design of the semiconductor element circuit of the present invention, the brightness of the LED array LED can be adjusted by inputting the dimming control signal DIM.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

G‧‧‧ gate

D‧‧‧汲

S‧‧‧ source

R‧‧‧resistance

Z‧‧‧Genna

BG‧‧‧Base Gate

Claims (7)

A semiconductor device comprising: a MOS transistor, on a substrate, wherein the MOS transistor comprises: a high voltage well region having a first conductivity type, located in the substrate; an isolation structure located at the a high-voltage well region; a source region having the first conductivity type, located in the high-voltage well region of a first side of the isolation structure; and a drain region having the first conductivity type, located in the isolation structure a high voltage well region on a second side; and a gate structure located on the high voltage well region and extending over a portion of the isolation structure, wherein a doping depth of the high voltage well region below the gate structure is less than a source region and a doping depth of the high voltage well region below the drain region; a nano-dipole on the substrate, wherein the nano-reactor comprises: an anode, and a substrate gate electrical And a cathode electrically connected to the gate structure; and a high resistance conductor structure located above the isolation structure, wherein the high resistance conductor structure is a continuous structure, wherein the high resistance conductor structure a first end and the Region is electrically connected, and the high resistance conductor structure connected to a second terminal of the diode is satisfied by the cathode electrode and the gate structure electrically. The semiconductor device of claim 1, wherein the nano-dipole comprises: a first well region having the first conductivity type, located in the substrate; a first doped region having a second conductivity type is located in the first well region; a substrate region having the first conductivity type is located in the first well region, wherein the base region is located in the first doping region a second doped region having the first conductivity type, located in the first well region of a first side of the first doped region; and a third doping having the first conductivity type a miscellaneous region located in the first well region of a second side of the first doped region; a second well region having the second conductivity type located in the substrate adjacent to the first well region; And a fourth doped region having the second conductivity type is located in the second well region. A semiconductor device comprising: a MOS transistor, on a substrate, wherein the MOS transistor comprises: a high voltage well region having a first conductivity type, located in the substrate; an isolation structure located at the a high-voltage well region; a source region having the first conductivity type, located in the high-voltage well region of a first side of the isolation structure; and a drain region having the first conductivity type, located in the isolation structure a second side of the high voltage well region; a gate structure located on the high voltage well region, wherein the gate structure partially covers the isolation structure; and a first well region having a second conductivity type, located in the isolation Within the high pressure well region between the structure and the source region; a first field region having the second conductivity type is located in the first well region; and a first doping region having the second conductivity type is located in the first field region, wherein the first doping region The region is electrically connected to a substrate and adjacent to the gate structure; a nano-dipole is disposed on the substrate, wherein the nano-reactor comprises: an anode electrically connected to the substrate gate And a cathode electrically connected to the gate structure; and a high resistance conductor structure located above the isolation structure, wherein the high resistance conductor structure is a continuous structure, wherein the high resistance conductor structure The first end is electrically connected to the drain region, and a second end of the high resistance conductor structure is electrically connected to the cathode of the nano diode and the gate structure. The semiconductor device of claim 3, wherein the nano-dipole comprises: a second well region having the first conductivity type, located in the substrate; and a second having the second conductivity type a doped region, located in the second well region; a substrate region having the first conductivity type, located in the second well region, wherein the substrate region is located below the second doped region; having the first conductive region a third doped region of the type, located in the second well region of a first side of the second doped region; a fourth doped region having the first conductivity type, located in the second doped region In a second well area of a second side; a third well region having the second conductivity type is located in the substrate adjacent to the first well region; a second field region having the second conductivity type is located in the third well region; A fifth doped region of the second conductivity type is electrically connected to the base gate and is located in the second field region. A method of fabricating a semiconductor device, comprising: forming a MOS semiconductor on a substrate; forming a nano-dipole on the substrate on a first side of the MOS transistor, wherein the nucleus The pole body includes an anode and a cathode, wherein the anode is electrically connected to a substrate gate, and the cathode is electrically connected to the MOS transistor, wherein the step of forming the nano diode comprises: Forming a first well region having a first conductivity type; forming a first doped region having a second conductivity type in the first well region; forming the first conductivity type in the first well region a base region, wherein the base region is located below the first doped region; forming a second doping having the first conductivity type in the first well region of a first side of the first doped region a third doped region having the first conductivity type is formed in the first well region of a second side of the first doped region; and a second conductivity type is formed in the substrate a second well region adjacent to the first well region; formed in the second well region A second conductivity type fourth doped And forming a high-resistance conductor structure over the isolation structure, wherein the high-resistance conductor structure is a continuous structure, wherein the first doped region and the fourth doped region serve as the nano-dipole The anode of the body is electrically connected to a substrate gate; the second doped region and the third doped region serve as the cathode of the nano-dipole; and a first of the high-resistance conductor structure The terminal is electrically connected to the drain region, and a second end of the high resistance conductor structure is electrically connected to the cathode of the nano diode and a gate of the gate structure of the MOS transistor . The method of manufacturing a semiconductor device according to claim 5, wherein the step of forming the MOS transistor comprises: forming a high-voltage well region having the first conductivity type in the substrate; Forming an isolation structure; forming a source region having the first conductivity type in the high voltage well region on a first side of the isolation structure; forming in the high voltage well region on a second side of the isolation structure a drain region having the first conductivity type; and forming the gate structure on the high voltage well region, wherein the gate structure partially covers the isolation structure, and the doping of the high voltage well region under the gate structure The depth is less than the doping depth of the source region and the high voltage well region below the drain region. A method of manufacturing a semiconductor device according to claim 5, wherein The step of forming the MOS transistor includes: forming a high voltage well region having the first conductivity type in the substrate; forming an isolation structure on the high voltage well region; and forming a first side of the isolation structure Forming a source region having the first conductivity type in the high voltage well region; forming a drain region having the first conductivity type in the high voltage well region on a second side of the isolation structure; Forming a gate structure on the well region, wherein the gate structure partially covers the isolation structure; forming a third well region having the second conductivity type in the high voltage well region between the isolation structure and the source region Forming a first field region having the second conductivity type in the third well region; and forming a fifth doping region having the second conductivity type in the first field region, wherein the fifth doping region The impurity region is electrically connected to the substrate gate and adjacent to the gate structure; and the step of forming the nano diode includes: forming a second field region in the second well region, wherein the fourth region is formed A miscellaneous zone is formed in the second field zone.