TWI559274B - Display the drive circuit of the panel - Google Patents

Description

Display panel drive circuit

The present invention relates to a driving circuit, and more particularly to a driving circuit for a display panel.

Press, the general display panel has a scan driving circuit and a data driving circuit to control a plurality of pixels to display a picture. However, the general scan driving circuit has a complex level conversion circuit, and the level conversion circuit requires a relatively large circuit layout area, so a large area is required in the scan driving circuit to layout the level conversion circuit, thereby resulting in higher manufacturing. cost. In addition, with the rise of energy-saving awareness, the scan drive circuit needs to reduce power consumption and meet the requirements of energy saving.

Therefore, the present invention provides a driving circuit for a display panel.

One of the objectives of the present invention is to provide a driving circuit for a display panel that uses a control signal to control a first level control circuit and a second level control circuit to reduce the number of level conversion circuits.

One of the objects of the present invention is to provide a driving circuit for a display panel that utilizes a buffer circuit to reduce power consumption of the driving circuit.

To achieve the above object, the present invention is a driving circuit for a display panel that generates a plurality of driving signals to drive at least one scanning line. Drive circuit includes complex level conversion circuit a decoding circuit and a complex output circuit, the decoding circuit comprising a first level control circuit and a plurality of second level control circuits. The level conversion circuit generates a plurality of control signals; the first level control circuit receives the control signals to determine that the level of at least one of the plurality of decoded signals is a first level; the second level control circuits respectively Receiving one of the control signals to determine that the levels of the other decoded signals are a second level; and the output circuits generate the driving signals according to the decoded signals, and at least one of the driving signals has A drive level is used to drive at least one scan line.

To achieve the above object, the driving circuit of the display panel of the present invention includes a buffer circuit that causes switching of the transistors to be asynchronously switched to reduce power consumption.

10‧‧‧bit conversion circuit

20‧‧‧First level control circuit

30‧‧‧Second level control circuit

40‧‧‧Output circuit

41‧‧‧ buffer circuit

42‧‧‧First output transistor

43‧‧‧Second output transistor

44, 47‧‧‧Optoelectronics

45‧‧‧ Third output transistor

46‧‧‧fourth output transistor

50‧‧‧ bias circuit

Bias‧‧‧bias signal

D0, D1, D2‧‧‧ input signal

D0A, D0B, D1A, D1B, D2A, D2B‧‧‧ control signals

G0~G7‧‧‧ drive signal

M1~M16‧‧‧O crystal

S0~S7‧‧‧ decoding signal

VGL, GND‧‧‧ first level

VPP, VGH‧‧‧ second level

1 is a circuit diagram of a first embodiment of a driving circuit of a display panel of the present invention; and FIG. 2 is a circuit diagram of a second embodiment of a driving circuit of the display panel of the present invention; Figure: is a circuit diagram of a third embodiment of a driving circuit of a display panel of the present invention; fourth drawing: a circuit diagram of a fourth embodiment of a driving circuit of the display panel of the present invention; It is a circuit diagram of a first embodiment of the second level control circuit and the output circuit of the present invention; FIG. 6 is a circuit diagram of a fifth embodiment of the driving circuit of the display panel of the present invention; Figure: is a circuit diagram of a sixth embodiment of a driving circuit of the display panel of the present invention; Figure 8 is a circuit diagram of a second embodiment of the output circuit of the present invention; and a ninth diagram: a waveform diagram of a second embodiment of the driving circuit of the display panel of the present invention.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

For a better understanding and understanding of the features and advantages of the present invention, the preferred embodiments and the detailed description are as follows: please refer to the first figure, which is the present invention. A circuit diagram of a first embodiment of a drive circuit of a display panel. As shown in the figure, the driving circuit of the present invention generates complex driving signals G0~G7 for driving the plurality of scanning lines so that the display panel can display a picture. The driving circuit comprises a complex level conversion circuit 10, a decoding circuit and a complex output circuit 40. The decoding circuit comprises a first level control circuit 20 and a plurality of second level control circuits 30. The level conversion circuits 10 respectively receive the input signals D0~D2 and convert the levels of the input signals D0~D2 to generate a complex control signal. D0A~D2A and D0B~D2B, the control signals D0A~D2A and D0B~D2B are used to control the decoding circuit. In other words, the control signals D0A~D2A and D0B~D2B are used to control the first level control circuit 20 and the These second level control circuits 30.

The decoding circuit includes a plurality of transistors, and is coupled to the level conversion circuits 10 and receives the control signals D0A~D2A and D0B~D2B, and generates complex decoding signals S0~ according to the control signals D0A~D2A and D0B~D2B. S7. In addition, a three-to-eight decoding circuit is formed by the coupling relationship between the second level control circuit 30 and the transistors of the first level control circuit 20. The control signals D0A to D2A and D0B to D2B control the transistors of the first level control circuit 20 and the second level control circuit 30 to generate the decoded signals S0 to S7. In addition, the transistors of the first level control circuit 20 may be an N-type transistor, and the transistors of the second level control circuit 30 may be a P-type transistor.

Furthermore, the first level control circuit 20 is coupled to the level conversion circuits 10 and receives the control signals D0A~D2A and D0B~D2B, and is controlled by the control signals D0A~D2A and D0B~D2B. In order to determine that the decoded signals S0~S7 have a level as a first level VGL. The plurality of second level control circuits 30 are respectively coupled to one of the level conversion circuits 10 and respectively receive one of the control signals D0A to D2A and D0B to D2B, and are controlled by the received control signal to It is determined that the levels of the other decoded signals S0 to S7 are a second level VPP.

In the above, the second level control circuits 30 respectively include transistors M2, M4, M6, M8, M10, M12, M14, M16, and control signals D0A and D0B in the control signals D0A~D2A and D0B~D2B. The transistors M2, M4 of the second level control circuit 30 are controlled to generate decoded signals S0, S1 having a second level VPP. The output circuits 40 are coupled to the decoding circuit, and generate the driving signals according to the decoding signals S0~S7. G0~G7. At least one of the output circuits 40 receives the decoded signals S0~S7 having the first level VGL to output the driving signals G0~G7 having a driving level, so at least one of the driving signals G0~G7 has a driving The level is driven to drive at least one scan line. Furthermore, the other output circuits 40 receive the decoded signals S0~S7 having the second level VPP to output the driving signals G0~G7 having a non-driving level, and control the other scanning lines. Based on the above, the first level control circuit 20 controls the driving signals G0 of one of the output circuits 40 to output the driving level, and the second level control circuit 30 controls the driving signals of the other output circuits 40 to output the non-driving level. G1~G7.

Referring to the first figure, the control signals D0B and D0A generated by the level conversion circuits 10 are used to control the plurality of transistors M1, M3, M5, and M7 that generate the decoded signals S0 to S7 in the first level control circuit 20. M9, M11, M13, M15 and second level control circuit 30, while other control signals D1B, D2B, D1A and D2A control other transistors of the first level control circuit 20, so that the level conversion circuit 10 of the present invention generates The control signals D0B and D0A control the first level control circuit 20 and the second level control circuit 30. The first level control circuit 20 and the second level control circuit 30 respectively generate the decoded signal S0~ having the first level VGL or the second level VPP by the control of the control signals D0A~D2A and D0B~D2B. S7 to drive the scan line.

For example, when the control signal D0B controls the transistor M1 to turn off, the transistor M2 is controlled to be turned on, so that the control signal D0B cuts off the decoding signal S0 to the current path of the first level VGL, and turns on the decoding signal S0 to be the second level VPP. Current path. Similarly, the control signal D0A (inversion of the control signal D0B) controls the transistor M3 to turn on when the transistor M3 is turned on, so that the control signal D0A turns on the decoding signal S1 to be a partial current path of the first level VGL, and turns off the decoding signal. S1 is the current path of the second level VPP. Therefore, the first level control circuit 20 and the second level control circuit 30 of the present invention can be controlled by The same control signal D0A (or control signal D0B) causes the driving signals G0~G7 to be at the driving level or the non-driving level. In addition, the driving level or the non-driving level of the driving signals G0~G7 respectively control the pixel transistors to be turned on or off via the scanning lines.

The output circuit 40 of the first embodiment of the driving circuit of the present invention is an inverter having an input end and an output end, the input end being coupled to the first level control circuit 20 and the second level control circuit 30, In order to receive the decoding signal S0, the inverter generates the driving signal G0 of the driving level according to the decoding signal S0 having the first level VGL, or the inverter generates the non-driving level according to the decoding signal S0 with the second level VPP. Drive signal G0.

For example, the transistor M1 in the first level control circuit 20 is coupled to one of the level conversion circuits 10, and the transistor M2 in the second level control circuit 30 is coupled to the same transistor M1. In the level conversion circuit 10, the transistor M1 is coupled to the first level VGL, and the transistor M2 receives the second level VPP. When one of the level conversion circuits 10 receives the input signal D0 of 1.8 volts, the level conversion circuit 10 generates the control signal D0B and the control signal D0A according to the input signal D0, and the control signal D0B is, for example, 0 (low level). The control signal D0A is, for example, 1 (high level), and the low level control signal D0B turns off the transistor M1 and conducts the crystal M2, so that the transistor M2 generates the decoded signal S0 with the second level VPP according to the second level VPP. (High level), the high level decoding signal S0 causes the driving signal G0 outputted by the inverter to be a non-driving level. In other words, the control signal D0B controls the transistor M2 to make the drive signal G0 a non-driving level.

Similarly, when the level conversion circuit 10 receives the input signal D0 of 0 volts, the level conversion circuit 10 generates a high level control signal D0B, and a low level control signal D0A, and the high level control signal D0B is energized. The crystal M1 is turned off and the second transistor M2 is turned off. Thus, the transistor M1 generates the decoded signal S0 having the first level VGL according to the first level VGL. Bit), the low level decoding signal S0 causes the driving signal G0 output by the inverter to be the driving level. In other words, the control signal D0B controls the transistor M1 to make the driving signal G0 a driving level. Furthermore, as shown in the first figure, the input end of the inverter of the output circuit 40 is coupled to the transistor M1 and the transistor M2, and the transistor M1 controls the driving signal G0 of the inverter output driving level, and the transistor M2 controls The inverter outputs a driving signal G0 of a non-driving level.

In addition, the level conversion circuit 10 receives the input signals D1, D2 to generate control signals D1B, D1A, D2B, D2A, control signals D1B, D1A, D2B, D2A control the other transistors in the first level control circuit 20, and the above Similar, it will not be repeated here.

Please refer to the second figure, which is a circuit diagram of a second embodiment of a driving circuit of the display panel of the present invention. As shown in the figure, the difference between the second embodiment and the first embodiment is that the output circuit 40 of the second embodiment adds a buffer circuit 41, and the output circuit 40 of the second embodiment is compared to the output circuit 40 of the first embodiment. Can consume less power. The output circuit 40 of the second embodiment includes a buffer circuit 41, a first output transistor 42 and a second output transistor 43. The snubber circuit 41 is coupled between the first transistor M1 and the second transistor M2. The first output transistor 42 has a first end, a second end, and a third end. The first end is coupled to the scans. At least one scan line of the line outputs the drive signal G0, the second end is coupled to the first level control circuit 20 via the buffer circuit 41, and the third end is coupled to the second level VPP. The second output transistor 43 has a first end, a second end and a third end. The first end is coupled to the at least one scan line and outputs the driving signal G0, and the second end is coupled to the second level via the buffer circuit 41. The control circuit 30 has a third end coupled to the first level VGL.

As described above, the transistor M1 of the first level control circuit 20 generates the low level decoded signal S0 according to the first level VGL, and the transistor M2 of the second level control circuit 30 generates the high level according to the second level VPP. Bit decode signal S0. Wherein, the first level control circuit 20 The generated low-level decoding signal S0 controls the second output transistor 43 to be turned off, and then controls the first output transistor 42 to be turned on via the buffer circuit 41. Thus, the driving signal G0 is driven according to the second level VPP. Furthermore, the high-level decoding signal S0 generated by the second level control circuit 30 controls the first output transistor 42 to be turned off, and then controls the second output transistor 43 to be turned on via the buffer circuit 41, so that the driving signal G0 is based on the first level. VGL is a non-driving level. Therefore, by the arrangement of the buffer circuit 41, the switching of the first output transistor 42 and the second output transistor 43 can be switched between off-and-off and off-power to reduce power consumption. Further, the buffer circuit 41 in the output circuit 40 may be a resistor. However, the buffer circuit 41 of the second figure is not limited to being a resistor, and the buffer circuit 41 of the second diagram of the present invention may be a plurality of transistors 44, 47 as shown in the third figure.

In view of the above, please refer to the third drawing, which is a circuit diagram of a third embodiment of the driving circuit of the display panel of the present invention. The third embodiment is different from the second embodiment in that the buffer circuit 41 of the third embodiment is changed from a resistor to a plurality of transistors 44, 47, and the remaining level shifting circuit 10, the first level control circuit 20 The second level control circuit 30 is not changed, so the level conversion circuit 10, the first level control circuit 20, and the second level control circuit 30 are not repeatedly shown. As shown in the third figure, the transistor 44 is connected in series with the transistor M2. The transistor 47 is coupled to the transistor M2 and connected in parallel with the transistor 44. The transistors 44 and 47 are coupled to the first output transistor 42 and the second output. The crystal 43 and the transistors 44, 47 can be controlled by a circuit, for example, by a bias circuit 50. The bias circuit 50 generates a bias signal Bias, and the bias signal Bias controls the transistors 44, 47 to make electricity. The crystals 44, 47 operate in a resistive region and the transistors 44, 47 act as a resistor. As such, the switching of the first output transistor 42 and the second output transistor 43 can also be asynchronous switching. In addition, the transistor M2 can be combined with the first output transistor 42 and the second The output transistor 43 and the transistors 44, 47 are designed together in the output circuit 40. Therefore, the present invention does not limit the design scope of the second level control circuit 30.

Referring to the second and third figures, in this embodiment, the high level of the control signals D0B, D0A is designed to be lower than the level of the second level VPP, so that the transistor M2 operates in the resistance region and a current flows. Therefore, when the first level control circuit 20 provides the first level VGL-current path, the decoded signal S0 is the first level VGL. When the first level control circuit 20 does not provide the first level VGL-current path, the level of the decoded signal S0 is pulled to the second level VPP due to the current generated by the transistor M2 operating in the resistance region, thus driving Signal G0 can be maintained at a non-driving level. In addition, this embodiment designs the high level of the other control signals D1B, D1A, D2B, and D2A to the level of the second level VPP.

Please refer to the fourth figure, which is a circuit diagram of a fourth embodiment of the driving circuit of the display panel of the present invention. As shown in the figure, the fourth embodiment is different from the first embodiment and the second embodiment in that the transistors of the first level control circuit 20 of the fourth embodiment are a P-type transistor, and The level control circuit 20 generates the decoded signals S0 to S7 according to the second level VPP. The design of the second level control circuit 30 and the output circuit 40 is also different. Please refer to the fifth figure.

Please refer to the fifth figure, which is a circuit diagram of an embodiment of the second level control circuit and the output circuit of the present invention. As shown, the transistor M2 is coupled between the first level control circuit 20 (fourth figure) and the first level VGL. The output circuit 40 includes a buffer circuit 41, a first output transistor 42, a second output transistor 43, a third output transistor 45, and a fourth output transistor 46. The first output transistor 42 is coupled to the second level VPP, the second output transistor 43 is coupled to the first output transistor 42 and the first level VGL, and the third output transistor 45 is coupled to the second level VPP and the first An output transistor 42 , the fourth output transistor 46 is coupled to the first level VGL and the second output transistor 43 , and the buffer circuit 41 is coupled Between the third output transistor 45 and the fourth output transistor 46. The first output transistor 42 outputs a driving signal G0 having a driving level according to the second level VPP, and the second output transistor 43 outputs a driving signal G0 having a non-driving level according to the first level VGL.

Referring to the fourth and fifth figures, in this embodiment, the low level of the control signals D0B, D0A is designed to be higher than the level of the first level VGL, so that the transistor M2 operates in the resistance region and a current flows. Therefore, when the first level control circuit 20 provides the second level VPP-current path, the decoded signal S0 is the second level VPP. When the first level control circuit 20 does not provide the second level VPP-current path, the level of the decoded signal S0 is pulled to the first level VGL due to the current generated by the transistor M2 operating in the resistor region, thus driving the signal G0 can be maintained at a non-driving level. In addition, this embodiment designs the low level of the other control signals D1B, D1A, D2B, and D2A to the level of the first level VGL.

In response to the above, the third output transistor 45 and the fourth output transistor 46 are controlled by the decoding signal S0, and the transistor M2 is controlled by the control signal D0A. After the fourth output transistor 46 is turned on by the high-level decoding signal S0, the first level VGL controls the first output transistor 42 to be turned on, so that the output circuit 40 can generate the driving signal G0 having the driving level. Furthermore, after the control signal D0A controls the transistor M2 to be turned on, the first level VGL controls the third output transistor 45 to be turned on, and the second level VPP controls the second output transistor 43 to be turned on, so that the output circuit 40 can be The first level VGL generates a drive signal G0 having a non-driving level.

Please refer to the sixth drawing, which is a circuit diagram of a fifth embodiment of a driving circuit of the display panel of the present invention. As shown, the fifth embodiment is different from the first embodiment in that the second level control circuit 30 of the fifth embodiment is controlled by the bias signal Bias instead of the control signals D0B, D0A. In other words, the transistor M2 is coupled to the bias circuit 50 (as shown in the third figure), and the bias signal Bias control transistor M2 is generated with the second The decoded signals of the VPP are S0~S7. Furthermore, the buffer circuit 41 of the fifth embodiment can be changed from a resistor to a transistor 44 (third diagram), and the transistor 44 is also controlled by a signal generated by the bias circuit 50 (third diagram). However, the signal of the control transistor 44 is such that the transistor 44 operates in the resistance region, and the bias signal Bias of the second level control circuit 30 is controlled so that the decoded signal S0 is at a high level, so that the signals of the control transistor 44 are different. The bias signal Bias of the second level control circuit 30 is controlled.

In addition, the first level control circuit 20 of the fifth embodiment is composed of an N-type transistor, but as described in the previous embodiment, the first level control circuit 20 may be composed of a P-type transistor, please refer to the seventh figure. It is a circuit diagram of a sixth embodiment of a driving circuit of the display panel of the present invention. As shown in the figure, the difference between the sixth embodiment and the fifth embodiment is that the first level control circuit 20 of the sixth embodiment is composed of a P-type transistor, wherein the design of the second level control circuit 30 and the output circuit 40 is shown. Also varies, please refer to the eighth picture.

Please refer to the eighth figure, which is a circuit diagram of a second embodiment of the output circuit of the present invention. As shown in the figure, the difference between this embodiment and the fifth embodiment is that the output circuit 40 of the present embodiment does not include a resistor. However, the output circuit 40 of the present embodiment includes a first output transistor 42, a second output transistor 43, a third output transistor 45, and a fourth output transistor 46. The third output transistor 45 is coupled to the first level control circuit 20 (the seventh figure) and the second level control circuit 30. The fourth output transistor 46 is connected in series with the third output transistor 45 and coupled to the first standard. The bit control circuit 20 and the second level control circuit 30. The first level control circuit 20 or the second level control circuit 30 controls the fourth output transistor 46 to switch with the third output transistor 45. Furthermore, the output circuit 40 is coupled between the first level control circuit 20 and at least one of the scan lines. The first level control circuit 20 controls the output circuit 40, and the output circuit 40 controls the drive signal G0. for Drive level. In addition, the output circuit 40 controls the driving signal G0 to be a non-driving level according to the second level VPP.

In addition, in the eighth embodiment, the transistor M2, the first output transistor 42, the second output transistor 43, the third output transistor 45, and the fourth output transistor 46 may be integrated into the output circuit 40. Therefore, the present invention does not limit the design scope of the output circuit 40. Furthermore, for convenience of description, the second level of each embodiment of the present invention is VPP and the first level is VGL for illustration, but the second level of the present invention may be changed to VGH or Bias, and the first standard The bit can be changed to GND, so the level of the first level and the second level of the present invention can be changed according to the design requirements, and the second level and the first level are modified by referring to the circuit of the present invention. source.

Please refer to the ninth drawing, which is a waveform diagram of a second embodiment of the driving circuit of the display panel of the present invention. As shown in the figure, the waveforms of the driving signals G0 and G1 generated by the level conversion circuit 10, the first level control circuit 20, the second level control circuit 30, and the output circuit 40 drive the falling edge of the signal G0 and The rising edges of the driving signal G1 are interlaced at a slightly lower position, and the staggered position may be different via the design of the output circuit 40. For example, because the waveforms of the two signals are staggered, the gate of the panel can be opened earlier, so that the source has more time to charge, especially in the high-resolution panel, the charging time of the source is quite short. Early control of the gate opening allows more time for the source to charge.

In summary, the driving circuit of the display panel of the present invention comprises a complex level conversion circuit, a decoding circuit and a complex output circuit. The decoding circuit comprises a first level control circuit and a plurality of second level control circuits. The level conversion circuit generates a plurality of control signals; the first level control circuit receives the control signals to determine that the level of at least one of the plurality of decoded signals is a first level; the second level control circuits respectively Receive this One of the control signals is used to determine the level of the other decoded signals as a second level; and the output circuits generate the driving signals according to the decoded signals, and at least one of the driving signals has a driving Level to drive at least one scan line.

The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the variations, modifications, and modifications of the shapes, structures, features, and spirits described in the claims of the present invention. All should be included in the scope of the patent application of the present invention.

10‧‧‧bit conversion circuit

40‧‧‧Output circuit

41‧‧‧ buffer circuit

42‧‧‧First output transistor

43‧‧‧Second output transistor

D0~D2‧‧‧ input signal

D0A, D0B, D1A, D1B, D2A, D2B‧‧‧ control signals

G0~G7‧‧‧ drive signal

M1~M16‧‧‧O crystal

S0~S7‧‧‧ decoding signal

VGL‧‧‧ first position

VPP‧‧‧ second position

Claims (13)

A driving circuit for a display panel, the driving circuit generates a plurality of driving signals for driving at least one scanning line, the driving circuit comprising: a complex level conversion circuit, receiving a plurality of input signals, and converting the levels of the input signals to generate a plurality of control signals; a decoding circuit coupled to the level conversion circuits and receiving the control signals, and generating a complex decoding signal according to the control signals, the decoding circuit comprising: a first level control circuit coupled The level conversion circuit receives the control signals and is controlled by the control signals to determine that the level of at least one of the decoded signals is a first level or a second level; The second level control circuit is coupled to one of the level conversion circuits, and respectively receives one of the control signals, and is controlled by the received control signal to determine the quasi-other of the decoded signals. If the bit is the second level or the first level, when the first level control circuit determines that the level of the at least one of the decoded signals is the first level, the second level The control circuit determines that the levels of the other decoded signals are the second level, and when the first level control circuit determines that the level of the at least one of the decoded signals is the second level, the second The level control circuit determines that the levels of the other decoded signals are the first level; and the plurality of output circuits are coupled to the decoding circuit, and generate the driving signals according to the decoded signals, and the driving signals are at least Having a driving level to drive the at least one scan line, at least one of the output circuits receiving the decoded signal having the first level or the second level determined by the first level control circuit to Output has The driving signal of the driving level. The driving circuit of the display panel of the first aspect of the invention, wherein the output circuit is an inverter, the inverter has an input end and an output end, and the input end is coupled to the first level control The circuit and one of the second level control circuits, the input end receiving the decoded signal determined by the first level control circuit having the first level or receiving the second level control circuit The decoding signal of the second level, the inverter generates the driving signal of the driving level according to the decoding signal having the first level, or the inverter according to the decoding signal having the second level The drive signal is generated at a non-drive level. The driving circuit of the display panel of claim 1, wherein the output circuit comprises: a buffer circuit coupled between the first level control circuit and the second level control circuit; An output transistor having a first end, a second end, and a third end, the first end coupled to the at least one scan line and outputting the driving signal, wherein the second end is coupled to the first via the buffer circuit a level control circuit, the third end is coupled to the second level; and a second output transistor having a first end, a second end, and a third end, the first end coupled to the at least a scan line is coupled to the second level control circuit, the third end is coupled to the first level control circuit, wherein the third end is coupled to the first level; wherein the buffer circuit causes the first output to be electrically The switching of the crystal and the second output transistor is asynchronous switching. The driving circuit of the display panel according to claim 3, wherein the buffer circuit is a resistor or a transistor. The driving circuit of the display panel according to claim 1, wherein the output circuits comprise: a first output transistor coupled to the second level; a second output transistor coupled to the first output transistor and the first level; a third output transistor coupled to the second level And the first output transistor; a fourth output transistor coupled to the first level and the second output transistor; and a buffer circuit coupled to the third output transistor and the fourth output Between the transistors, wherein the first output transistor outputs the driving signal having the driving level according to the second level, and the second output transistor outputs a non-driving level according to the first level output. The drive signal. The driving circuit of the display panel of claim 1, wherein the output circuits comprise a buffer circuit, a first output transistor and a second output transistor, wherein the first level control circuit controls the first After the output transistor is turned off, the first output transistor is controlled to be turned on by the buffer circuit, and the driving signal is the driving level, and the second level control circuit controls the first output transistor to be turned off, and the buffer circuit is turned on. The second output transistor is controlled to be turned on, and the driving signal is a non-driving level. The driving circuit of the display panel of claim 1, comprising: a bias circuit for generating a bias signal; wherein the output circuits comprise a buffer circuit, a first output transistor and a a second output transistor, the bias signal controlling the buffer circuit to switch the first output transistor and the second output transistor to be asynchronously switched. The driving circuit of the display panel of claim 1, wherein the falling edge of the first driving signal of one of the driving signals and the rising edge of the second driving signal of the driving signals are interdigitated. When the crystal is not completely turned off by the first driving signal, the second driving signal turns on another transistor to charge the other transistor early. A driving circuit for displaying a panel, the driving circuit generating a plurality of driving signals for driving at least one scan line of the display panel, the driving circuit comprising: a plurality of level conversion circuits, receiving the plurality of input signals, and converting the bits of the input signals And generating a complex control signal; a decoding circuit coupled to the level conversion circuits and receiving the control signals, and generating a complex decoding signal according to the control signals, the decoding circuit comprising: a first level control The circuit is coupled to the level conversion circuits and receives the control signals, and is controlled by the control signals to determine that the level of at least one of the decoded signals is a first level or a second And a plurality of second level control circuits coupled to a bias signal and controlled by the bias signal to determine the level of the other decoded signals as the second level or the first standard a bit, when the first level control circuit determines that the level of the at least one of the decoded signals is the first level, the second level control circuits determine the positions of the other decoded signals The second level control circuit determines the order of the other decoded signals when the first level control circuit determines that the level of the at least one of the decoded signals is the second level The bit is the first level; the plurality of buffer circuits are respectively coupled to the first level control circuit and the second level control circuit, and the first level control circuit controls the driving signal to be a driving standard via the buffer circuit The second level control circuit controls the driving signal to be a non-driving level via the buffer circuit; and the plurality of output circuits are coupled to the decoding circuit, and generate the driving signals according to the decoding signals, and the driving signals are generated. At least one of the signals has the driving level to drive the at least one scan line, and at least one of the output circuits receives the decoding determined by the first level control circuit having the first level or the second level a signal to output the driving signal having the driving level; The driving level and the non-driving level are respectively used to control the scan line. The driving circuit of the display panel of claim 9, comprising: a bias circuit for generating the bias signal, the bias signal controlling the second level control circuits to generate the The second level or the decoded signals of the first level. The driving circuit of the display panel of claim 9, wherein the output circuits respectively comprise a first output transistor and a second output transistor, the buffer circuit being a resistor, the resistor The switching of the first output transistor and the second output transistor is asynchronous switching. The driving circuit of the display panel of claim 9, wherein the output circuits respectively comprise one of the second level control circuits, a first output transistor, a second output transistor, and a first a third output transistor and a fourth output transistor, wherein the output circuits are respectively coupled between the first level control circuit and the scan lines, and the first level control circuit controls the output circuits to enable the The driving signals are the driving levels, and the output circuits control the driving signals to be the non-driving level according to the second level control circuits. The driving circuit of the display panel of claim 9, wherein the falling edge of the first driving signal of one of the driving signals is interleaved with the rising edge of the second driving signal of the driving signals, when an electric When the crystal is not completely turned off by the first driving signal, the second driving signal turns on another transistor to charge the other transistor early.